TRC102 Range Test at 433.92MHz By Scott Shoaf, RFIC Product Engineer, RF Monolithics, Dallas, TX Disclaimer: This test is intended to provide a benchmark for range performance of the TRC102. Each operating environment will differ with each having unique obstacles for RF propagation to contend with. The TRC102 has +7dBm (5mW) of output power and the best receive sensitivity of our RFIC line of short range radios. The performance at 433.92 MHz is used as a baseline for range test characterization between 315MHz and 916MHz. From this, one can gain an idea of how much line-of-sight range to expect depending upon the frequency of operation and the operating environment. In the U.S., FCC part 15 limits transmission output power to 0dBm (1mW) for short range, unlicensed radio applications. The output power of the TRC102 is adjustable which allows for testing and operation at other power levels. Since the FCC limit is 0dBm, the output power on the TRC102 was adjusted down -6dB from the peak power level. The setup parameters for the Transmitter, using the RFDA, were as follows: Freq – 433.92MHz Oscillator Enabled Synthesizer Enabled Clock Output Disabled Pin 8 – Data Detector Output PLL Dithering On Crystal Load – 8.5pF FSK Deviation – 15kHz Pout - -6dB (0 dBm) Polarity of Modulation – Fo+df Clock Buffer Slew - >5MHz Data Rate – 2400 (19200) -Prescaler Enabled (Disabled) -R=17 For the above Transmitter settings, the respective register values are as follows: Configuration - 0x8010 Frequency setting – 0xA620 Power Management – 0x8219 (Transmitter Off), 0x8239 (Transmitter On) Receiver Setting – N/A Transmitter Setting – 9800 Synch Character – 0xCEE2 PLL Command – 0xCC06 AFC Command – 0xC4E7 Data Rate Command – 0xC691 Data Filter Command – N/A FIFO Buffer Cmd – N/A 1/30/2007 The setup parameters for the Receiver, using the RFDA, were as follows: Freq – 433.92MHz Oscillator Enabled Synthesizer Enabled Clock Output Disabled Pin 8 – Data Detector Output PLL Dithering On Crystal Load – 8.5pF LNA Gain – Max DRSSI - -103dBm Baseband BW – 67kHz Valid Data Detector – Medium Synch Charac Byte – E2 (Programmable) Clock Buffer Slew - >5MHz AFA Enabled -Fine Mode Enabled -Mode – Auto, keep offset -Tuning - +7/-8 Fres -Output Enabled Data Rate – 2400 (19200) -Prescaler Enabled (Disabled) -R=17 Data Filter -Clock Recovery – Slow -Filter Type – Digital LPF -DQD – 4 FIFO Buffer -Enable Synch Latch -Disable Sensitive Reset -FIFO Fill Start – Synch Pattern -FIFO IT level – 8 For the above Receiver settings, the respective register values are as follows: Configuration - 0x8010 Frequency setting – 0xA620 Power Management – 0x82D9 (Receive and Baseband On) Receiver Setting – 0x95C0 Transmitter Setting – N/A Synch Character – 0xCEE2 PLL Command – 0xCC06 AFC Command – 0xC4E7 Data Rate Command – 0xC691 Data Filter Command – 0xC22C FIFO Buffer Cmd – 0xCA83 1/30/2007 All tests were conducted using the antenna soldered to a DR-TRC102-433 evaluation board. The data rate was configured to 2.4kbps. A data payload of 35 bytes was transmitted, including a 2 byte preamble. The first test uses a simple λ/4 monopole at 433.92MHz on both transmitter and receiver. The transmitter was mounted at a height of 3m (10ft). The receiver was held at 1.5m high as the distance between the two were increased. A line-of-sight range of 675m (2217ft) was achieved using the monopole antenna. The second test uses RFM’s loaded monopole at 433.92MHz on both transmitter and receiver. This is the same antenna used on the DR-1300A-DK ASH Development Kit. The transmitter was mounted at a height of 3m (10ft). The receiver was also held at 1.5m high as the distance between the two were increased. A line-of-sight range of 725m (2376ft) was achieved using the loaded monopole antenna. This data shows that operating the TRC102 at max power (+7dBm), a range of >1000m is achievable. The evaluation boards were not specifically designed to optimize use with an antenna. The evaluation board does not provide a “balanced” ground plane for use with a monopole antenna structure, thus, a PCB design that is optimized for a monopole, using a λ/4 radiating element centered in a ground plane, would theoretically give an additional range of 15-30m (50-100ft). Range λ/4 Monopole End Loaded Monopole Max >1000m >1000m +0dBm 675m(2271ft) 725m (2376ft) 1/30/2007 Receiver Range Test Assembly Code for C8051F330: $include (c8051f330.inc) ;-- Bit Addressable RXFLG EQU STATFLG EQU 00H 01H ;RX FLAG AT REG 20H, BIT 0 ;STATUS READ FLAG AT REG 20H, BIT 1 ;-- Byte Addressable HIGHBYTE EQU LOWBYTE EQU TBLOFF EQU CNT EQU CHKSMH EQU RXBUF EQU 21H 22H 23H 24H 25H 26H ;HIGH BYTE OF IC WORD ;LOW BYTE OF IC WORD ;Table offset value ;byte count ;CHECKSUM HIGH BYTE ;RX BUFFER AREA TO 46h ;PORT 0-----------------------RXLED EQU P0.0 ACKLED EQU P0.1 SLPLED EQU P0.2 TXLED EQU P0.3 ;O LED ;O LED ;O LED ;O LED 1 P/P 1 P/P 1 P/P 1 P/P 0 0 0 0 RS232TX RS232RX SCK SDO ;O ;I ;O ;I 1 P/P 0 O/D 1 P/P 0 O/D 1 1 0 1 ;O ;O ;I ;O ;O LED ;I ;I ;I (or INT) ;I 1 P/P 0 1 P/P 1 0 O/D 1 1P/P 0 EQU EQU EQU EQU P0.4 P0.5 P0.6 P0.7 ;PORT 1-----------------------SDI EQU P1.0 SEL EQU P1.1 IRQ EQU P1.2 FSEL EQU P1.3 ;LED EQU P1.3 FFULL EQU P1.4 RSSI EQU P1.5 DDET EQU P1.6 RNGTST EQU P1.7 ORG LJMP ORG 0 O/D 0 O/D 0 O/D 0 O/D 1 1 1 1 00h MAIN 0FFh ;------ Initialization functions ----------------MAIN: mov PCA0MD, #00h Port_IO_Init: mov mov mov mov mov mov mov mov P0MDOUT, #05Fh ;0101 1111 P1MDOUT, #0Bh;0000 1011 P0SKIP, #00Fh P0, #0B0h ;1011 0000 P1, #0F6h ;1111 0110 P2, #000h XBR0, #003h ;0000 0011 XBR1, #040h ;0100 0000 Timer1_Init: mov TMOD, #021h mov TH1, #0CBh MOV TL1, mov CKCON, #00h ;TMR1 Mode 2(2 8-bit), TMR0 Mode 1(16-bit) ;UART Reload value for 19.2Baud #0CBH ;INIT TMR1 ;SYSCLK/12 UART_Init: mov SCON0, ;RXEN,RX INT active on stop bit #030h SPI_Init: mov SPI0CFG, #047h 1/30/2007 mov SPI0CN, #0Fh mov SPI0CKR, #000H Oscillator_Init: mov OSCICN, #80h ;CLK = 3.06/2 = 1.5 MHz ;SYSCLK = 24.5 MHz/8 = 3.0MHz Interrupts_Init: mov PCA0MD,#00h MOV EIE1,#80h SETB PSPI0 SETB EA ;Main Code Section*********************************** mov mov mov mov mov mov mov mov R0,#00h R1,#00h R2,#00h R3,#00h R4,#00h R5,#00h R6,#00h R7,#00h CLR CLR STATFLG RXFLG ;CLEAR REGISTERS ; ; ; ; ; ; ; ;Flash LED's ON STARTUP SETB RXLED ;TURN ON LED SETB TR0 ;TMR0 ENABLED NXT: JNB TF0,NXT ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG SETB TXLED ;TURN ON LED NXT1: JNB TF0,NXT1 ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG SETB ACKLED ;TURN ON LED NXT2: JNB TF0,NXT2 ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG SETB SLPLED ;TURN ON LED NXT3: JNB TF0,NXT3 ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG CLR RXLED CLR TXLED CLR ACKLED CLR SLPLED ;TURN OFF LED CLR TR0 ;TMR0 DISABLED ;---------------------------------------------------------------;TEST IF JUMPER INSTALLED FOR DATA RATE JNB RNGTST,CFG2 ;Configure Device FOR 2.4KBPS CFG1: mov XBR1,#0C0h ;DIS WEAK PULLUPS mov CNT,#0Dh ;LOAD BYTE COUNT mov DPTR,#RXSETUP2400 ;load table pointer mov TBLOFF,#0 ;set offset value A1: mov A,TBLOFF ;load offset value mov R1,#HIGHBYTE ;load buffer with HIGHBYTE ADDRESS movc A,@A+DPTR ;load table byte mov @R1,A ;...into buffer inc TBLOFF ;incr offset inc R1 ;incr buffer to LOWBYTE ADDRESS 1/30/2007 mov A,TBLOFF ;load offset value movc A,@A+DPTR ;load table byte mov @R1,A ;...into buffer inc TBLOFF MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND ;DO ACTUAL SPI TRANSACTION MOV SPI0CN,#00Dh ;SET nSEL HIGH (DESELECT CHIP) djnz CNT,A1 ;DECREMENT BYTE COUNTER SJMP START ;---------------------------------------------------------------;Configure Device 19.2KBPS CFG2: mov XBR1,#0C0h ;DIS WEAK PULLUPS mov CNT,#0Dh ;LOAD BYTE COUNT mov DPTR,#RXSETUP19200 ;load table pointer mov TBLOFF,#0 ;set offset value RA1: mov A,TBLOFF ;load offset value mov R1,#HIGHBYTE ;load buffer with HIGHBYTE ADDRESS movc A,@A+DPTR ;load table byte mov @R1,A ;into buffer inc TBLOFF ;incr offset inc R1 ;incr buffer to LOWBYTE ADDRESS mov A,TBLOFF ;load offset value movc A,@A+DPTR ;load table byte mov @R1,A ;into buffer inc TBLOFF MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND ;DO ACTUAL SPI TRANSACTION MOV SPI0CN,#00Dh ;SET nSEL HIGH (DESELECT CHIP) djnz CNT,RA1 ;DECREMENT BYTE COUNTER ;---------------------------------------------------------------;******************************************************** ;******************* MAIN LOOP *********************** ;******************************************************** START: CLR A ;CLEAR ACC CLR CHKSMH ;CLEAR CHECKSUM HIGH BYTE MOV CNT,#1FH ;LOAD BYTE COUNT MOV R1,#RXBUF ;LOAD ADDR OF FIRST BUFFER LOC XX1: JNB DDET,XX1 ;WAIT FOR VALID DATA Z1: JNB FFULL,Z1 ;TEST IF DATA IN FIFO READY ;------------------------------------------------------------;BEGIN DATA RX ;**REFER TO RECOMMENDED READ PROCESS IN DATASHEET ; 1-PULL nCS "HIGH" ; 2-PULL FSEL "LOW" ; 3-WAIT FOR FINT TO GO "HIGH" INDICATING RX DATA RDY ; 4-WRITE A DUMMY BYTE TO THE SPI AND READ FIFO DATA BACK ;------------------------------------------------------------UNO: SETB ACKLED MOV SPI0DAT,#00H ;WRITE DUMMY BYTE TO SPI WAIT3: JNB SPIF, WAIT3 ;WAIT FOR SPI DONE CLR SPIF ;RESET FLAG MOV @R1,SPI0DAT ;WRITE BYTE TO RX BUFFER LOC INC R1 DJNZ CNT,Z1 ;DECREMENT COUNT. BAIL IF ALL BYTES RX LJMP COMPARE ;IF ALL BYTES READ THEN COMPARE ;------------------------------------------------------------;COMPARE THE RX DATA TO DATA IN MEMORY ;------------------------------------------------------------COMPARE: ;COMPARE READ VALUES TO THOSE IN MEM mov CNT,#1Eh ;LOAD RX DATA COUNTER mov R1,#RXBUF ;load table pointer mov DPTR,#TXDATA ;load table pointer CLR A 1/30/2007 HERE: MOVC mov CJNE INC INC CLR DJNZ A,@A+DPTR B,@R1 A,B,RESTART DPTR R1 A CNT,HERE ;------------------------------------------------------------;FLASH GREEN LED IF DATA GOOD ;------------------------------------------------------------SETB SLPLED ;TURN ON LED MOV TL0,#00H MOV TH0,#0E0H SETB TR0 ;TMR0 ENABLED ;CLEAR BUFFER MOV CNT,#20h ;LOAD BYTE COUNT MOV R1,#RXBUF ;LOAD ADDR OF FIRST BUFFER LOC X2: MOV @R1,#00h INC R1 DJNZ CNT,X2 ;--- THIS RESETS THE SYNCH CHARAC RECOGNITION ----mov HIGHBYTE,#0CAH MOV LOWBYTE,#81H ;LOAD FIFO/RESET CONFIG REG MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND ;CLEAR SYNCH CHAR RECOG MOV SPI0CN,#00Dh ;SET nSEL HIGH (DESELECT CHIP) MOV LOWBYTE,#83H ;LOAD FIFO/RESET CONFIG REG MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND ;RESET FIFO FILL ON SYNCH CHAR MOV SPI0CN,#00Dh ;SET nSEL HIGH (DESELECT CHIP) ;-----------------------------------------------------WT: JNB TF0,WT ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG CLR SLPLED ;TURN OFF LED CLR TR0 YR1: JB DDET,YR1 ;WAIT FOR VALID DATA INACTIVE CLR ACKLED ;TURN OFF LED LJMP START ;------------------------------------------------------------;------------------------------------------------------------; FLASH RED LED IF BAD DATA ;------------------------------------------------------------RESTART: ;CLEAR BUFFER AND FLASH ERR LED SETB TXLED ;TURN ERR LED ON MOV TL0,#00H MOV TH0,#0C0H SETB TR0 ;TMR0 ENABLED ;CLEAR BUFFER RST: MOV CNT,#20h ;LOAD BYTE COUNT MOV R1,#RXBUF ;LOAD ADDR OF FIRST BUFFER LOC X1: MOV @R1,#00h INC R1 DJNZ CNT,X1 ;--- THIS RESETS THE SYNCH CHARAC RECOGNITION ----mov HIGHBYTE,#0CAH MOV LOWBYTE,#81H ;LOAD FIFO/RESET CONFIG REG MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND ;CLEAR SYNCH CHAR RECOG MOV SPI0CN,#00Dh ;SET nSEL HIGH (DESELECT CHIP) MOV LOWBYTE,#83H ;LOAD FIFO/RESET CONFIG REG MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND ;RESET FIFO FILL ON SYNCH CHAR MOV SPI0CN,#00Dh ;SET nSEL HIGH (DESELECT CHIP) ;-----------------------------------------------------WT2: 1/30/2007 JNB TF0,WT2 ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG CLR TXLED ;TURN OFF ERR LED CLR TR0 XR1: JB DDET,XR1 ;WAIT FOR VALID DATA INACTIVE CLR ACKLED LJMP START ;------------------------------------------------------------- ; ************************ SPI SEND ******************************************* SPISEND: ;(Chip Select already LOW) MOV SPI0DAT,HIGHBYTE ;WRITE HIGH BYTE TO SPI WAIT4: JNB SPIF,WAIT4 ;WAIT FOR SPI TO FINISH FIRST XFER,LOOP IF STILL BUSY CLR SPIF ;CLEAR SPI INT FLAG TO PROCEED MOV SPI0DAT,LOWBYTE ;WRITE LOW BYTE TO SPI WAIT5: JNB SPIF,WAIT5 ;WAIT FOR SPI TO FINISH 2ND XFER,LOOP IF STILL BUSY CLR SPIF ;CLEAR SPI INT FLAG TO PROCEED RTRN: CLR ACKLED RET ; ****************************************************************************** RXSETUP2400: DB 80h DB 67h ;config reg DB 0A6h DB 40h ;Freq set DB 96H DB 0a0H ;RX set DB 98h DB 00h ;TX set DB 0CEh DB 0D4H ;Synch Char DB 0CCh DB 06h ;PLL cmd DB 0C6h DB 91h ;Data Rate 2.4Kbps DB 0C4h DB 0D7h ;AFA DB 0CAh DB 83h ;RX FIFO (FILL ALWAYS 87H) (SYNCH CHAR 83H) DB 0C2h DB 2Ch ;Baseband Filter DB 82h DB 0D9h ;Pwr mng ;TURN ON RX DB 82h DB 049h ;Pwr mng ;TURN OFF SYNTH (CALIBRATE) DB 82h DB 0D9h ;Pwr mng ;TURN ON SYNTH (CALIBRATE) RXSETUP19200: DB 80h 1/30/2007 DB 67h ;config reg DB 0A6h DB 40h ;Freq set DB 96H DB 0C0H ;RX set DB 98h DB 00h ;TX set DB 0CEh DB 0D4H ;Synch Char DB 0CCh DB 06h ;PLL cmd DB 0C6h DB 11h ;Data Rate 19.2Kbps DB 0C4h DB 0D7h ;AFA DB 0CAh DB 83h ;RX FIFO (FILL ALWAYS 87H) (SYNCH CHAR 83H) DB 0C2h DB 2Ch ;Baseband Filter DB 82h DB 0D9h ;Pwr mng DB 82h DB 0C9h ;Pwr mng ;TURN OFF SYNTH (CALIBRATE) DB 82h DB 0D9h ;Pwr mng ;TURN ON SYNTH (CALIBRATE) TXDATA: DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB '' 'R' 'F' 'M' '' 'R' 'F' 'I' 'C' '' 'R' 'A' 'N' 'G' 'E' '' 'T' 'E' 'S' 'T' '' '4' '3' '3' '.' '9' '2' '' 'M' 'H' 1/30/2007 DB 'z' END 1/30/2007 Transmitter Range Test Assembly Code for C8051F330: $include (c8051f330.inc) ;-- Bit Addressable RXFLG EQU STATFLG EQU 00H 01H ;RX FLAG AT REG 20H, BIT 0 ;STATUS READ FLAG AT REG 20H, BIT 1 ;-- Byte Addressable HIGHBYTE EQU LOWBYTE EQU TBLOFF EQU CNT EQU 21H 22H 23H 24H ;HIGH BYTE OF IC WORD ;LOW BYTE OF IC WORD ;Table offset value ;byte count ;PORT 0-----------------------RXLED EQU ACKLED EQU SLPLED EQU TXLED EQU P0.0 P0.1 P0.2 P0.3 ;O LED ;O LED ;O LED ;O LED RS232TX RS232RX SCK SDO P0.4 P0.5 P0.6 P0.7 ;O ;I ;O ;I 1 P/P 0 O/D 1 P/P 0 O/D 1 1 0 1 P1.0 P1.1 P1.2 P1.3 P1.3 P1.4 P1.5 P1.6 P1.7 ;O ;O ;I ;O ;O LED ;I ;I ;I (or INT) ;I 1 P/P 1 P/P 0 O/D 1 P/P 0 1 1 1 0 O/D 0 O/D 1 0 O/D 1 1 EQU EQU EQU EQU ;PORT 1-----------------------SDI EQU SEL EQU IRQ EQU FSEL EQU ;LED EQU DCLK EQU RSSI EQU VDDET EQU RNGTST EQU ORG LJMP 00h MAIN ORG LJMP 73H INTT 1 P/P 1 P/P 1 P/P 1 P/P 0 O/D 0 0 0 0 1 ;TMR3 interrupt ORG 0FFh ;**** UART ISR ******************* ; THE TRANSMIT IS PERFORMED ON A TIMER INTERRUPT. INTT: mov TMR3CN,#00h ;TMR3 OFF ;Transmit Packet ;Turn on Transmitter and begin TX preamble while loading other data mov HIGHBYTE,#82h ;load SPI address mov LOWBYTE,#39h ;Load SPI data, Turn on TX MOV SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) ACALL SPISEND SETB TXLED ;Turn on LED ;Begin loading data payload mov HIGHBYTE,#0B8h MOV SPI0DAT,HIGHBYTE W2:JNB SPIF,W2 CLR SPIF mov CNT,#25h mov DPTR,#TXDATA mov TBLOFF,#0 Z1: mov A,TBLOFF mov R1,#LOWBYTE movc A,@A+DPTR mov @R1,A inc TBLOFF MOV SPI0DAT,LOWBYTE ;load address of TX reg ;ADDRESS THE TX REG ;WAIT FOR SPI TO FINISH ;CLEAR SPI INT FLAG ;load byte count(35) ;load table pointer ;set offset value ;load offset value ;load buffer pointer ;load table byte ;..into LOWBYTE buffer ;incr offset ;WRITE DATA BYTE TO SPI 1/30/2007 W3: JNB CLR SPIF,W3 SPIF ;WAIT FOR SPI TO FINISH ;CLEAR SPI INT FLAG JNB djnz MOV mov mov MOV ACALL CLR SDO,LP CNT,Z1 SPI0CN,#00Dh HIGHBYTE,#82h LOWBYTE,#19h SPI0CN,#009h SPISEND TXLED ;loop until next byte load ;SET nSEL HIGH (DESELECT CHIP) TO WRITE TO NEW REGISTER ;load address ;Load data, Turn OFF TX ;SET nSEL LOW (CHIP SELECT) mov MOV TMR3CN,#04h SPI0CN,#00Dh ;TMR3 en ;SET nSEL HIGH (DESELECT CHIP) LP: ;Turn off LED DN: RETI ;RETURN ;************************************************************************************************ ;------ Initialization functions ----------------MAIN: mov mov mov mov mov mov mov mov mov PCA0MD, #000h P0MDOUT, #05Fh P1MDOUT, #0Bh P0SKIP, #00Fh P0, #0B0h P1, #0FEh P2, #000h XBR0, #003h XBR1, #040h ;0101 1111 ;0000 1011 ;1111 1110 Timer1_Init: mov mov MOV mov mov TMOD, #021h TH1, #0CBh TL1, #0CBH CKCON, #00h TCON, #040h ;TMR1 Mode 2(2 8-bit), TMR0 Mode 1(16-bit) ;UART Reload value for 19.2Baud ;INIT TMR1 ;SYSCLK/12 ;TMR1 En Timer3_Init: MOV MOV MOV TMR3CN, #00h TMR3RLH, #090h TMR3RLL, #00h ;TMR3 dis, TMR3 clk = 255.208kHz,TMR3 MODE 16-BIT AUTORELD UART_Init: mov SCON0, ;RXEN,RX INT active on stop bit SPI_Init: mov mov mov SPI0CFG, #040h SPI0CN, #00Dh SPI0CKR, #00H Oscillator_Init: mov OSCICN, Interrupts_Init: mov MOV SETB SETB #030h #80h ;SYSCLK = 24.5 MHz/8 = 3.06 MHz PCA0MD,#00h EIE1,#80h PSPI0 EA ;Main Code Section*********************************** mov mov mov mov mov mov mov R0,#00h R1,#00h R2,#00h R3,#00h R4,#00h R5,#00h R6,#00h ;CLEAR REGISTERS ; ; ; ; ; ; 1/30/2007 mov CLR CLR R7,#00h STATFLG RXFLG ; SETB SETB RXLED TR0 ;TURN ON LED ;TMR0 ENABLED JNB CLR SETB TF0,NXT TF0 TXLED ;WAIT TIL TMR OVERFLOW THEN JUMP ;CLEAR OVERFLOW FLAG ;TURN ON LED JNB CLR SETB TF0,NXT1 TF0 ACKLED ;WAIT TIL TMR OVERFLOW THEN JUMP ;CLEAR OVERFLOW FLAG ;TURN ON LED JNB CLR SETB TF0,NXT2 TF0 SLPLED ;WAIT TIL TMR OVERFLOW THEN JUMP ;CLEAR OVERFLOW FLAG ;TURN ON LED ;Flash LED's NXT: NXT1: NXT2: NXT3: JNB TF0,NXT3 ;WAIT TIL TMR OVERFLOW THEN JUMP CLR TF0 ;CLEAR OVERFLOW FLAG CLR RXLED CLR TXLED CLR ACKLED CLR TR0 ;TMR0 DISABLED ;------------------------------------------------------------mov CKCON,#000h ;SYSCLK/12 ;******************************************************** ;******************* MAIN LOOP *********************** ;******************************************************** JNB RNGTST,CFG2 ;Configure Device CFG1: A1: mov mov mov mov mov mov movc mov inc inc mov movc mov inc MOV ACALL XBR1,#0C0h ;disable port pullups CNT,#09h ;load byte counter DPTR,#TXSETUP_PMAX ;load table pointer TBLOFF,#0 ;set offset value A,TBLOFF ;load offset value R1,#HIGHBYTE ;load buffer pointer A,@A+DPTR ;load table byte @R1,A ;...into buffer TBLOFF ;incr offset R1 ;incr buffer A,TBLOFF ;load offset value A,@A+DPTR ;load table byte @R1,A ;...into buffer TBLOFF SPI0CN,#009h ;SET nSEL LOW (CHIP SELECT) SPISEND MOV SPI0CN,#00Dh djnz CNT,A1 SJMP START ;SET nSEL HIGH (DESELECT CHIP) ;decrement byte counter CFG2: YA1: mov mov mov mov mov mov movc mov inc XBR1,#0C0h ;disable port pullups CNT,#09h ;load byte counter DPTR,#TXSETUP_0dBm ;load table pointer TBLOFF,#0 ;set offset value A,TBLOFF ;load offset value R1,#HIGHBYTE ;load buffer pointer A,@A+DPTR ;load table byte @R1,A ;...into buffer TBLOFF ;incr offset 1/30/2007 inc R1 mov A,TBLOFF movc A,@A+DPTR mov @R1,A inc TBLOFF MOV SPI0CN,#009h ACALL SPISEND MOV SPI0CN,#00Dh djnz CNT,YA1 ;incr buffer ;load offset value ;load table byte ;...into buffer ;SET nSEL LOW (CHIP SELECT) ;SET nSEL HIGH (DESELECT CHIP) ;decrement byte counter ;******* Start Timer3 and LOOP til next TX ****************** START: mov TMR3CN,#04h ;TMR3 en IL: NOP SJMP IL ;***** READ CHIP STATUS ***** STATGO: SETB TXLED CLR STATFLG MOV SPI0CN,#009h MOV SPI0DAT,#00H WAITSS: JNB SPIF, WAITSS CLR SPIF MOV R0,SPI0DAT MOV SPI0DAT,#00H WAITZZ: JNB SPIF, WAITZZ CLR SPIF MOV R1,SPI0DAT ;IF SET, CLEAR FLAG FIRST ;SET nSEL LOW (CHIP SELECT) ;WRITE DUMMY BYTE TO SPI ;WRITE HIGH BYTE TO BUFFER ;WRITE DUMMY BYTE TO SPI ;WRITE LOW BYTE TO BUFFER ; *** SPI SEND *********************************************** SPISEND: ;(Chip Select already LOW) MOV SPI0DAT,HIGHBYTE ;WRITE HIGH BYTE TO SPI WAIT4: JNB SPIF,WAIT4 ;WAIT FOR SPI TO FINISH FIRST XFER,LOOP IF STILL BUSY CLR SPIF ;CLEAR SPI INT FLAG TO PROCEED MOV SPI0DAT,LOWBYTE ;WRITE LOW BYTE TO SPI WAIT5: JNB SPIF,WAIT5 ;WAIT FOR SPI TO FINISH 2ND XFER,LOOP IF STILL BUSY CLR SPIF ;CLEAR SPI INT FLAG TO PROCEED RTRN: CLR ACKLED RET TXSETUP_PMAX: ;PMAX DB 80h DB 0A7h ;config reg DB 0A6h DB 40h ;Freq set DB 82h DB 19h ;Pwr mng DB 98h DB 10h ;TX set DB 0CEh DB 0E2h ;Synch Char DB 0CCh DB 06h ;PLL cmd DB 0C6h DB 91h ;Data Rate 2400 DB 0CAh 1/30/2007 DB 81h ;Dis RESET DB 0C4H DB 0D7H ;AFA TXSETUP_0dBm: ;0dBm DB 80h DB 0A7h ;config reg DB 0A6h DB 40h ;Freq set DB 82h DB 19h ;Pwr mng DB 98h DB 10h ;TX set DB 0CEh DB 0E2h ;Synch Char DB 0CCh DB 06h ;PLL cmd DB 0C6h DB 91H ;Data Rate 2400 DB 0CAh DB 81h ;Dis RESET DB 0C4H DB 0D7H ;AFA TXDATA: DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 0AAh 0AAh 0AAh 0AAh 2Dh 0D4h '' 'R' 'F' 'M' '' 'R' 'F' 'I' 'C' '' 'R' 'A' 'N' 'G' 'E' '' 'T' 'E' 'S' 'T' '' '4' '3' '3' '.' '9' '2' '' 'M' 'H' ;0 ;0 ;0 ;1 ;2 ;3 'FOR TRC101 AND RXC101' ;4 ;5 ;6 ;7 ;8 ;9 ;A ;B ;C ;D ;E ;F ;10 ;11 ;12 ;13 ;14 ;15 ;16 ;17 ;18 ;19 ;1A ;1B ;1C ;1D ;1E ;1F ;20 ;21 1/30/2007 DB DB DB DB DB 'z' 0DH 07H 98H 00H ;22 ;23 ;23 ;24 ;25 END 1/30/2007