AN723 P OR TING C ONSIDERATIONS FROM C8051F330-5 AND C8051F336-9 T O C8051F39 X /37 X 1. Introduction This application note highlights the differences among the C8051F330-5, C8051F336-9, and C8051F39x/37x MCUs. These devices are designed to be code-compatible and pin-compatible, and thus require very minor changes when porting firmware and hardware between MCUs in these three families. The ’F39x/37x is the newest among the three families and includes an enhanced feature set in addition to all of the peripherals of the ’F330-5 and ’F336-9. 2. Common Features Some digital and analog peripherals are common to the three families. If SFR paging is accounted for, firmware written for these peripherals will work on any of the three families. The list of common digital and analog peripherals is: ADC and ADC Temperature Sensor SMBus 0 Comparator SPI IDAC 0 Timers 0, 1, 2, 3 PCA UART Note that while these peripherals are common to all three families, they might not be available in each part number of a product family. Refer to the Ordering Information sections of the applicable data sheets to determine the specific part number that includes the peripherals necessary for the system. As an example, the C8051F330-GM is pin- and code-compatible with the C8051F393-A-GM. However, the C8051F393-A-GM does not include an ADC peripheral. If this peripheral is necessary for the system, the appropriate upgrade choice is the C8051F392-A-GM. 2.1. Pin-Compatibility Corresponding package options in each product family are 100% pin-compatible; therefore, no PCB redesign is necessary when switching between these product families. Additional porting considerations are discussed in Section 3. Table 1 accounts for pin-compatibility but not memory size and available peripherals. A specific ’F39x/ 37x part number is recommended for each ’F330-5 and ’F336-9 part number in Section 4. Table 1. Pin-Compatible MCUs Package C8051F330/1/2/3/4/5 C8051F336/7/8/9 C8051F39x/37x QFN-20 (all are pin compatible) C8051F330-GM C8051F331-GM C8051F332-GM C8051F333-GM C8051F334-GM C8051F335-GM C8051F336-GM C8051F337-GM C8051F392-GM C8051F393-GM C8051F396-GM C8051F397-GM C8051F398-GM C8051F399-GM QFN-24 (all are pin compatible) — C8051F338-GM C8051F339-GM C8051F390-GM C8051F391-GM C8051F394-GM C8051F395-GM Rev. 0.2 8/12 Copyright © 2012 by Silicon Laboratories C8051F370-GM C8051F371-GM C8051F374-GM C8051F375-GM AN723 AN723 3. Distinguishing Factors Table 2 lists the primary differences between the three MCU families. Some peripherals and capabilities are unique to certain product families. When moving a design from one MCU family to another, ensure that the new MCU family includes the necessary features. Also, note that the features listed in the table might not be available in all products in the product family. See the applicable data sheet to determine the part number that includes features necessary for the design. The addition of features to the ’F39x/37x family created minor differences between some common components of the three families. When porting code between these families, it will be necessary to make minor firmware changes if these components are used. These differences and the required changes are detailed in Sections 3.1 through 3.7. If these changes are accounted for, any firmware written for one of the three product families can run directly on an MCU from the other two product families. Table 2. Features Differences between MCU Families Feature C8051F330/1/2/3/4/5 C8051F336/7/8/9 C8051F39x/37x 25 25 50 24.5 MHz 24.5 MHz 49 MHz 8 kB 16 kB 16 kB 512 B 512 B 768 B — — ADC Channels 16 20 20 ADC Temp Sensor Precision Temp Sensor — — IDACs 1 1 2 Port Pins 17 21 21 All Port Pins 5 V Tolerant — Timers 4 4 6 SMBus/I2C 1 1 2 CRC — — QFN-20 QFN-24 — Core System Clock Maximum Internal Oscillator Calibration Frequency Program Memory Maximum XRAM SFR Paging Analog Digital Pinout and Packages 2 Rev. 0.2 AN723 3.1. Internal High-Frequency Oscillator The ’F330-5 and ’F336-9 devices include an internal high-frequency oscillator calibrated to 24.5 MHz. The ’F39x/ 37x devices include an internal high-frequency oscillator calibrated to 49 MHz. Upon reset, the system clock (SYSCLK) frequency is 3.0625 MHz on all three families. Internal high-frequency oscillator firmware written for the ’F330-5 or ’F336-9 will result in the same SYSCLK frequency on the ’F39x/37x. Internal high-frequency oscillator firmware written for the ’F39x/37x will result in the same SYSCLK frequency on a ’F330-5 or ’F336-9 as long as the 49 MHz frequency is not selected. Table 3. SYSCLK Frequency SYSCLK Frequency CLKSEL[1:0] OSCICN[1:0] C8051F330/1/2/3/4/5 C8051F336/7/8/9 C8051F39x/37x 11b XXb* — — 49 MHz 00b 11b 24.5 MHz 24.5 MHz 24.5 MHz 00b 10b 12.25 MHz 12.25 MHz 12.25 MHz 00b 01b 6.125 MHz 6.125 MHz 6.125 MHz 00b 00b 3.0625 MHz 3.0625 MHz 3.0625 MHz * Note: XX denotes don’t care 3.2. Special Function Register Paging The ’F39x/37x devices implement a paged special function register (SFR) scheme which greatly expands the number of available SFR addresses. This SFR address expansion provides support for more peripherals such as: Second current DAC (IDA1) Second SMBus peripheral (SMBus1) CRC unit (CRC0) Precision temperature sensor (TS0) Timer 4 and Timer 5 To correctly read or write to SFRs in a ’F39x/37x device, the SFRPAGE register must be set to the correct SFR page. The SFRPAGE register itself is accessible from all SFR pages. For example, to access the IDA1 control register IDA1CN, SFRPAGE must be set to 0x0F. SFRPAGE = CONFIG_PAGE; IDA1CN |= 0x80; // Switch SFR page to 0x0F // Enable IDA1 CONFIG_PAGE is defined as 0x0F in the C8051F390_defs.h header file. It is recommended to use the defined constants for SFRPAGE to enhance code readability and to reduce the porting effort for future platforms. When porting code from a ’F330-5 or ’F336-9 device to a ’F39x/37x device, modify the firmware to set the SFRPAGE before any SFR accesses. When porting code from a ’F39x/37x device to a ’F33x device, remove all writes to SFRPAGE. Rev. 0.2 3 AN723 3.3. Special Function Registers Page Address The SFR memory maps of the ’F330-5, ’F336-9, and ’F39x/37x are very similar. However, there are a few differences related to functionality or features found on only one of the two device families. Fortunately, SFRs that exist on one family but not on the other can be safely written and read on the other device family without causing a problem. Likewise, certain registers have additional bits defined that are not present on both devices. In these cases, the default bit settings are safe to write, and the read values of those bits are defined in the data sheet. Figure 1 shows the combined SFR map of the three device families. The locations of SFRs that differ between the three families and those with only bitwise differences are highlighted. F8 F0 E8 E0 SPI0CN B ADC0CN 0 F D8 D0 C8 C0 B8 0(8) Bit-Addressable ACC PCA0CN 0 F 0 F 0 F 0 F PSW TMR2CN TMR5CN SMB0CN SMB1CN IP B0 A8 0 F A0 98 90 88 80 0 F 1(9) XBR0 XBR1 PCA0MD PCA0CPM0 TS0DATL REF0CN TS0CN TMR2RLL REG0CN TMR5RLL SMB0CF SMB0DAT SMB1CF SMB1DAT IDA0CN AMX0N IDA1CN OSCXCN OSCICN CLKSEL P2 SCON0 SPI0CFG SBUF0 TMR3CN TMR4CN TMOD SP TCON P0 3(B) 4(C) OSCLCN PCA0CPM1 TS0DATH SFRSTACK TMR2RLH TMR5RLH 5(D) 6(E) P0MAT P0MASK EIP1 P1MASK ADC0GTL ADC0GTH ADC0LTL ADC0LTH SMBTC AMX0P ADC0CF ADC0L ADC0H EIP2 OSCICL PFE0CN FLSCL FLKEY DERIVID REVISION EMI0CN EIE2 SN0 SN1 SN2 SN3 SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE CRC0FLIP CPT0CN CRC0IN CPT0MD CRC0DAT CPT0MX TMR3RLL TMR3RLH TMR3L TMR3H IDA0L IDA0H TMR4RLL TMR4RLH TMR4L TMR4H IDA1L IDA1H TL0 TL1 TH0 TH1 CKCON PSCTL DPL DPH IPH EIP1H EIP2H PCON denotes SFRs on ’F336-9 and ’F39x/37x only denotes SFRs on ’F39x/37x only denotes bitwise differences across all three families Figure 1. ’F330-5, ’F336-9, and ’F39x/37x SFR Memory Map 4 7(F) VDM0CN PCA0PWM P1MAT RSTSRC SMB0ADM IT01CF EIE1 SMB1ADM PCA0CPM2 CRC0AUTO CRC0CNT CRC0CN SMB0ADR P2SKIP P0SKIP P1SKIP SMB1ADR TMR2L TMR2H PCA0CLR SFRPGCN TMR5L TMR5H PCA0L PCA0H PCA0CPL0 PCA0CPH0 P0MDIN P1MDIN P2MDIN CKCON1 PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 IE P1 2(A) Rev. 0.2 AN723 3.4. Precision Temperature Sensor An ADC temperature sensor is included in the ’F330-5, ’F336-9, and ’F39x/37x families. The ’F39x/37x family also includes a self-contained precision temperature sensor that is accurate to ±2 °C. The ’F39x/37x precision temperature sensor directly reports the die temperature in degrees Celsius as a 16-bit, two’s complement number. The ±2 °C accuracy is achieved with no calibration. Though the ’F39x/37x retains an ADC temperature sensor for ’F330-5 and ’F336-9 compatibility, ’F39x/37x designs are encouraged to utilize the ±2 °C accurate precision temperature sensor. 3.5. Lock Byte On every Silicon Labs MCU, the lock byte is located in the last byte of user-accessible flash. The ’F330-5 family has 8K, 4K, and 2K of flash. The ’F336-9 family has 16K of flash. The ’F39x/37x family has 16K, 8K, and 4K of flash. When porting firmware from one family to another, the location of the lock byte must be moved if it is used. Table 4. Location of Lock Byte Lock Byte Address Flash Size C8051F330/1/2/3/4/5 C8051F336/7/8/9 C8051F39x/37x 16K Flash — 0x3DFF 0x3FFF 8K Flash 0x1DFF — 0x1FFF 4K Flash 0x0FFF — 0x0FFF 2K Flash 0x07FF — — Rev. 0.2 5 AN723 3.6. Differences in Electrical Characteristics Table 5 lists select electrical characteristics that have a wider specification on the ’F39x/37x compared to the ’F330-5 and ’F336-9. Electrical characteristics in this list were selected based on significance, and the list is not comprehensive. Note: Refer to the respective data sheets for the comprehensive electrical characteristics. All port pins on the ’F330-5 and ’F336-9 devices are 5 V tolerant. On ’F39x/37x devices, all port pins are not 5 V tolerant, and power should not be applied to any port pin until the voltage on the VDD pin is within the data sheet specification. Table 5. Selected Differences in Electrical Characteristics Parameter Conditions ’F330-5 ’F336-9 ’F39x/37x Units Voltage on any Port I/O Pin or RST with respect to GND, Absolute Maximum 5.8 5.8 VDD* + 0.3 V Specified Operating Temperature Range, Maximum 85 85 105 (‘F39x) 85 (‘F37x) °C Digital Supply Current—CPU Active (Normal Mode, Fetching Instructions from flash), Typical VDD = 3.0 V, F = 80 kHz 31 35 250 µA Digital Supply Current—CPU Inactive (Idle Mode, Not Fetching Instructions from flash), Typical VDD = 3.0 V, F = 80 kHz 16 13 100 µA Port I/O Input High Voltage, Minimum 2 2 VDD – 0.4 (1.8 ≤ VDD < 2.7) VDD – 0.5 (2.7 ≤ VDD ≤ 3.6) V Port I/O Input Low Voltage, Maximum 0.8 0.8 0.5 (1.8 ≤ VDD < 2.7) 0.6 (2.7 ≤ VDD ≤ 3.6) V Flash Erase Cycle Time, Maximum 20 20 27 ms ADC INL, Maximum ±1 ±1 ±2 LSB ±0.5 ±0.5 <±1 LSB IDAC INL, Maximum — ±2 ±3 LSB IDAC DNL, Maximum ±1 ±1 ±1 (0 to +105 °C) ±1.3 (–40 to 0°C) LSB IDAC INL, Typical * Note: Maximum VDD is 3.6 V on ’F39x/37x Electrical characteristics obtained from: C8051F330-5 data sheet v1.7 C8051F336-9 data sheet v1.0 C8051F39x/37x data sheet v0.71 3.7. Other Peripherals All other peripherals and features not discussed in the previous sections are functionally the same between the two device families. If SFR paging is accounted for, firmware written for these peripherals will operate the same way on any of the three device families. 6 Rev. 0.2 AN723 4. Recommended Part Numbers The ’F39x/37x devices was designed to be pin- and code-compatible with the ’F330-5 and ’F336-9 devices. Table 6 identifies a specific ’F39x/37x part number for each ’F330-5 and ’F336-9 part number. Recommended ’F39x/37x part numbers were selected based on pin-compatibility, flash size, and available peripherals. Table 6. ‘F330-5 and ‘F336-9 Replacement Part Numbers C8051F330/1/2/3/4/5 C8051F336/7/8/9 C8051F39x/37x C8051F330-GM — C8051F396-A-GM C8051F331-GM — C8051F397-A-GM C8051F332-GM — C8051F398-A-GM C8051F333-GM — C8051F399-A-GM C8051F334-GM — C8051F398-A-GM* C8051F335-GM — C8051F399-A-GM* — C8051F336-GM C8051F392-A-GM — C8051F337-GM C8051F393-A-GM — C8051F338-GM C8051F390-A-GM C8051F370-A-GM — C8051F339-GM C8051F391-A-GM C8051F371-A-GM * Note: 2 kB flash is unavailable on ’F39x/37x. Smallest flash size on ’F39x/37x is 4 kB. Rev. 0.2 7 AN723 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: www.silabs.com/support and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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