RFM products are now Murata products. SC3046B-5 • • • • • Quartz SAW Frequency Stability Fundamental Fixed Frequency Very Low Jitter and Power Consumption Rugged, Miniature, Surface-Mount Case Low-Voltage Power Supply (3.3 VDC) 933.12 MHz Differential Sine-Wave Clock This digital clock is designed for use in high-speed communications timing systems. Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving 50 Ω loads. Absolute Maximum Ratings Rating Value Units Power Supply Voltage (VCC at Terminal 1) 0 to +4.0 VDC Input Voltage (ENABLE at Terminal 8) 0 to +4.0 VDC -40 to +85 °C Case Temperature (Powered or Storage) Electrical Characteristics Characteristic Output Frequency Sym Notes Minimum fO 1, 2 932.725 Absolute Frequency SMC-8B Case Typical Variation over Temperture Q and Q Output Power into 50Ω (VSWR ≤ 1.2) VO 1, 3 Operating Load VSWR Symmetry 3, 4, 5 Harmonic Spurious Start Up Time Output (Disabled) 49 1, 10 MHz 70 ppm 6.0 dBm 2:1 VP-P 51 % -30 dBc -60 dBc 30 µs 30 psP-P 3, 4, 6, 7 200 mVP-P from 1 MHz to ½ fO on 3, 4, 7, 8 35 psP-P 3, 9 75 mVP-P Amplitude into 50 Ω 3 15 Units 933.300 No Noise on VCC 50 Output DC Resistance (between Q & Q) ENABLE (Terminal 14) Input HIGH Voltage VIH VCC-0.1 Input LOW Voltage VIL 0.0 Input HIGH Current IIH Input LOW Current IIL DC Power Supply 3.0 3, 4, 6 Nonharmonic Spurious Q and Q Period Jitter 0.5 Maximum Propagation Delay tPD VCC Operating Current ICC Operating Ambient Temperature 1, 3 1, 3 TA Lid Symbolization (YY = Year, WW = Week) VCC 3 3, 9 Operating Voltage KΩ +3.13 +3.30 25 10 VCC+0.1 V 0.20 V 5 mA -1 mA 1 ms +3.47 VDC 45 mA +60 °C RFM SC3046B-5 933.12 MHz YYWW CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. NOTES: 1. 2. 3. 4. 5. 6. Unless otherwise noted, all specifications are at 25 ± 3°C and include any combination of load VSWR and VCC. In addition, Q and Q are terminated into 50 Ω loads to ground. (See: Typical Test Circuit.) One or more of the following United States patents apply: 4,616,197; 4,670,681; 4,760,352. The design, manufacturing process, and specifications of this device are subject to change without notice. Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and nominal power supply voltage. Symmetry is defined as the pulse width (in percent of total period) measured at the 50% points of Q or Q. (See: Timing Definitions.) Jitter and other spurious outputs induced by externally generated electrical noise on VCC or mechanical vibration are not included. Dedicated external voltage ©2010-2015 by Murata Electronics N.A., Inc. SC3046B-5 (R) 2/12/15 7. 8. 9. 10. Page 1 of 2 regulation and careful PCB layout are recommended for optimum performance. Applies to period jitter of Q and Q. Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half of fO at the VCC power supply terminal. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is defined as the time from the 50% point on the rising edge of ENABLE to the 90% point on the rising edge of the output amplitude or as the fall time from the 50% point to the 10% point. (SEE: Timing Definitions.) The start up time is definded as the time from when power is applied to terminals 1 and 8 (90% of 3.3V) until power out from Q and Qbar reaches 90% of Qout level. www.murata.com Electrical Connections Footprint Actual size footprint: Terminal Number Connection 1 VCC 2 Ground 3 NC or Ground 4 1 8 2 7 Q Output 3 6 5 Q Output 4 5 6 Ground Typical Printed Circuit Board Land Pattern A typical land pattern for a circuit board is shown below. Grounding of the metallic center pad is critical to the performance of this high frequency Clock. 7 8 ENABLE LID Ground TOP VIEW Typically 0.01" to 0.05" or 0.25 mm to 1.25 mm (8 Places) Case Design All pads consist of 30 microinches (min) electroless gold on 50 microinches (min) electroless nickel over base metal. The metallic center pad was designed for mechanical support. Grounding of this pad is critical to the performance of this high frequency Clock. Lid symbolization, including terminal 1 locator dot, are in contrasting ink. Symbolization varies by model number. For purposes of illustration, only terminal 1 dot is shown. (The optimum value of this dimension is dependent on the PCB assembly process employed.) . Typical Test Circuit 0.1 μF V cc B D C E N (X8) A Tektronix CSA 803 Digitizing Oscilloscope Sine-Wave Signal Generator 4.7 μH V cc F (X8) Clock Under Test M G 50 Ω Q Ch 1 Trigger * Ch 2 ENABLE (X3) 50 Ω L H (X2) K * 50 Ω Q *Power Splitter, Mini-Circuits ZFSC2-4 J Timing Definitions Electrical Characteristics Dimensions Propagation Delay: Millimeters Min Max Inches Min Max A 13.46 13.97 0.530 0.550 B 9.14 9.66 0.360 0.380 C 2.05 Nominal 0.081 Nominal D 3.56 Nominal 0.141 Nominal E 2.24 Nominal 0.088 Nominal F 1.27 Nominal 0.050 Nominal G 2.54 Nominal 0.100 Nominal H 3.05 Nominal 0.120 Nominal J 1.93 Nominal 0.076 Nominal K 5.54 Nominal 0.218 Nominal L 4.32 Nominal 0.170 Nominal M 4.83 Nominal 0.190 Nominal N 0.50 Nominal 0.020 Nominal ENABLE 50% 50% 90% Q or Q Output Amplitude Envelope 10% t PD t PD Symmetry: Q or Q Output 50% 50% Symmetry as % of Period 50% Symmetry as % of Period Period ©2010-2015 by Murata Electronics N.A., Inc. SC3046B-5 (R) 2/12/15 Page 2 of 2 www.murata.com