MT9044
T1/E1/OC3 System Synchronizer
Data Sheet
Features
•
November 2005
Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and
Stratum 4 timing for DS1 interfaces
•
Supports ITU-T G.813 Option 1 clocks for 2048
kbit/s interfaces
•
Supports ITU-T G.812 Type IV clocks for
1,544 kbit/s interfaces and 2,048 kbit/s interfaces
Ordering Information
MT9044AP
MT9044AL
MT9044APR
MT9044APR1
MT9044AP1
MT9044AL1
44
44
44
44
44
44
Pin
Pin
Pin
Pin
Pin
Pin
PLCC
MQFP
PLCC
PLCC*
PLCC*
MQFP*
Tubes
Trays
Tape & Reel
Tape & Reel
Tubes
Trays
* Pb Free Matte Tin
-40°C to +85°C
•
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
•
•
Selectable 1.544 MHz, 2.048 MHz or 8 kHz input
reference signals
Accepts reference inputs from two independent
sources
•
JTAG Boundary Scan
•
Provides C1.5, C2, C3, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
•
Provides 5 different 8 KHz framing pulses
•
Holdover frequency accuracy of 0.05 PPM
•
Holdover indication
•
Attenuates wander from 1.9 Hz
•
Provides Time Interval Error (TIE) correction
OSCi
OSCo
IEEE
1149.1a
PRI
SEC
Reference
Select
MUX
•
Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
•
ST-BUS clock and frame pulse sources
TCLR
VDD
Master Clock
TCK
TDI
TMS
TRST
TDO
Applications
TIE
Corrector
Circuit
TIE
Corrector
Enable
C19o
C1.5o
C3o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Virtual
Reference
DPLL
Selected
Reference
Reference
Select
VSS
State
Select
Output
Interface
Circuit
Input
Impairment
Monitor
State
Select
Feedback
RSEL
LOS1
LOS2
Automatic/Manual
Control State Machine
Guard Time
Circuit
Frequency
Select
MUX
ACKi
APLL
ACKo
MS1
MS2
RST HOLDOVER
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003 - 2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT9044
Data Sheet
Change Summary
Changes from November 2004 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this
issue.
Page
6
Item
Change
The sentence "While the RST pin is low, all
frame and clock outputs are at logic high." is
changed to "While the RST pin is low, all
frame outputs except RSP and TSP and all
clock outputs except C6o, C16o and C19o
are at logic high. The RSP, TSP, C6o and
C16o are at logic low during reset. The C19o
is free-running during reset."
Pin Description - Pin 28 RST
Changes from November 2003 Issue to November 2004 Issue. Page, section, figure and table numbers refer to this
issue.
Page
Item
Change
21
Guard Time Calculation
Example time increases from to 0.9 to1.45
seconds
27
Table "DC Electrical Characteristics"
line item 7
Changed Minimum Schmitt high level input
voltage VSIH from 2.3 volts to 3.4 volts
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
Description
The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links.
The MT9044 generates ST-BUS clock and framing signals that are phase locked to either a 2.048 MHz,
1.544 MHz, or 8 kHz input reference.
PRI
SEC
TRST
TCLR
TCLK
VSS
TMS
RST
TDI
FS1
FS2
6 5 4 3 2 1 44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
7
8
9
10
11
12
13
14
15
16
17
MT9044AP
39
38
37
36
35
34
33
32
31
30
29
VDD
OSCo
OSCi
VSS
F16o
RSP
F0o
TSP
F8o
C1.5o
AVDD
IC
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
1
2
3
4
5
6
7
8
9
10
11
MT9044AL
12 13 14 15 16 17 18 19 20 21 22
ACKi
VSS
ACKo
C8o
C16o
C6o
VDD
C3o
C2o
C4o
C19o
ACKi
VSS
ACKo
C8o
C16o
C6o
VDD
18 19 20 21 22 23 24 25 26 27 28
C3o
C2o
C4o
C19o
VDD
OSCo
OSCi
VSS
F16o
RSP
F0o
TSP
F8o
C1.5o
AVDD
PRI
SEC
TRST
TCLR
TCK
VSS
TMS
RST
TDI
FS1
FS2
The MT9044 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and
Stratum 4; and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander
tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope,
holdover frequency and MTIE requirements for these specifications.
Figure 2 - Pin Connections
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Zarlink Semiconductor Inc.
33
32
31
30
29
28
27
26
25
24
23
IC
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
MT9044
Data Sheet
Pin Description
Pin # Pin #
PLCC MQFP
1,10, 39,4,17
23,31
,25
Name
Description
VSS
Ground. 0 Volts.
Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is
internally pulled up to VDD.
2
40
TCK
3
41
TCLR
TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a re-alignment of input phase with output
phase as shown in Figure 19. The TCLR pin should be held low for a minimum of
300 ns. This pin is internally pulled down to VSS.
4
42
TRST
Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.
5
43
SEC
Secondary Reference (TTL Input). This is one of two (PRI & SEC) input
reference sources (falling edge) used for synchronization. One of three possible
frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be used. The selection of the
input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi control
inputs (Automatic or Manual). This pin is internally pulled up to VDD.
6
44
PRI
Primary Reference (TTL Input). See pin description for SEC. This pin is
internally pulled up to VDD.
7,28
1,22
VDD
Positive Supply Voltage. +5VDC nominal.
8
2
OSCo
Oscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz
crystal is connected from this pin to OSCi, see Figure 10. For clock oscillator
operation, this pin is left unconnected, see Figure 9.
9
3
OSCi
Oscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal
is connected from this pin to OSCo, see Figure 10. For clock oscillator operation,
this pin is connected to a clock source, see Figure 9.
11
5
F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61 ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 8.192 Mb/s. See Figure 20.
12
6
RSP
Receive Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing
pulse, which marks the end of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
13
7
F0o
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns
active low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 20.
14
8
TSP
Transmit Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high
framing pulse, which marks the beginning of an ST-BUS frame. This is typically
used for connection to the Siemens MUNICH-32 device. See Figure 21.
15
9
F8o
Frame Pulse (CMOS Output). This is an 8 kHz 122 ns active high framing pulse,
which marks the beginning of a frame. See Figure 20.
16
10
C1.5o
Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
17
11
AVDD
Analog Vdd. +5VDC nominal.
18
12
C3o
Clock 3.088 MHz (CMOS Output). This output is used in T1 applications.
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
Pin Description (continued)
Pin # Pin #
PLCC MQFP
Name
Description
19
13
C2o
Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at
2.048 Mb/s.
20
14
C4o
Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at
2.048 Mb/s and 4.096 Mb/s.
21
15
C19o
Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.
22
16
ACKi
Analog PLL Clock Input (CMOS Input). This input clock is a reference for an
internal analog PLL. This pin is internally pulled down to VSS.
24
18
ACKo
Analog PLL Clock Output (CMOS Output). This output clock is generated by
the internal analog PLL.
25
19
C8o
Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at
8.192 Mb/s.
26
20
C16o
Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation
with a 16.384 MHz clock.
27
21
C6o
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
29
23
30
24
GTi
Guard Time (Schmitt Input). This input is used by the MT9044 state machine in
both Manual and Automatic modes. The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary
Holdover Mode and Secondary Normal Mode. The logic level at this input is gated
in by the rising edge of F8o. See Tables 4 and 5.
32
26
GTo
Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o,
buffered and output on GTo. This pin is typically used to drive the GTi input through
an RC circuit.
33
27
LOS2
Secondary Reference Loss (TTL Input). This input is normally connected to the
loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the
SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs
control the MT9044 state machine when operating in Automatic Control. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled
down to VSS.
34
28
LOS1
Primary Reference Loss (TTL Input). Typically, external equipment applies a
logic high to this input when the PRI reference signal is lost or invalid. The logic
level at this input is gated in by the rising edge of F8o. See LOS2 description. This
pin is internally pulled down to VSS.
35
29
TDO
Test Serial Data Out (TTL Output). JTAG serial data is output on this pin on the
falling edge of TCK. This pin is held in high impedance state when JTAG scan is
not enabled.
36
30
MS2
Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1,
determines the device’s mode (Automatic or Manual) and state (Normal, Holdover
or Freerun) of operation. The logic level at this input is gated in by the rising edge
of F8o. See Table 3.
HOLDOVER Holdover (CMOS Output). This output goes to a logic high whenever the digital
PLL goes into holdover mode.
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
Pin Description (continued)
Pin # Pin #
PLCC MQFP
Name
Description
37
31
MS1
Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by
the rising edge of F8o. See pin description for MS2. This pin is internally pulled
down to VSS.
38
32
RSEL
Reference Source Select (TTL Input). In Manual Control, a logic low selects the
PRI (primary) reference source as the input reference signal and a logic high
selects the SEC (secondary) input. In Automatic Control, this pin must be at logic
low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
This pin is internally pulled down to VSS.
39
33
IC
40
34
FS2
Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects
which of three possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be
input to the PRI and SEC inputs. See Table 1.
41
35
FS1
Frequency Select 1 (TTL Input). See pin description for FS2.
42
36
TDI
Test Serial Data In (TTL Input). JTAG serial test instructions and data are shifted
in on this pin. This pin is internally pulled up to VDD.
43
37
RST
Reset (Schmitt Input). A logic low at this input resets the MT9044. To ensure
proper operation, the device must be reset after changes to the method of control,
reference signal frequency changes and power-up. The RST pin should be held
low for a minimum of 300 ns. While the RST pin is low, all frame outputs except
RSP and TSP and all clock outputs except C6o, C16o and C19o are at logic high.
The RSP, TSP, C6o and C16o are at logic low during reset. The C19o is freerunning during reset. Following a reset, the input reference source and output
clocks and frame pulses are phase aligned as shown in Figure 19.
44
38
TMS
Test Mode Select (TTL Input). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to VDD.
Internal Connection. Tie low for normal operation.
Functional Description
The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links.
Figure 1 shows the functional block diagram which is described in the following sections.
Reference Select MUX Circuit
The MT9044 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables
1, 4 and 5.
Frequency Select MUX Circuit
The MT9044 operates with one of three possible input reference frequencies (8 kHz, 1.544 MHz or 2.048 MHz).
The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference
inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be
performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and
must not be used. See Table 1.
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
FS2
FS1
Input Frequency
0
0
Reserved
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
Table 1 - Input Frequency Selection
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL will
lead to unacceptable phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.
TCLR
Resets Delay
Control
Circuit
Control Signal
Delay Value
PRI or SEC
from
Reference
Select Mux
Programmable
Delay Circuit
Virtual
Reference
to DPLL
Compare
Circuit
TIE Corrector
Enable
from
State Machine
Feedback
Signal from
Frequency
Select MUX
Figure 3 - TIE Corrector Circuit
During a switch, from one reference to the other, the State Machine first changes the mode of the device from
Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an
accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the
current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the
Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as
the previous reference signal would have been if the reference switch had not taken place. The State Machine then
returns the device to Normal Mode.
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,
no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change
at the input of the DPLL, or at the output of the DPLL.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A
minimum reset pulse width is 300 ns. This results in a phase alignment between the input reference signal and the
output signal as shown in Figure 20. The speed of the phase alignment correction is limited to 5 ns per 125 us, and
convergence is in the direction of least phase travel.
The state diagrams of Figure 7 and 8 indicate the state changes that activate the TIE Corrector Circuit.
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the MT9044 consists of a Phase Detector, Limiter, Loop Filter, Digitally
Controlled Oscillator, and a Control Circuit.
Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the
proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz or 2.048 MHz).
Virtual Reference from
TIE Corrector
Phase
Detector
Feedback Signal from
Frequency Select MUX
Limiter
Loop Filter
State Select from
Input Impairment
Monitor
Digitally
Controlled
Oscillator
DPLL Reference to
Output Interface Circuit
Control
Circuit
State Select from
State Machine
Figure 4 - DPLL Block Diagram
Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5 ns per 125 us. This is well within the maximum
phase slope of 7.6 ns per 125 us or 81 ns per 1.326 ms specified by AT&T TR62411, and Bellcore GR-1244CORE.
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three
reference frequency selections (8 kHz, 1.544 MHz or 2.048 MHz). This filter ensures that the jitter transfer
requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9044.
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30 ms to 60 ms) frequency the
DCO was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
a DS2 Divider Circuit and an analog PLL to generate the required output signals.
Four tapped delay lines are used to generate a 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384 MHz signal to generate two clock outputs. C1.5o and C3o are generated by
dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
T1 Divider
C1.5o
C3o
12 MHz
Tapped
Delay
Line
E1 Divider
Tapped
Delay
Line
From
DPLL
Tapped
Delay
Line
Tapped
Delay
Line
16 MHz
12 MHz
DS2 Divider
19 MHz
C2o
C4o
C8o
C16o
F0o
F8o
F16o
C6o
C19o
Analog PLL
ACKo
ACKi
Figure 5 - Output Interface Circuit Block
The frame pulse outputs (F0o, F8o, F16o, TSP, RSP) are generated directly from the C16 clock.
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o,
C2o, C4o, C8o, C16o, F0o, F16o and C6o are locked to one another for all operating states, and are also locked to
the selected input reference in Normal Mode. See Figures 20 and 21.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g. 30 pF) loads.
Analog Phase Lock Loop (APLL)
The analog PLL is intended to be used to achieve a 50% duty cycle output clock. Connecting C19o to ACKi will
generate a phase locked 19.44 MHz ACKo output with a nominal 50% duty cycle and a maximum peak_to_peak
unfiltered jitter of 0.174 U.I.. The analog PLL has an intrinsic jitter of less than 0.01 U.I. In order to achieve this low
jitter level a separate pin is provided to power (AVdd) the analog PLL.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)
when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical
Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the
incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output
signal locked to the input signal. The holdover output signal is based on the incoming signal 30 ms minimum to
60 ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the
Holdover Mode is very accurate (e.g., ±0.05 ppm). The the Auto-Holdover circuit does not use TIE correction.
Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved (is
the same as just prior to the switch to Auto-Holdover).
Automatic/Manual Control State Machine
The Automatic/Manual Control State Machine allows the MT9044 to be controlled automatically (i.e., LOS1, LOS2
and GTi signals) or controlled manually (i.e., MS1, MS2, GTi and RSEL signals). With manual control a single mode
of operation (i.e., Normal, Holdover and Freerun) is selected. Under automatic control the state of the LOS1, LOS2
and GTi signals determines the sequence of modes that the MT9044 will follow.
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit, the DPLL
and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL, MS1,
MS2 and GTi of the Guard Time Circuit (See Figure 6).
All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of
Operation section for full details on Automatic Control and Manual Control.
To
Reference
Select MUX
RSEL
LOS1
LOS2
To TIE
Corrector
Enable
To DPLL
State
Select
Automatic/Manual Control
State Machine
MS1
To and From
Guard Time
Circuit
MS2
Figure 6 - Automatic/Manual Control State Machine Block Diagram
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
Guard Time Circuit
The GTi pin is used by the Automatic/Manual Control State Machine in the MT9044 under either Manual or
Automatic control. The logic level at the GTi pin performs two functions, it enables and disables the TIE Corrector
Circuit (Manual and Automatic) and it selects which mode change takes place (Automatic only). See the
Applications - Guard Time section.
For both Manual and Automatic control, when switching from Primary Holdover to Primary Normal, the TIE
Corrector Circuit is enabled when GTi=1, and disabled when GTi=0.
Under Automatic control and in Primary Normal Mode, two state changes are possible (not counting AutoHoldover). These are state changes to Primary Holdover or to Secondary Normal. The logic level at the GTi pin
determines which state change occurs. When GTi=0, the state change is to Primary Holdover. When GTi=1, the
state change is to Secondary Normal.
Master Clock
The MT9044 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Control and Modes of Operation
The MT9044 can operate either in Manual or Automatic Control. Each control method has three possible modes of
operation, Normal, Holdover and Freerun.
As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control.
Control
RSEL
Input Reference
MANUAL
0
PRI
1
SEC
0
State Machine Control
1
Reserved
AUTO
Table 2 - Input Reference Selection
MS2
MS1
Control
Mode
0
0
MANUAL
NORMAL
0
1
MANUAL
HOLDOVER
1
0
MANUAL
FREERUN
1
1
AUTO
State Machine Control
Table 3 - Operating Modes and States
11
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Manual Control
Manual Control should be used when either very simple MT9044 control is required, or when complex control is
required which is not accommodated by Automatic Control. For example, very simple control could include
operation in a system which only requires Normal Mode with reference switching using only a single input stimulus
(RSEL). Very simple control would require no external circuitry. Complex control could include a system which
requires state changes between Normal, Holdover and Freerun Modes based on numerous input stimuli. Complex
control would require external circuitry, typically a microcontroller.
Under Manual Control, one of the three modes is selected by mode/control select pins MS2 and MS1. The active
reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 7 for
details of the state change sequences.
Automatic Control
Automatic Control should be used when simple MT9044 control is required, which is more complex than the very
simple control provide by Manual Control with no external circuitry, but not as complex as Manual Control with a
microcontroller. For example, simple control could include operation in a system which can be accommodated by
the Automatic Control State Diagram shown in Figure 8.
Automatic Control is also selected by mode/control pins MS2 and MS1. However, the mode and active reference
source is selected automatically by the internal Automatic State Machine (See Figure 6). The mode and reference
changes are based on the logic levels on the LOS1, LOS2 and GTi control pins. Refer to Table 5 and Figure 8 for
details of the state change sequences.
Normal Mode
Normal Mode is typically used when a slave clock source, synchronized to the network is required.
In Normal Mode, the MT9044 provides timing (C1.5o, C2o, C3o, C4o, C8o, C16o, and C19) and frame
synchronization (F0o, F8o, F16o, RSP, TSP) signals, which are synchronized to one of two reference inputs (PRI or
SEC). The input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz or 2.048 MHz.
From a reset condition, the MT9044 will take up to 25 seconds for the output signal to be phase locked to the
selected reference.
The selection of input references is control dependent as shown in State Tables 4 and 5. The reference frequencies
are selected by the frequency control pins FS2 and FS1 as shown in Table 1.
12
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Holdover Mode
Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily
disrupted.
In Holdover Mode, the MT9044 provides timing and synchronization signals, which are not locked to an external
reference signal, but are based on storage techniques. The storage value is determined while the device is in
Normal Mode and locked to an external reference signal.
When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT9044
output frequency is stored alternately in two memory locations every 30 ms. When the device is switched into
Holdover Mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the
device.
The frequency accuracy of Holdover Mode is ±0.05ppm, which translates to a worst case 35 frame (125 us) slips in
24 hours. This meets the Bellcore GR-1244-CORE Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24
hours).
Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on
the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi)
accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a
±32 ppm master clock may have a temperature coefficient of ±0.1 ppm per degree C. So a 10 degree change in
temperature, while the MT9044 is in Holdover Mode may result in an additional offset (over the ±0.05 ppm) in
frequency accuracy of ±1 ppm, which is much greater than the ±0.05 ppm of the MT9044.
The other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch.
For instance, jitter of 7.5 UI at 700 Hz may reduce the Holdover Mode accuracy from 0.05 ppm to 0.10 ppm.
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
In Freerun Mode, the MT9044 provides timing and synchronization signals which are based on the master clock
frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32 ppm output clock
is required, the master clock must also be ±32 ppm. See Applications - Crystal and Clock Oscillator sections.
13
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Description
State
Input Controls
Freerun
Normal
(PRI)
Normal
(SEC)
Holdover
(PRI)
Holdover
(SEC)
MS2
MS1
RSEL
GTi
S0
S1
S2
S1H
S2H
0
0
0
0
S1
-
S1 MTIE
S1
S1 MTIE
0
0
0
1
S1
-
S1 MTIE
S1 MTIE
S1 MTIE
0
0
1
X
S2
S2 MTIE
-
S2 MTIE
S2 MTIE
0
1
0
X
/
S1H
/
-
/
0
1
1
X
/
S2H
S2H
/
-
1
0
X
X
-
S0
S0
S0
S0
Legend:
No Change
/
Not Valid
MTIE
State change occurs with TIE Corrector Circuit
Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Manual Control State Table
S0
Freerun
(10X)
S1
Normal
Primary
(000)
{A}
(GTi=0)
(GTi=1)
S1A
Auto-Holdover
Primary
(000)
S2A
Auto-Holdover
Secondary
(001)
S1H
Holdover
Primary
(010)
S2H
Holdover
Secondary
(011)
{A}
NOTES:
(XXX)
MS2 MS1 RSEL
Phase Re-Alignment
{A}
Invalid Reference Signal
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
Movement to Normal State from any
state requires a valid input signal
Figure 7 - Manual Control State Diagram
14
Zarlink Semiconductor Inc.
S2
Normal
Secondary
(001)
MT9044
Data Sheet
Description
State
Input Controls
Freerun
Normal
(PRI)
Normal
(SEC)
Holdover
(PRI)
Holdover
(SEC)
LOS2
LOS1
GTi
RST
S0
S1
S2
S1H
S2H
1
1
X
0 to 1
-
S0
S0
S0
S0
X
0
0
1
S1
-
S1 MTIE
S1
S1 MTIE
X
0
1
1
S1
-
S1 MTIE
S1 MTIE
S1 MTIE
0
1
0
1
S1
S1H
-
-
S2 MTIE
0
1
1
1
S2
S2 MTIE
-
S2 MTIE
S2 MTIE
1
1
X
1
-
S1H
S2H
-
-
Legend:
No Change
MTIE
State change occurs with TIE Corrector Circuit
Refer to Automatic Control State Diagram for state changes to and from Auto-Holdover State
Table 5 - Automatic Control (MS1=MS2=1, RSEL=0) State Table
(11X)
(11X) RST=1
Reset
S0
Freerun
(X0X)
(01X)
(X0X)
(X0X)
(01X)
(01X)
(X0X)
S1
Normal
Primary
{A}
(01X)
S1A
Auto-Holdover
Primary
S2A
Auto-Holdover
Secondary
S2
Normal
Secondary
{A}
(X0X)
(011)
(11X)
(010 or 11X)
(X0X)
(011)
(01X)
(X00)
S1H
Holdover
Primary
(X01)
S2H
Holdover
Secondary
(010 or 11X)
(11X)
NOTES:
(XXX)
LOS2 LOS1 GTi
Phase Re-Alignment
{A}
Invalid Reference Signal
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
Movement to Normal State from any
state requires a valid input signal
Figure 8 - Automatic Control State Diagram
15
Zarlink Semiconductor Inc.
MT9044
Data Sheet
MT9044 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring
the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the
applicable standards.
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the MT9044, two internal elements determine the jitter attenuation. This includes the internal 1.9 Hz low pass
loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5 ns/125 us.
Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the
maximum output phase slope will be limited (i.e., attenuated) to 5 ns/125 us.
The MT9044 has thirteen outputs with three possible input frequencies for a total of 39 possible jitter transfer
functions. However, the data sheet section on AC Electrical Characteristics - Jitter Transfer specifies transfer
values for only three cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to 2.048 MHz. Since all
outputs are derived from the same signal, these transfer values apply to all outputs.
It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns.
Consequently, a transfer value using different input and output frequencies must be calculated in common units
(e.g., seconds) as shown in the following example.
What is the T1 and E1 output jitter when the T1 input jitter is 20 UI (T1 UI Units) and the T1 to T1 jitter
attenuation is 18 dB?
OutputT1 = InputT1 ×10
OutputT1 = 20 ×10
18-
–------- 20
A
–----- 20
= 2.5UI ( T1 )
( 1UIT1 )
OutputE1 = OutputT1 × ---------------------( 1UIE1 )
( 644ns )
OutputE1 = OutputT1 × ------------------- = 3.3UI ( T1 )
( 488ns )
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on
the three jitter transfer functions provided.
16
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Note that the resulting jitter transfer functions for all combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz) and
outputs (8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz) for a given input signal (jitter
frequency and jitter amplitude) are the same.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the MT9044, the Freerun accuracy is equal to the
Master Clock (OSCi) accuracy.
Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the MT9044, the storage value is determined while
the device is in Normal Mode and locked to an external reference signal.
The absolute Master Clock (OSCi) accuracy of the MT9044 does not affect Holdover accuracy, but the change in
OSCi accuracy while in Holdover Mode does.
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull
into synchronization. The MT9044 capture range is equal to ±230 ppm minus the accuracy of the master clock
(OSCi). For example, a ±32 ppm master clock results in a capture range of ±198 ppm.
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the MT9044.
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal.
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
MTIE ( S ) = TIEmax ( t ) – TIEmin ( t )
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Zarlink Semiconductor Inc.
MT9044
Data Sheet
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
In the case of the MT9044, the output signal phase continuity is maintained to within ±5 ns at the instance (over one
frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of
mode change, may accumulate up to ±200 ns over many frames. The rate of change of the ±200 ns phase shift is
limited to a maximum phase slope of approximately 5 ns/125 us. This meets the maximum phase slope
requirement of Bellcore GR-1244-CORE (81 ns/1.326 ms).
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9044 loop filter and
limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for maximum phase lock time.
MT9044 and Network Specifications
The MT9044 fully meets all applicable PLL requirements (intrinsic jitter/wander, jitter/wander tolerance,
jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and
MTIE during reference rearrangement) for the following specifications.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Bellcore GR-1244-CORE June 1995 for Stratum 3, Stratum 4 Enhanced and Stratum 4
AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4
ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
TBR 4 November 1995
TBR 12 December 1993
TBR 13 January 1996
ITU-T I.431 March 1993
ITU-T G.813 August 1996 for Option1 clocks for 2048 kbit/s interfaces
ITU-T G.812 June 1998 for type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces
18
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Applications
This section contains MT9044 application specific details for clock and crystal operation, guard time usage, reset
operation, power supply decoupling, Manual Control operation and Automatic Control operation.
Master Clock
The MT9044 can use either a clock or crystal as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source
may be ±100 ppm. For applications requiring an accurate Freerun Mode, such as Bellcore GR-1244-CORE, the
tolerance of the master timing source must Be no greater than ±32 ppm.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT9044 will always equal ±230 ppm.
For example, if the master timing source is ±100 ppm, then the capture range will be ±130 ppm.
Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes
absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
See AC Electrical Characteristics.
MT9044
OSCi
+5 V
+5 V
20 MHz OUT
GND
0.1 uF
OSCo
No Connection
Figure 9 - Clock Oscillator Circuit
For applications requiring ±32 ppm clock accuracy, the following clock oscillator module may be used.
CTS CXO-65-HG-5-C-20.0 MHz
Frequency:
20 MHz
Tolerance:
25 ppm 0C to 70C
Rise & Fall Time:
8 ns (0.5 V 4.5 V 50 pF)
Duty Cycle:
45% to 55%
The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9044, and the OSCo
output should be left open as shown in Figure 9.
Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a
crystal, resistor and capacitors is shown in Figure 10.
19
Zarlink Semiconductor Inc.
MT9044
Data Sheet
MT9044
OSCi
20 MHz
1 MΩ
56 pF
39 pF
3-50 pF
OSCo
100 Ω
1 uH
1 uH inductor: may improve stability and is optional
Figure 10 - Crystal Oscillator Circuit
The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance.
Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance
contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances, and stray
capacitances have a major effect on the accuracy of the oscillator frequency.
The trimmer capacitor shown in Figure 10 may be used to compensate for capacitive effects. If accuracy is not a
concern, then the trimmer may be removed, the 39 pF capacitor may be increased to 56 pF, and a wider tolerance
crystal may be substituted.
The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler
oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal
specification is as follows.
Frequency:
Tolerance:
Oscillation Mode:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:
Approximate Drive Level:
e.g., CTS R1027-2BB-20.0 MHZ
(±20 ppm absolute, ±6 ppm 0C to
20 MHz
As required
Fundamental
Parallel
32 pF
35 Ω
1 mW
50C, 32 pF, 25 Ω)
Guard Time Adjustment
Excessive switching of the timing reference (from PRI to SEC) in the MT9044 can be minimized by first entering
Holdover Mode for a predetermined maximum time (i.e., guard time). If the degraded signal returns to normal
before the expiry of the guard time (e.g., 2.5 seconds), then the MT9044 is returned to its Normal Mode (with no
reference switch taking place). Otherwise, the reference input may be changed from Primary to Secondary.
20
Zarlink Semiconductor Inc.
MT9044
Data Sheet
MT9044
GTo
R
150 kΩ
+
C
10 uF
GTi
RP
1 kΩ
Figure 11 - Symmetrical Guard Time Circuit
A simple way to control the guard time (using Automatic Control) is with an RC circuit as shown in Figure 11.
Resistor RP is for protection only and limits the current flowing into the GTi pin during power down conditions. The
guard time can be calculated as follows.
V DD
guard time = RC × ln --------------------------------
V
–
V
DD
SIH
guard time ≈ RC × 0.6
example
guard time ≈ 150k × 10u × 0.6 = 1.45 s
•
V SIH is the logic high going threshold level for the GTi Schmitt Trigger input, see DC Electrical Characteristics
In cases where fast toggling might be expected of the LOS1 input, then an unsymmetrical Guard Time Circuit is
recommended. This ensures that reference switching doesn’t occur until the full guard time value has expired. An
unsymmetrical Guard Time Circuit is shown in Figure 12.
MT9044
GTo
+
RC
150 kΩ
RD
1 kΩ
C
10 uF
GTi
RP
1 kΩ
Figure 12 - Unsymmetrical Guard Time Circuit
21
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Figure 13 shows a typical timing example of an unsymmetrical Guard Time Circuit with the MT9044 in Automatic
Control.
SEC
SIGNAL
STATUS
GOOD
LOS2
PRI
SIGNAL
STATUS
GOOD
BAD
GOOD
GOOD
BAD
TD
TD
LOS1
GTo
VSIH
GTi
MT9044
STATE
PRI
NORMAL
PRI
HOLDOVER
PRI
NORMAL
PRI
HOLDOVER
SEC
NORMAL
PRI
NORMAL
NOTES:
1. TD represents the time delay from when the reference goes
bad to when the MT9044 is provided with a LOS indication.
Figure 13 - Automatic Control, Unsymmetrical Guard Time Circuit Timing Example
TIE Correction (using GTi)
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will
prevent unwanted accumulated phase change between the input and output. This is mainly applicable to Manual
Control, since Automatic Control together with the Guard Time Circuit inherently operate in this manner.
For instance, 10 Normal to Holdover to Normal mode change sequences occur, and in each case Holdover was
entered for 2s. Each mode change sequence could account for a phase change as large as 350 ns. Thus, the
accumulated phase change could be as large as 3.5 us, and, the overall MTIE could be as large as 3.5 us.
Phase hold = 0.05ppm × 2s = 100ns
Phase state = 50ns + 200ns = 250ns
Phase 10 = 10 × ( 250ns + 100ns ) = 3.5us
•
0.05 ppm is the accuracy of Holdover Mode
•
50 ns is the maximum phase continuity of the MT9044 from Normal Mode to Holdover Mode
•
200 ns is the maximum phase continuity of the MT9044 from Holdover Mode to Normal Mode (with or without TIE
Corrector Circuit)
When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case
holdover was entered for 2s, each mode change sequence could still account for a phase change as large as
350 ns. However, there would be no accumulated phase change, since the input to output phase is re-aligned after
every Holdover to Normal state change. The overall MTIE would only be 350 ns.
22
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Reset Circuit
A simple power up reset circuit with about a 50 us reset low time is shown in Figure 14. Resistor RP is for protection
only and limits current into the RST pin during power down conditions. The reset low time is not critical but should
be greater than 300 ns.
MT9044
+5 V
R
10 kΩ
RST
RP
1 kΩ
C
10 nF
Figure 14 - Power-Up Reset Circuit
Dual T1 Reference Sources with MT9044 in Automatic Control
For systems requiring simple state machine control, the application circuit shown in Figure 15 using Automatic
Control may be used.
In this circuit, the MT9044 is operating Automatically, using a Guard Time Circuit, and the LOS1 and LOS2 inputs to
determine all mode changes. Since the Guard Time Circuit is set to about 1s, all line interruptions (LOS1=1) less
than 1s will cause the MT9044 to go from Primary Normal Mode to Holdover Mode and not switch references. For
line interruptions greater than 1s, the MT9044 will switch Modes from Holdover to Secondary Normal, provided that
the secondary signal is valid (LOS2=0). After receiving a good primary signal (LOS1=0), the MT9044 will switch
back to Primary Normal Mode For complete Automatic Control state machine details, refer to Table 5 for the State
Table, and Figure 8 for the State Diagram.
23
Zarlink Semiconductor Inc.
MT9044
To Line 1
MT9074
TTIP
To
TX Line
XFMR
DSTo
DSTi
TRING
RTIP
To
RX Line
XFMR
Data Sheet
F0i
C4i
RRING
MT9044
E1.5o
LOS
PRI
SEC
+5V
To Line 2
TTIP
To
TX Line
XFMR
To
RX Line
XFMR
DSTo
DSTi
+5V
FS1
FS2
150 kΩ
GTo
GTi
1 kΩ
RST
OSCi
1 kΩ
10 kΩ
+5V
TRST
TRING
RTIP
LOS1
LOS2
MS1
MS2
RSEL
MT9074
F0o
C4o
1 kΩ
+
F0i
C4i
10 uF
RRING
10 nF
E1.5o
LOS
CLOCK
Out
20 MHz ±32 ppm
MT8985
STo0
STi0
STo1
STi1
F0i
C4i
Figure 15 - Dual T1 Reference Sources with MT9044 in 1.544 MHz Automatic Control
24
Zarlink Semiconductor Inc.
MT9044
To Line 1
To
TX Line
XFMR
MT9075
TTIP
DSTo
DSTi
TRING
RTIP
To
RX Line
XFMR
Data Sheet
F0i
C4i
RRING
MT9044
RxFP
PRI
LOS
To Line 2
DSTo
DSTi
TRING
RST
RTIP
To
RX Line
XFMR
LOS1 C1.5o
LOS2
FS1
MS1
FS2
MS2
RSEL
GTi
TRST
MT9075
TTIP
To
TX Line
XFMR
SEC
F0o
C4o
OSCi
+5V
CLOCK
Out
20 MHz ±32 ppm
F0i
C4i
RRING
RxFP
LOS
External Stimulus
CONTROLLER
MT8985
STo0
STi0
STo1
STi1
F0i
C4i
Figure 16 - Dual E1 Reference Sources with MT9044 in 8 kHz Manual Control
Dual E1 Reference Sources with MT9044 in Manual Control
For systems requiring complex state machine control, the application circuit shown in Figure 16 using Manual
Control may be used.
In this circuit, the MT9044 is operating Manually and is using a controller for all mode changes. The controller sets
the MT9044 modes (Normal, Holdover or Freerun) by controlling the MT9044 mode/control select pins (MS2 and
MS1). The input (Primary or Secondary) is selected with the reference select pin (RSEL). TIE correction from
Primary Holdover Mode to Primary Normal Mode is enabled and disabled with the guard time input pin (GTi). The
input to output phase alignment is re-aligned with the TIE circuit reset pin (TCLR), and a complete device reset is
done with the RST pin.
The controller uses two stimulus inputs (LOS) directly from the MT9075 E1 interfaces, as well as an external
stimulus input. The external input may come from a device that monitors the status registers of the E1 interfaces,
and outputs a logic one in the event of an unacceptable status condition.
25
Zarlink Semiconductor Inc.
MT9044
Data Sheet
For complete Manual Control state machine details, refer to Table 4 for the State Table, and Figure 7 for the State
Diagram.
Single Reference Source E1 to STS-3 with 8 kHz Reference
The device may operate in freerun mode or with a single reference source. The 8 kHz output from the MT9075 is
sourced from the clock extracted from the E1 trunk. It becomes the reference for the PLL which then generates STBUS signals F0o, C4o and C2o to form the system backplane clock. The MT90840 connects to the system
backplane, as well as to an OC3 link via an STS-3 Framer and optical link. The 19.44 Mhz clock required by the
MT90840 is generated by the MT9044. In the event that the E1 link is broken, the LOS output of the MT9075 goes
high placing the MT9044 in freerun mode.
To E1 Line
MT9075
DSTo
DSTi
TTIP
To
TX Line
XFMR
TRING
F0i
C4i
RTIP
To
RX Line
XFMR
RRING
MT9044
RxFP
PRI
LOS
To OC3 Line
To
TX Line
XFMR
To
RX Line
XFMR
LOS1 C1.5o
LOS2
FS1
MS1
FS2
MS2
RSEL
OSCi
TCLR C19o
ACKi
RST
ACKo
GTi
MT90840
PDo0-7 STo0-7
STi0-7
PPFTo
PDi0-7
PCKR
1 kΩ
F0i
C4b
PCKT
F0o
C4o
10 kΩ
+5V
+5V
PPFRi
10 nF
MT90820
STo0
STi0
STo1-8
STi1-8
F0i
C4i
Figure 17 - Single Source - E1 to STS-3 with 8 kHz Reference
26
Zarlink Semiconductor Inc.
CLOCK
Out
20 MHz ±32 ppm
MT9044
Data Sheet
Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated
Parameter
Symbol
Min.
Max.
Units
1
Supply voltage
VDD
-0.3
7.0
V
2
Voltage on any pin
VPIN
-0.3
VDD+0.3
V
3
Current on any pin
IPIN
20
mA
4
Storage temperature
TST
125
°C
5
PLCC package power dissipation
PPD
900
mW
900
6 MQFP package power dissipation
PPD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
mW
-55
Recommended Operating Conditions* - * Voltages are with respect to ground (VSS) unless otherwise stated
Characteristics
1
Supply voltage
2
Operating temperature
Sym.
Min.
Max.
Units
VDD
4.5
5.5
V
TA
-40
85
°C
DC Electrical Characteristics* - * Voltages are with respect to ground (VSS) unless otherwise stated
Characteristics
1
Supply current with:
2
Sym.
Min.
Max.
Units
Conditions/Notes
OSCi = 0 V
IDDS
10
mA
Outputs unloaded
OSCi = Clock
IDD
90
mA
Outputs unloaded
2.0
3
TTL high-level input voltage
VIH
4
TTL low-level input voltage
VIL
5
CMOS high-level input voltage
VCIH
6
CMOS low-level input voltage
VCIL
7
Schmitt high-level input voltage
VSIH
8
Schmitt low-level input voltage
VSIL
9
Schmitt hysteresis voltage
VHYS
0.4
10
Input leakage current
IIL
-10
11
High-level output voltage
VOH
2.4 V
12
Low-level output voltage
VOL
V
0.8
0.7VDD
0.3VDD
3.4
0.8
+10
0.4 V
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
27
Zarlink Semiconductor Inc.
V
V
OSCi
V
OSCi
V
GTi, RST
Note the typical value is
3.1 volts at VDD = 5.0
volts
V
GTi, RST
V
GTi, RST
µA
VI = VDD or 0 V
V
IOH = 10 mA
V
IOL = 10 mA
MT9044
Data Sheet
AC Electrical Characteristics - Performance
Characteristics
Min.
Max.
Units
Conditions/Notes†
±±0 ppm
-0
+0
ppm
5-8
2
±32 ppm
-32
+32
ppm
5-8
3
±100 ppm
-100
+100
ppm
5-8
±0 ppm
-0.05
+0.05
ppm
1,2,4,6-8,40
5
±32 ppm
-0.05
+0.05
ppm
1,2,4,6-8,40
6
±100 ppm
-0.05
+0.05
ppm
1,2,4,6-8,40
±0 ppm
-230
+230
ppm
1-3,6-8
8
±32 ppm
-198
+198
ppm
1-3,6-8
9
±100 ppm
-130
+130
ppm
1-3,6-8
30
s
1-3,6-14
200
ns
1
4
7
Sym.
Freerun Mode accuracy with OSCi at:
Holdover Mode accuracy with OSCi at:
Capture range with OSCi at:
10
Phase lock time
11
Output phase continuity with:
switch
reference
1-3,6-14
12
mode switch to Normal
200
ns
1-2,4-14
13
mode switch to Freerun
200
ns
1-,4,6-14
14
mode switch to Holdover
50
ns
1-3,6-14
15
MTIE (maximum time interval error)
600
ns
1-14,27
16
Output phase slope
45
us/s
1-14,27
17
Reference input for Auto-Holdover with:
8 kHz
-18 k
+18 k
ppm
1-3,6,9-11
18
1.544 MHz
-36 k
+36 k
ppm
1-3,7,9-11
19
2.048 MHz
-36 k
+36 k
ppm
1-3,8-11
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are with respect to
ground (VSS) unless otherwise stated
Characteristics
Sym.
Schmitt
TTL
CMOS
Units
VT
1.5
1.5
0.5VDD
V
1
Threshold Voltage
2
Rise and Fall Threshold Voltage High
VHM
2.3
2.0
0.7VDD
V
3
Rise and Fall Threshold Voltage Low
VLM
0.8
0.8
0.3VDD
V
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Timing for input and output signals is based on the worst case result of the combination of TTL and CMOS thresholds.
* See Figure 18.
28
Zarlink Semiconductor Inc.
MT9044
Data Sheet
Timing Reference Points
V HM
VT
V LM
ALL SIGNALS
tIRF, tORF
tIRF, tORF
Figure 18 - Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics - Input/Output Timing
Characteristics
Sym.
Min.
100
1
Reference input pulse width high or low
tRW
2
Reference input rise or fall time
tIRF
3
8 kHz reference input to F8o delay
tR8D
4
1.544 MHz reference input to F8o delay
5
Max.
Units
ns
10
ns
-21
6
ns
tR15D
337
363
ns
2.048 MHz reference input to F8o delay
tR2D
222
238
ns
6
F8o to F0o delay
tF0D
110
134
ns
7
F16o setup to C16o falling
tF16S
11
35
ns
8
F16o hold from C16o rising
tF16H
0
20
ns
9
F8o to C1.5o delay
tC15D
-51
-37
ns
10
F8o to C6o delay
tC6D
-3
11
ns
11
F8o to C3o delay
tC3D
-51
-37
ns
12
F8o to C2o delay
tC2D
-13
2
ns
13
F8o to C4o delay
tC4D
-13
2
ns
14
F8o to C8o delay
tC8D
-13
2
ns
15
F8o to C16o delay
tC16D
-13
2
ns
16
F8o to TSP delay
tTSPD
-10
10
ns
17
F8o to RSP delay
tRSPD
-10
10
ns
18
F8o to C19o delay
tC19D
0
52
ns
19
C1.5o pulse width high or low
tC15W
309
339
ns
20
C3o pulse width high or low
tC3W
149
175
ns
21
C6o pulse width high or low
tC6W
72
86
ns
22
C2o pulse width high or low
tC2W
230
258
ns
23
C4o pulse width high or low
tC4W
111
133
ns
24
C8o pulse width high or low
tC8W
52
70
ns
25
C16o pulse width high or low
tC16WL
24
35
ns
26
TSP pulse width high
tTSPW
478
494
ns
29
Zarlink Semiconductor Inc.
MT9044
Data Sheet
AC Electrical Characteristics - Input/Output Timing
Characteristics
Sym.
Min.
Max.
Units
27
RSP pulse width high
tRSPW
474
491
ns
28
C19o pulse width high or low
tC19W
16
36
ns
29
F0o pulse width low
tF0WL
230
258
ns
30
F8o pulse width high
tF8WH
111
133
ns
31
F16o pulse width low
tF16WL
52
70
ns
32
Output clock and frame pulse rise or fall time
9
ns
33
Input Controls Setup Time
tS
100
ns
34
Input Controls Hold Time
tH
100
ns
tORF
† See "Notes" following AC Electrical Characteristics tables.
tR8D
PRI/SEC
8 kHz
tRW
tR15D
PRI/SEC
1.544 MHz
VT
tRW
VT
tR2D
PRI/SEC
2.048 MHz
tRW
VT
VT
F8o
NOTES:
1. Input to output delay values
are valid after a TRST or RST
with no further state changes
Figure 19 - Input to Output Timing (Normal Mode)
30
Zarlink Semiconductor Inc.
MT9044
Data Sheet
tF8WH
VT
F8o
tF0D
tF0WL
VT
F0o
tF16WL
VT
F16o
tF16S
tF16H
tC16WL
tC16D
VT
C16o
tC8W
tC8W
tC8D
VT
C8o
tC4W
tC4W
tC4D
VT
C4o
tC2D
tC2W
C2o
tC6W
tC6W
tC6D
C6o
tC3W
tC3W
VT
VT
tC3D
VT
C3o
tC15D
tC15W
VT
C1.5o
tC19D
tC19W
VT
C19o
Figure 20 - Output Timing 1
F8o
VT
VT
C2o
tRSPD
VT
RSP
tRSPW
tTSPW
TSP
VT
tTSPD
Figure 21 - Output Timing 2
31
Zarlink Semiconductor Inc.
MT9044
Data Sheet
VT
F8o
tS
tH
MS1,2
LOS1,2
RSEL, GTi
VT
Figure 22 - Input Controls Setup and Hold Timing
AC Electrical Characteristics - Intrinsic Jitter Unfiltered
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Intrinsic jitter at F8o (8 kHz)
0.0002
UIpp
1-14,21-24,28
2
Intrinsic jitter at F0o (8 kHz)
0.0002
UIpp
1-14,21-24,28
3
Intrinsic jitter at F16o (8 kHz)
0.0002
UIpp
1-14,21-24,28
4
Intrinsic jitter at C1.5o (1.544 MHz)
0.030
UIpp
1-14,21-24,29
5
Intrinsic jitter at C2o (2.048 MHz)
0.040
UIpp
1-14,21-24,30
6
Intrinsic jitter at C3o (3.088 MHz)
0.060
UIpp
1-14,21-24,31
7
Intrinsic jitter at C6o (6.312 MHz)
0.120
UIpp
1-14,21-24,31
8
Intrinsic jitter at C4o (4.096 MHz)
0.080
UIpp
1-14,21-24,32
9
Intrinsic jitter at C8o (8.192 MHz)
0.160
UIpp
1-14,21-24,33
10
Intrinsic jitter at C16o (16.384 MHz)
0.320
UIpp
1-14,21-24,34
11
Intrinsic jitter at TSP (8 kHz)
0.0002
UIpp
1-14,21-24,28
12
Intrinsic jitter at RSP (8 kHz)
0.0002
UIpp
1-14,21-24,28
13
Intrinsic jitter at C19o (19.44 MHz)
0.23
UIpp
1-14,21-24,41
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C1.5o (1.544 MHz) Intrinsic Jitter Filtered
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Intrinsic jitter (4 Hz to 100 kHz filter)
0.015
UIpp
1-14,21-24,29
2
Intrinsic jitter (10 Hz to 40 kHz filter)
0.010
UIpp
1-14,21-24,29
3
Intrinsic jitter (8 kHz to 40 kHz filter)
0.010
UIpp
1-14,21-24,29
4
Intrinsic jitter (10 Hz to 8 kHz filter)
0.005
UIpp
1-14,21-24,29
† See "Notes" following AC Electrical Characteristics tables.
32
Zarlink Semiconductor Inc.
MT9044
Data Sheet
AC Electrical Characteristics - C2o (2.048 MHz) Intrinsic Jitter Filtered
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Intrinsic jitter (4 Hz to 100 kHz filter)
0.015
UIpp
1-14,21-24,30
2
Intrinsic jitter (10 Hz to 40 kHz filter)
0.010
UIpp
1-14,21-24,30
3
Intrinsic jitter (8 kHz to 40 kHz filter)
0.010
UIpp
1-14,21-24,30
4
Intrinsic jitter (10 Hz to 8 kHz filter)
0.005
UIpp
1-14,21-24,30
† See "Notes" following AC Electrical Characteristics tables
AC Electrical Characteristics - 8 kHz Input to 8 kHz Output Jitter Transfer
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Jitter attenuation for 1 [email protected] UIpp input
0
6
dB
1-3,6,9-14,21-22,24,28,35
2
Jitter attenuation for 1 [email protected] UIpp input
6
16
dB
1-3,6,9-14,21-22,24,28,35
3
Jitter attenuation for 10 [email protected] UIpp input
12
22
dB
1-3,6,9-14,21-22,24,28,35
4
Jitter attenuation for 60 [email protected] UIpp input
28
38
dB
1-3,6,9-14,21-22,24,28,35
5
Jitter attenuation for 300 [email protected] UIpp input
42
dB
1-3,6,9-14,21-22,24,28,35
6
Jitter attenuation for 3600 [email protected] UIpp
input
45
dB
1-3,6,9-14,21-22,24,28,35
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 1.544 MHz Input to 1.544 MHz Output Jitter Transfer
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Jitter attenuation for 1 Hz@20 UIpp input
0
6
dB
1-3,7,9-14,21-22,24,29,35
2
Jitter attenuation for 1 Hz@104 UIpp input
6
16
dB
1-3,7,9-14,21-22,24,29,35
3
Jitter attenuation for 10 Hz@20 UIpp input
12
22
dB
1-3,7,9-14,21-22,24,29,35
4
Jitter attenuation for 60 Hz@20 UIpp input
28
38
dB
1-3,7,9-14,21-22,24,29,35
5
Jitter attenuation for 300 Hz@20 UIpp input
42
dB
1-3,7,9-14,21-22,24,29,35
6
Jitter attenuation for 10 [email protected] UIpp input
45
dB
1-3,7,9-14,21-22,24,29,35
7
Jitter attenuation for 100 [email protected] UIpp
input
45
dB
1-3,7,9-14,21-22,24,29,35
† See "Notes" following AC Electrical Characteristics tables.
33
Zarlink Semiconductor Inc.
MT9044
Data Sheet
AC Electrical Characteristics - 2.048 MHz Input to 2.048 MHz Output Jitter Transfer
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Jitter at output for 1 [email protected] UIpp input
2.9
UIpp
1-3,8,9-14,21-22,24,30,35
2
with 40 Hz to 100 kHz filter
0.09
UIpp
1-3,8,9-14,21-22,24,30,36
3
Jitter at output for 3 [email protected] UIpp input
1.3
UIpp
1-3,8,9-14,21-22,24,30,35
4
with 40 Hz to 100 kHz filter
0.10
UIpp
1-3,8,9-14,21-22,24,30,36
5
Jitter at output for 5 [email protected] UIpp input
0.80
UIpp
1-3,8,9-14,21-22,24,30,35
6
with 40 Hz to 100 kHz filter
0.10
UIpp
1-3,8,9-14,21-22,24,30,36
7
Jitter at output for 10 [email protected] UIpp input
0.40
UIpp
1-3,8,9-14,21-22,24,30,35
8
with 40 Hz to 100 kHz filter
0.10
UIpp
1-3,8,9-14,21-22,24,30,36
9
Jitter at output for 100 [email protected] UIpp input
0.06
UIpp
1-3,8,9-14,21-22,24,30,35
10
with 40 Hz to 100 kHz filter
0.05
UIpp
1-3,8,9-14,21-22,24,30,36
11
Jitter at output for 2400 [email protected] UIpp input
0.04
UIpp
1-3,8,9-14,21-22,24,30,35
12
with 40 Hz to 100 kHz filter
0.03
UIpp
1-3,8,9-14,21-22,24,30,36
13
Jitter at output for 100 [email protected] UIpp input
0.04
UIpp
1-3,8,9-14,21-22,24,30,35
14
with 40 Hz to 100 kHz filter
0.02
UIpp
1-3,8,9-14,21-22,24,30,36
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 8 kHz Input Jitter Tolerance
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Jitter tolerance for 1 Hz input
0.80
UIpp
1-3,6,9-14,21-22,24-26,28
2
Jitter tolerance for 5 Hz input
0.70
UIpp
1-3,6,9-14,21-22,24-26,28
3
Jitter tolerance for 20 Hz input
0.60
UIpp
1-3,6,9-14,21-22,24-26,28
4
Jitter tolerance for 300 Hz input
0.20
UIpp
1-3,6,9-14,21-22,24-26,28
5
Jitter tolerance for 400 Hz input
0.15
UIpp
1-3,6,9-14,21-22,24-26,28
6
Jitter tolerance for 700 Hz input
0.08
UIpp
1-3,6,9-14,21-22,24-26,28
7
Jitter tolerance for 2400 Hz input
0.02
UIpp
1-3,6,9-14,21-22,24-26,28
8
Jitter tolerance for 3600 Hz input
0.01
UIpp
1-3,6,9-14,21-22,24-26,28
† See "Notes" following AC Electrical Characteristics tables.
34
Zarlink Semiconductor Inc.
MT9044
Data Sheet
AC Electrical Characteristics - 1.544 MHz Input Jitter Tolerance
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Jitter tolerance for 1 Hz input
150
UIpp
1-3,7,9-14,21-22,24-26,29
2
Jitter tolerance for 5 Hz input
140
UIpp
1-3,7,9-14,21-22,24-26,29
3
Jitter tolerance for 20 Hz input
130
UIpp
1-3,7,9-14,21-22,24-26,29
4
Jitter tolerance for 300 Hz input
35
UIpp
1-3,7,9-14,21-22,24-26,29
5
Jitter tolerance for 400 Hz input
25
UIpp
1-3,7,9-14,21-22,24-26,29
6
Jitter tolerance for 700 Hz input
15
UIpp
1-3,7,9-14,21-22,24-26,29
7
Jitter tolerance for 2400 Hz input
4
UIpp
1-3,7,9-14,21-22,24-26,29
8
Jitter tolerance for 10 kHz input
1
UIpp
1-3,7,9-14,21-22,24-26,29
9
Jitter tolerance for 100 kHz input
0.5
UIpp
1-3,7,9-14,21-22,24-26,29
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 2.048 MHz Input Jitter Tolerance
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes†
1
Jitter tolerance for 1 Hz input
150
UIpp
1-3,8,9-14,21-22,24-26,30
2
Jitter tolerance for 5 Hz input
140
UIpp
1-3,8,9-14,21-22,24-26,30
3
Jitter tolerance for 20 Hz input
130
UIpp
1-3,8,9-14,21-22,24-26,30
4
Jitter tolerance for 300 Hz input
50
UIpp
1-3,8,9-14,21-22,24-26,30
5
Jitter tolerance for 400 Hz input
40
UIpp
1-3,8,9-14,21-22,24-26,30
6
Jitter tolerance for 700 Hz input
20
UIpp
1-3,8,9-14,21-22,24-26,30
7
Jitter tolerance for 2400 Hz input
5
UIpp
1-3,8,9-14,21-22,24-26,30
8
Jitter tolerance for 10 kHz input
1
UIpp
1-3,8,9-14,21-22,24-26,30
9
Jitter tolerance for 100 kHz input
1
UIpp
1-3,8,9-14,21-22,24-26,30
† See "Notes" following AC Electrical Characteristics tables.
35
Zarlink Semiconductor Inc.
MT9044
Data Sheet
AC Electrical Characteristics - OSCi 20 MHz Master Clock Input
Characteristics
1
2
Sym.
Frequency accuracy
(20 MHz nominal)
3
Min.
Max.
Units
-0
+0
ppm
15,18
-32
+32
ppm
16,19
-100
+100
ppm
17,20
40
60
%
4
Duty cycle
5
Rise time
10
ns
6
Fall time
10
ns
Conditions/Notes†
† See "Notes" following AC Electrical Characteristics tables.
† Notes:
Voltages are with respect to ground (V SS) unless otherwise stated.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1. PRI reference input selected.
2. SEC reference input selected.
3. Normal Mode selected.
4. Holdover Mode selected.
5. Freerun Mode selected.
6. 8 kHz Frequency Mode selected.
7. 1.544 MHz Frequency Mode selected.
8. 2.048 MHz Frequency Mode selected.
9. Master clock input OSCi at 20 MHz ±0 ppm.
10. Master clock input OSCi at 20 MHz ±32 ppm.
11. Master clock input OSCi at 20 MHz ±100 ppm.
12. Selected reference input at ±0 ppm.
13. Selected reference input at ±32 ppm.
14. Selected reference input at ±100 ppm.
15. For Freerun Mode of ±0 ppm.
16. For Freerun Mode of ±32 ppm.
17. For Freerun Mode of ±100 ppm.
18. For capture range of ±230 ppm.
19. For capture range of ±198 ppm.
20. For capture range of ±130 ppm.
21. 25 pF capacitive load.
22. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where1 UIpp = 1/20 MHz.
23. Jitter on reference input is less than 7 nspp.
24. Applied jitter is sinusoidal.
25. Minimum applied input jitter magnitude to regain synchronization.
26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
27. Within 10 ms of the state, reference or input change.
28. 1 UIpp = 125 us for 8 kHz signals.
29. 1 UIpp = 648 ns for 1.544 MHz signals.
30. 1 UIpp = 488 ns for 2.048 MHz signals.
31. 1 UIpp = 323 ns for 3.088 MHz signals.
32. 1 UIpp = 244 ns for 4.096 MHz signals.
33. 1 UIpp = 122 ns for 8.192 MHz signals.
34. 1 UIpp = 61 ns for 16.384 MHz signals.
35. No filter.
36. 40 Hz to 100 kHz bandpass filter.
37. With respect to reference input signal frequency.
38. After a RST or TRST.
39. Master clock duty cycle 40% to 60%.
40. Prior to Holdover Mode, device was in Normal Mode and phase locked.
41. 1 Ulpp = 51 ns for 19.44 MHz signals.
36
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