ISO-CMOS MT8980D Family ST-BUSTM Digital Switch Data Sheet Features April 2011 • Zarlink ST-BUS compatible • 8-line x 32-channel inputs • 8-line x 32-channel outputs • 256 ports non-blocking switch • Single power supply (+5 V) • Low power consumption: 30 mW Typ. • Microprocessor-control interface • Three-state serial outputs Ordering Information MT8980DP1 MT8980DE1 MT8980DPR1 44 Pin PLCC* 40 Pin PDIP* 44 Pin PLCC* Tubes Tubes Tape & Reel *Pb Free Matte Tin -40°C to +85°C Description This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT8980 provides microprocessor read and write access to individual ST-BUS channels. Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved. MT8980D Data Sheet Change Summary Changes from February 2005 Issue to April 2011 Issue. Page 1 Item Change Ordering Information Obsolete Leaded packages, only Pb Free packages are available. Figure 2 - Pin Connections Pin Descripton Pin # 40 DIP 44 PLCC Name Description 1 2 DTA Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A 909 1/4W, resistor is recommended to be used as a pullup. 2-4 3-5 STi0STi2 ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input streams. 5-9 7-11 STi3STi7 ST-BUS Input 3 to 7 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input streams. 10 12 VDD Power Input. Positive Supply. 11 13 F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i. 2 Zarlink Semiconductor Inc. MT8980D Data Sheet Pin Descripton Pin # 40 DIP 44 PLCC Name Description 12 14 C4i 13-15 15-17 A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor interface. 16-18 19-21 A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor interface. 19 22 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. 20 23 R/W Read or Write (Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. 21 24 CS Chip Select (Input). This is the input for the active low chip select on the microprocessor interface. 22-24 25-27 D7-D5 Data 7 to 5 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. 25-29 29-33 D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. 30 34 VSS 31-35 35-39 STo7STo3 ST-BUS Output 7 to 3 (Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams. 36-38 41-43 STo2STo0 ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams. 39 44 ODE Output Drive Enable (Input). If this input is held high, the STo0-STo7 output drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0STo7 outputs can go high impedance under software control. 40 1 CSTo Control ST-BUS Output (Complementary Output). Each frame of 256 bits on this ST-BUS output contains the values of bit 1 in the 256 locations of the Connection Memory High. 6, 18, 28, 40 NC 4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock. Power Input. Negative Supply (Ground). No Connection. Functional Description In recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future. 3 Zarlink Semiconductor Inc. MT8980D Data Sheet The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key device being the MT8980 chip. The MT8980 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs (Message Mode). To the microprocessor, the MT8980 looks like a memory peripheral. The microprocessor can write to the MT8980 to establish switched connections between input ST-BUS channels and output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT8980, the microprocessor can receive messages from ST-BUS input channels or check which switched connections have already been established. By integrating both switching and interprocessor communications, the MT8980 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture. Hardware Description Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., Zarlink’s MT8964). This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT8980s to be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the two signals C4i and F0i. 4 Zarlink Semiconductor Inc. MT8980D Data Sheet Figure 3 - Address Memory Map Software Control The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory. If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits define one of the ST-BUS input or output streams. 5 Zarlink Semiconductor Inc. MT8980D Data Sheet Figure 4 - Control Register Bits Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values. If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the STBUS input stream and channel where the byte is to be found (see Fig. 6). If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5). Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0. 6 Zarlink Semiconductor Inc. MT8980D Figure 5 - Connection Memory High Bits Figure 6 - Connection Memory Low Bits 7 Zarlink Semiconductor Inc. Data Sheet MT8980D Data Sheet Applications Use in a Simple Digital Switching System Figs. 7 and 8 show how MT8980s can be used with MT8964s to form a simple digital switching system. Fig. 7 shows the interface between the MT8980s and the filter/codecs. Fig. 8 shows the position of these components in an example architecture. The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and STBUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT8980, which is used as a digital speech switch. The MT8964 is controlled by the ST-BUS input DC originating from the bottom MT8980, which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on the bottom MT8980. Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a private telephone network with 256 extensions which uses a single MT8980 as a speech switch and a second MT8980 for communication with the line interface circuits. A larger digital switching system may be designed by cascading a number of MT8980s. Fig. 9 shows how four MT8980s may be arranged in a non-blocking configuration which can switch any channel on any of the ST-BUS inputs to any channel on the ST-BUS outputs. Figure 7 - Example of Typical Interface between 8980s and 8964s for Simple Digital Switching System 8 Zarlink Semiconductor Inc. MT8980D Data Sheet Figure 8 - Example Architecture of a Simple Digital Switching System Figure 9 - Four 8980s Arranged in a Non-Blocking 16 x 16 Configuration 9 Zarlink Semiconductor Inc. MT8980D Data Sheet Application Circuit with 6802 Processor Fig. 10 shows an example of a complete circuit which may be used to evaluate the chip. For convenience, a 4 MHz crystal oscillator has been used rather than a 4.096 MHz clock, as both are within the limits of the chip’s specifications. The RC delay used with the 393 counters ensures a sufficient hold time for the FP signal, but the values used may have to be changed if faster 393 counters become available. The chip is shown as memory mapped into the MEK6802D3 system. Chip addresses 00-3F correspond to processor addresses 2000-203F. Delay through the address decoder requires the VMA signal to be used twice to remove glitches. The MEK6802D3 board uses a 10 KΩ pullup on the MR pin, which would have to be incorporated into the circuit if the board was replaced by a processor. 10 Zarlink Semiconductor Inc. MT8980D Figure 10 - Application Circuit with 6802 11 Zarlink Semiconductor Inc. Data Sheet MT8980D Data Sheet Absolute Maximum Ratings* Parameter Symbol Min. Max. Units -0.3 7 V 1 VDD - VSS 2 Voltage on Digital Inputs VI VSS-0.3 VDD+0.3 V 3 Voltage on Digital Outputs VO VSS-0.3 VDD+0.3 V 4 Current at Digital Outputs IO 40 mA 5 Storage Temperature TS +150 °C 6 Package Power Dissipation PD 2 W -65 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. Typ.‡ Max. Units 1 Operating Temperature TOP -40 +85 °C 2 Positive Supply VDD 4.75 5.25 V 3 Input Voltage VI 0 VDD V Test Conditions ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 I N P U T S O U T P U T S Sym. Min. Typ.‡ Supply Current IDD 6 10 Input High Voltage VIH Input Low Voltage VIL 0.8 V Input Leakage IIL 5 µA Input Pin Capacitance CI 2.0 VOH 2.4 Output High Current IOH 10 Output Low Voltage VOL Output Low Current IOL High Impedance Leakage IOZ Output Pin Capacitance CO Outputs unloaded V 8 Output High Voltage mA pF V 15 mA 0.4 5 10 5 8 VI between VSS and VDD V IOH = 10 mA Sourcing. VOH=2.4V IOL = 5 mA mA Sinking. VOL = 0.4V µA VO between VSS and VDD pF ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 12 Zarlink Semiconductor Inc. MT8980D Data Sheet Figure 11 - Output Test Load AC Electrical Characteristics† - Clock Timing (Figures 12 and 13) Sym. Min. Typ.‡ Max. Units Clock Period* tCLK 220 244 300 ns Clock Width High tCH 95 122 150 ns Clock Width Low tCL 110 122 150 ns Clock Transition Time tCTT Frame Pulse Setup Time tFPS 20 200 ns Frame Pulse Hold Time tFPH 0.020 50 µs Frame Pulse Width tFPW Characteristics 1 2 3 4 5 6 7 I N P U T S 20 Test Conditions ns 244 ns † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i. Figure 12 - Frame Alignment 13 Zarlink Semiconductor Inc. MT8980D Data Sheet Figure 13 - Clock Timing AC Electrical Characteristics† - Serial Streams (Figures 11, 14, 15 and 16) Sym. Min. Typ.‡ Max, Units STo0/7 Delay - Active to High Z tSAZ 20 50 80 ns RL=1 KΩ*, CL=150 pF ISTo0/7 Delay - High Z to Active tSZA 25 60 125 ns CL=150 pF STo0/7 Delay - Active to Active tSAA 30 65 125 ns CL=150 pF STo0/7 Hold Time tSOH 25 45 ns CL=150 pF Output Driver Enable Delay tOED ns RL=1 KΩ*, CL=150 pF External Control Hold Time tXCH ns CL=150 pF External Control Delay tXCD 75 110 ns CL=150 pF Serial Input Setup Time tSIS -40 -20 ns Serial Input Hold Time tSIH Characteristics 1 2 3 4 5 6 O U T P U T S 7 8 9 I N 45 0 125 50 90 Test Conditions ns † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 14 Zarlink Semiconductor Inc. MT8980D Figure 14 - Serial Outputs and External Control Figure 15 - Output Driver Enable 15 Zarlink Semiconductor Inc. Data Sheet MT8980D Data Sheet Figure 16 - Serial Inputs AC Electrical Characteristics† - Processor Bus (Figures 11 and 17) Characteristics Sym. Min. Typ.‡ 1 Chip Select Setup Time tCSS 20 0 ns 2 Read/Write Setup Time tRWS 25 5 ns 3 Address Setup Time tADS 25 5 ns 4 Acknowledgement Delay 40 Fast tAKD Slow tAKD 2.7 20 5 Fast Write Data Setup Time tFWS 6 Slow Write Data Delay tSWD 7 Read Data Setup Time tRDS 8 Data Hold Time tDHT 20 Write tDHT 20 Units Test Conditions 100 ns CL=150 pF 7.2 cycles C4i cycles1 ns 2.0 Read Max. 1.7 cycles C4i cycles1 0.5 cycles C4i cycles1, CL= 150 pF ns RL=1 KΩ*, CL=150 pF 10 50 ns 90 ns 9 Read Data To High Impedance tRDZ 10 Chip Select Hold Time tCSH 0 ns 11 Read/Write Hold Time tRWH 0 ns 12 Address Hold Time tADH 0 ns 13 Acknowledgement Hold Time tAKH 10 60 80 ns RL=1 KΩ*, CL=150 pF RL=1 KΩ*, CL=150 pF † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Note 1. Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period. 16 Zarlink Semiconductor Inc. MT8980D Figure 17 - Processor Bus 17 Zarlink Semiconductor Inc. Data Sheet For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE