CMOS ST-BUSTM Family MT89L85 Enhanced Digital Switch Data Sheet Features February 2006 • 3.3 volt supply • 5 V tolerant inputs and TTL compatible outputs • 256 x 256 channel non-blocking switch • Programmable frame integrity for wideband channels • Automatic identification of ST-BUS/GCI interface backplanes • Per channel tristate control Description • Patented message mode • Non-multiplexed microprocessor interface • Available in PLCC-44 and SSOP-48 packages • Pin compatible with MT8985 device • Low power consumption The MT89L85 Enhanced Digital Switch device is an upgraded 3-volt version of the MT8985 Digital Switch. It is pin compatible with the MT8985 and retains all of the MT8985's functionality. The enhanced digital switch is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs and any ST-BUS/MVIP environment. It provides simultaneous connections for up to 256 64 kb/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. As the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. The constant throughput delay feature allows grouped channels such as ISDN H0 to be switched through the device maintaining its sequence integrity. The MT89L85 is ideal for medium sized mixed voice/data switch and voice processing applications. Ordering Information MT89L85AP 44 Pin PLCC Tubes MT89L85AN 48 Pin SSOP Tubes MT89L85APR 44 Pin PLCC Tape & MT89L85ANR 48 Pin SSOP Tape & MT89L85AN1 48 Pin SSOP* Tubes MT89L85ANR1 48 Pin SSOP* Tape & MT89L85AP1 44 Pin PLCC* Tubes MT89L85APR1 44 Pin PLCC* Tape & *Pb Free Matte Tin Medium size digital switch matrices • Hyperchannel switching (e.g., ISDN H0) • ST-BUS/MVIP™ interface functions • Serial bus control and monitoring • Centralized voice processing systems • Data multiplexer C4i ** F0i RESET VDD VSS Frame Counter STi0 STi3 STi4 STi5 Serial to Parallel Converter Data Memory Control Register STi6 STi7 Connection Memory STo0 Parallel to Serial Converter DS CS R/W A5/ A0 DTA D7/ D0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 Control Interface ** for 48-pin SSOP only Reel ODE Output MUX STi1 STi2 Reel -40°C to +85°C Applications • Reel Reel CSTo Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved. MT89L85 NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 NC A3 A4 A5 DS R/W CS D7 D6 D5 NC 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS DTA STi0 STi1 STi2 NC STi3 STi4 STi5 STi6 STi7 VDD RESET F0i C4i A0 A1 A2 NC A3 A4 A5 DS R/W 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 Data Sheet 44 PIN PLCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS VDD D0 D1 D2 D3 D4 NC D5 D6 D7 CS VSS 48 PIN SSOP (JEDEC MO-118, 300mil Wide) Figure 2 - Pin Connections Pin Description Pin # 44 48 SSOP PLCC 2 2 3-5 7-11 3-5 7-11 12 12,36 13 Name DTA Description Data Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 channels at STi7 data rates of 2.048 Mbit/s. VDD +3.3 Volt Power Supply. RESET Device Reset (5V tolerant input). This pin is only available for the 48-pin SSOP package. This active low input puts the MT89L85 in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. This RESET pin must be held low for a minimum of 100nsec to reset the device. 13 14 F0i Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. 14 15 C4i Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams. 15-17 19-21 16-18 20-22 22 23 A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT89L85 internal registers. DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. 2 Zarlink Semiconductor Inc. MT89L85 Data Sheet Pin Description Pin # 44 48 SSOP PLCC Name Description Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. 23 24 R/W 24 26 CS 25-27 29-33 27-29 31-35 34 1,25,37 35-39 41-43 38-42 44-46 44 47 ODE 1 48 CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. 6,18, 28,40 6,19,30,4 3 Chip Select (Input). Active low input enabling a microprocessor read or write of control register or internal memories. D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data in the internal control register, connect memory high, connect memory low and data memory. VSS Ground Rail. STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These streams are STo0 composed of 32 channels at data rates of 2.048 Mbit/s. NC Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control. No Connection. Functional Description With the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. Existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels. The MT89L85 device provides both functions and allows existing systems based on the MT8985 to be easily upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The MT89L85 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces through the ST-BUS interface. Different digital backplanes can be accepted by the MT89L85 device without user's intervention. The MT89L85 device provides an internal circuit that automatically identifies the polarity and format of frame synchronization input signals compatible to ST-BUS and GCI interfaces. Device Operation A functional block diagram of the MT89L85 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 µs wide frames each containing 32 8-bit channels. Eight input (STi0-7) and eight output (STo0-7) serial streams are provided in the MT89L85 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications. 3 Zarlink Semiconductor Inc. MT89L85 Data Sheet Data Memory The received serial data is converted to parallel format by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memory. The sequential addressing of the Data Memory is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams. Depending on the type of information to be switched, the MT89L85 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, the variable delay mode can be selected ensuring minimum throughput delay between input and output data. In multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of the information through the switch. Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input (connection mode) or it can be originated from the microprocessor (message mode). If a channel is configured in connection mode, the source of the output data is the Data Memory. If a channel is configured in message mode, the source of the output data is the Connect Memory Low. Data destined for a particular channel on the serial output stream is read from the Data or Connect Memory Low during the previous channel time slot. This allows enough time for memory access and internal parallel to serial conversion. Connection and Message Modes In connection mode, the addresses of input source for all output channels are stored in the Connect memory Low. The Connect Memory Low locations are mapped to each location corresponding to an output 64 kb/s channel. The contents of the Data memory at the selected address are then transferred to the parallel to serial converters. By having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch. In message mode the CPU writes data to the Connect Memory Low locations which correspond to the output link and channel number. The contents of the Connect Memory Low are transferred to the parallel to serial converter one channel before it is to be output. The Connect Memory Low data is transmitted each frame to the output until it is changed by the CPU. The per-channel functions available in the MT89L85 are controlled by the Connect Memory High bits, which determine whether individual output channels are selected into specific conditions such as: message or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. In addition, the Connect Memory High provides one bit to allow the user to control the state of the CSTo output pin. If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual perchannel programming on the Connect Memory High bits. The Connect Memory data is received via the Microprocessor Interface at D0-D7 lines. The addressing of the MT89L85 internal registers, Data and Connect memories is performed through address input pins and some bits of the device's Control register. The higher order address bits come from the Control register, which may be written or read through the microprocessor interface. The lower order address bits come directly from the external address line inputs. For details on the device addressing, see Software Control and Control register description. Serial Interface Timing The MT89L85 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be implemented. The MT89L85 frame synchronization pulse can be formatted according to ST-BUS or GCI interface specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT89L85 device automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial 4 Zarlink Semiconductor Inc. MT89L85 Data Sheet interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the 4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. Delay through the MT89L85 The transfer of information from the input serial streams to the output serial streams results in a delay through the MT89L85 device. The delay through the device varies according to the mode selected in the V/C bit of the connect memory high. Variable Delay mode The delay in this mode is dependent only on the combination of source and destination channels and it is not dependent on the input and output streams. The minimum delay achievable in the MT89L85 device is 3 time slots. In the MT89L85 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the information is input. The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. Any switching configuration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the MT89L85 device in Variable Delay mode: Input Channel Output Channel n m=n, n+1 or n+2 m-n + 32 timeslots n m>n+2 m-n time slots n m<n 32-(n-m) time slots Throughput Delay Table 1 - Channel Delays for the Variable Delay Mode Constant Delay Mode In this mode frame integrity is maintained in all switching configurations by making use of a multiple Data-Memory buffer technique where input channels written in any of the buffers during frame N will be read out during frame N+2. In the MT89L85, the minimum throughput delay achieve-able in Constant Delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay. 5 Zarlink Semiconductor Inc. MT89L85 Data Sheet To summarize, any input time slot from input frame N will be always switched to the destination time slot on output frame N+2. In Constant Delay mode, the device throughput delay is calculated according to the following formula: DELAY = [32 + (32 - IN) + (OUT - 1)]; (expressed in number of time slots) Where: IN is the number of the input time slot (from 1 to 32). OUT is the number of the output time slot (from 1 to 32). Microprocessor Port The MT89L85 microprocessor port has pin compatibility with Zarlink MT8985 Digital Switch devices providing a non-multiplexed bus architecture. The parallel port consists of an 8 bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control registers, Connection Memory High, Connection Memory Low and the Data Memory. All locations are read/written except for the data memory which can be read only. Accesses from the microport to the connection memory and the data memory are multiplexed with accesses from the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA). A5 A4 A3 A2 A1 A0 LOCATION 0 1 1 1 1 1 1 1 1 0 0 0 • • • • • 1 0 0 0 • • • • • 1 0 0 0 • • • • • 1 0 0 0 • • • • • 1 0 0 1 • • • • • 1 Control Register Channel 0 Channel 1 • • • • • Channel 31 Figure 3 - Address Memory Map Note: "x" Don’t care. Software Control The address lines on the microprocessor interface give access to the MT89L85 internal registers and memories. If the A5,A1,A0 address line inputs are LOW, then the MT89L85 Internal Control Register is addressed (see Figure 3). If A5 input line is HIGH, then the remaining address input lines are used to select Memory subsections of 32 locations corresponding to the number of channels per input or output stream. As explained in the Control register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of the MT89L85 Data and Connect memories. The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream Address bits (see Figure 4). The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output ST-BUS streams. Bit 7 (Split Memory) of the Control register allows split memory operation whereby reads are from the Data memory and writes are to the Connect Memory LOW. The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the contents of the Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless 6 Zarlink Semiconductor Inc. MT89L85 Data Sheet the ODE input pin is LOW. If ME bit is HIGH, then the MT89L85 behaves as if bits 2 (Message Channel) and 0 (Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value. If ME bit is LOW, then bit 2 and 0 of each Connect Memory HIGH location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated ST-BUS output channel is in Message mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output. If the ODE input pin is LOW, then all serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) the output drivers for the corresponding individual STBUS output stream and channel. The contents of bit 1 (CSTo) of each Connection Memory High location (see Figure 5) is output on CSTo pin once every frame. The CSTo pin is a 2048 Mbit/s output which carries 256 bits. If CSTo bit is set HIGH, the corresponding bit on CSTo output is transmitted in HIGH. If CSTo bit is LOW, the corresponding bit on the CSTo output is transmitted in LOW. The contents of the 256 CSTo bits of the CMH are transmitted sequentially on to the CSTo output pin and are synchronous to the ST-BUS streams. To allow for delay in any external control circuitry the contents of the CSTo bit is output one channel before the corresponding channel on the ST-BUS streams. For example, the contents of CSTo bit in position 0 (ST0, CH0) of the CMH, is transmitted synchronously with ST-BUS channel 31, bit 7. The contents of CSTo bit in position 32 (ST1, CH0) of the CMH is transmitted during ST-BUS channel 31 bit 6. Bit V/C (Variable/Constant Delay) on the Connect Memory High locations allow per-channel selection between Variable and Constant throughput delay capabilities. Initialization of the MT89L85 On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT89L85 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMHb0s. 7 Zarlink Semiconductor Inc. MT89L85 7 6 5 4 SM ME X MS1 3 MS0 Data Sheet 2 1 0 STA2 STA1 STA0 Bit Name Description 7 SM Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. The Memory Select bits need to be set to specify the memory for the operations. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. 6 ME Message Enable. When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when in High Impedance. When 0, the Connection Memory bits for each channel determine what is output. 4-3 MS1-MS0 2-0 STA2-0 Memory Select Bits. The memory select bits operate as follows: 0-0 - Not to be used 0-1 - Data Memory (read only from the CPU) 1-0 - Connection Memory Low 1-1 - Connection Memory High Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations. Figure 4 - Control Register Bits x = Don’t care 8 Zarlink Semiconductor Inc. MT89L85 Data Sheet 7 6 5 4 3 2 1 0 X V/C X X X MC CSTo OE Bit Name Description 6 V/C Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis. 2 MC Message Channel. When 1, the contents of the corresponding location in Connection Memory Low are output on the corresponding channel and stream. When 0, the contents of the programmed location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream. 1 CSTo 0 OE CSTo Bit. This bit drives a bit time on the CSTo output pin. Output Enable. This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it. Figure 5 - Connection Memory High Bits x = Don’t care 7 6 5 4 3 2 1 0 SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0 Bit Name 7-5 SAB2-0* Source Stream Address bits. These three bits are used to select eight source streams for the connection. Bit 7 of each word is the most significant bit. 4-0* CAB4-0* Source Channel Address bits 0-4. These five bits are used to select 32 different source channels for the connection (The ST-BUS stream where the channel is present is defined by bits SAB2-0). Bit 4 is the most significant bit. * Description If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. Figure 6 - Connection Memory Low Bits 9 Zarlink Semiconductor Inc. MT89L85 Data Sheet Applications Typical Exchange, PBX or Multiplexer Figure 7 shows a typical implementation of line cards being interconnected through a central routing matrix that can scale up in channel capacity to accommodate different number of ports depending on the application. In a configuration where the switched services utilize concatenated or grouped time slots to carry voice, data and video (channels of 128, 256 Kb/s, ISDN H0 and others), the central routing matrix has to guarantee constant throughput delay to maintain the sequence integrity between input and output channels. Figure 7 shows an example where the MT89L85 device guarantees data integrity when data flows from the T1/E1 to the S/U interface links and viceversa. Modern technologies available today such as Frame Relay network using dedicated fractional T1 are one of the key applications for the MT89L85 device. To other lines Basic Rate Line Card Layers 2&3 Entity MT8930/31 S/U MT8910 MT8972 C P U ST-BUS ST-BUS To other lines ROUTING MATRIX MT89L85’s ST-BUS T1/E1 Link MT8940/ MT8941 MH89760/ MH89790 MT8920 µC Primary Rate Card Figure 7 - Typical Exchange, PBX or Multiplexer Configuration 10 Zarlink Semiconductor Inc. MT89L85 Data Sheet Low Latency Isochronous Network In today's local working group environment, there is an increasing demand for solutions on interconnection of desktop and telephone systems so that mixed voice, data and video services can be grouped together in a reliable network allowing the deployment of multimedia services. Existing multimedia applications require a network with predictable data transfer delays that can be implemented at a reasonable cost. The Low Latency Isochronous Network is one of the alternatives that system designers have chosen to accommodate this requirement (see Figure 8a). This network can be implemented using existing TDM transmission media devices such as ISDN Basic (S or U) and Primary rates trunks (T1 and CEPT) to transport mixed voice and data signals in grouped time slots; for example, 2B channels in case of ISDN S or U interfaces or up to 32 channels in case of a CEPT link. ISDN Desktops (2B+D) •••••• Analog Connections •••••• Server 2 Server 1 T1 •••••• T1 E1 Access to Public Network Server 3 n x 64 Connections (e.g. Video) Server 4 T1/E1 Isochronous Network Figure 8a - Private Isochronous Network Figure 8b shows a more detailed configuration whereby several PCs are connected to form an Isochronous network. Several services can be interconnected within a single PC chassis through the standardized Multi Vendor Integration Protocol (MVIP). Such an interface allows the distribution and interconnection of services like voice mail, integrated voice response, voice recognition, LAN gateways, key systems, fax servers, video cards, etc. The information being exchanged between cards through the MVIP interface on every computer as well as between computers through T1 or CEPT links is, in general, of mixed type where 64 Kb/s and N*64 Kb/s channels are grouped together. When such a mixed type of data is transferred between cards within one chassis or from one computer to another, the sequence integrity of the concatenated channels has to be maintained. The MT89L85 device suits this application and can be used to form a complete non-blocking switch matrix of 512 channels (see Figure 9). This allows 8 pairs of ST-BUS streams to be dedicated to the MVIP side whereas the remaining 8 pairs are used for local ancilliary functions in typical dual T1/E1 interface applications (Figure 10). Another application of the MT89L85 in an MVIP environment is to build an ISDN S-interface card (Figure 11). In this card, 7 pairs of ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface. 11 Zarlink Semiconductor Inc. MT89L85 Data Sheet To Video, Data, Fax and other services MVIP BUS Server 1 ISDN S-Interface ST-BUS MT89L85s (x4) MH89760B MH89790B MT8930B •• •• •• • MT8930B Local T1/E1 Link MVIP BUS Server 3 (256 PORT SWITCH MODULE) • • • MH89760B/790B ST-BUS MH89760B/790B • • • Server 3 MT89L85s (x4) MH89760B/790B MT89L85 MT89L85 ST-BUS MH89760B T1 MT89L85 MT89L85 E1 Dual T1/E1 Card Local T1/E1 Link MH89760B MH89790B ST-BUS MH89790B HDLC MT8972B or ANALOG •• •• • MT89L85s (x4) Server 2 MVIP BUS To Video, Data, Fax Services Local Environment Public Network Access Figure 8b - Implementation of an Isochronous Network Using Zarlink Components 12 Zarlink Semiconductor Inc. MT89L85 8 Input Streams From MVIP MT89L85 #1 Data Sheet 8 Output Streams to MVIP CSTo MVIP Direction 8 Input On-Board ST-BUS Streams MT89L85 #2 CSTo MVIP Enable MT89L85 #3 MT89L85 #4 Figure 9 - 512-Channel Switch Array 13 Zarlink Semiconductor Inc. 8 Output On-Board ST-BUS Streams MT89L85 Data Sheet MVIP HEADER FDL HDLC MT8952B MVIP STo0-7 MVIP STi0-7 SWITCH MT89L85 512 Channel Switch Matrix SWITCH MT89L85 FDL HDLC MT8952B T1/E1 MH89760B or MH89790B T1/E1 SWITCH MT89L85 SWITCH MT89L85 HDLC MT8952B DPLL MT8941 MH89760B or MH89790B HDLC MT8952B ANALOG D-PHONE MT8992/93 PC INTERFACE Figure 10 - Dual T1/E1 Card Functional Block Diagram 14 Zarlink Semiconductor Inc. MT89L85 Data Sheet MVIP HEADER MVIP STo1-7 STi7-1 MVIP STi1-7 SWITCH MATRIX MT89L85 STi0 STo7-1 STo0 S INTERFACE DPLL HDLC MT8941 MT8930B DTMF RECEIVER MT8870 DIGITAL PHONE HDLC MT8992/93 PC INTERFACE Figure 11 - S-Access Card Functional Block Diagram 15 Zarlink Semiconductor Inc. MT89L85 Data Sheet Absolute Maximum Ratings* Parameter Symbol Min. Max. Units VDD -0.3 5.0 V VSS-0.3 VDD+0.3 V 20 mA +125 °C 1 W 1 Supply Voltage 2 Voltage on Digital Inputs VI 3 Current at Digital Outputs IO 4 Storage Temperature TS 5 Package Power Dissipation PD -55 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. Typ.‡ Max. Units 1 Operating Temperature TOP -40 25 +85 °C 2 Positive Supply VDD 3.0 3.3 3.6 V 3 Input High Voltage VIH 0.7VDD VDD V 4 Input High Voltage on 5 V Tolerant Inputs VIH 5.5 V 5 Input Low Voltage VIL 0.3VDD V VSS Test Conditions ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 I N P U T S O U T P U T S Sym. Min. Typ.‡ Max. Units 4 7 mA Supply Current IDD Input High Voltage VIH Input Low Voltage VIL 0.3VDD V Input Leakage IIL 5 µA Input Pin Capacitance CI 10 pF Output High Voltage VOH 0.8VDD V Output High Current IOH 10 mA Output Low Voltage VOL Output Low Current IOL High Impedance Leakage IOZ Output Pin Capacitance CO 0.7VDD 5 V VI between VSS and VDD IOH = 10 mA Sourcing. VOH=0.8VDD IOL = 5 mA mA Sinking. VOL = 0.4 V 5 µA VO between VSS and VDD 10 pF ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Zarlink Semiconductor Inc. Outputs unloaded V 0.4 16 Test Conditions MT89L85 Data Sheet AC Electrical Characteristics _Timing Parameter Measurement Voltage Levels Characteristics Sym. Level Units 1 CMOS Threshold Voltage VTT 0.5VDD V 2 CMOS Rise/Fall Threshold Voltage high VHM 0.7VDD V 3 CMOS Rise/Fall Threshold Voltage low VLM 0.3VDD V Typ.‡ Max. Units Test Conditions AC Electrical Characteristics† - ST-BUS Timing Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. 1 Frame Pulse width tF0iW 2 Frame Pulse setup time tF0iS 10 190 ns 3 Frame Pulse hold time tF0iH 20 190 ns 4 STo delay Active to Active tSAA 55 ns 5 STi setup time tSTiS 20 ns 6 STi hold time tSTiH 20 ns 7 Clock period tC4i 200 244 300 ns 8 CK Input Low tCL 85 122 150 ns 9 CK Input High tCH 85 122 150 ns 10 Clock Rise/Fall Time tr,tf 10 ns 244 ns † Timing is over recommended temperature & power supply voltages (VDD=5V±5%, VSS=0V, TA=–40 to 85°C). ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 17 Zarlink Semiconductor Inc. Test Conditions CL=150 pF MT89L85 Data Sheet tF0iW F0i VHM VLM tC4i tF0iH C4i tCH tCL VHM VLM tf tF0iS tr tDAA V STo HM Ch. 31 Bit 0 VLM Ch. 0 Bit 7 Ch. 0 Bit 6 tSTiS STi VHM Ch. 31 Bit 0 VLM Ch. 0 Bit 5 tSTiH Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5 Figure 12 - ST-BUS Timing AC Electrical Characteristics† - GCI Timing Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. Typ.‡ Max. Units 1 Clock Period tC4i 150 244 300 ns 2 Pulse Width tCL, tCH 73 122 150 ns 3 Frame Width High tWFH 4 Frame Setup tF0iS 10 190 ns 5 Frame Hold tF0iH 20 190 ns 6 Data Delay/Clock Active to Active tDAA 55 ns 7 Serial Input Setup tSTiS 20 ns 8 Serial Input Hold tSTiH 20 ns 9 Clock Rise/Fall Time tr,tf 244 ns 10 † Timing is over recommended temperature & power supply voltages (VDD=3.3V±5%, VSS=0V, TA=–40 to 85°C). ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 18 Zarlink Semiconductor Inc. Test Conditions ns CL=150 pF MT89L85 Data Sheet C4i F0i STi/ STo bit 0 bit 1 bit 2 bit 3 Note: bit 0 identifies the first bit of the GCI frame See Detail a tr C4i tCH tCL tf tC4i VHM VLM tWFH F0i VHM VLM STo tF0iS tF0iH VHM VLM tSTiS tDAA STi tSTiH VHM VLM Detail a Figure 13 - GCI Timing AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes Characteristics 1 2 3 4 O U T P U T S Sym. Min. Typ.‡ Max. Units Test Conditions STo0/7 Delay - Active to High Z tSAZ 55 ns RL=1 KΩ*, CL=150 pF STo0/7 Delay - High Z to Active tSZA 55 ns CL=150 pF Output Driver Enable Delay tOED 50 ns RL=1 KΩ*, CL=150 pF CSTo Output Delay tXCD 55 ns CL=150 pF † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 19 Zarlink Semiconductor Inc. MT89L85 Data Sheet Bit Cell Boundary (GCI) C4i VHM VLM STo0 to STo7 (ST-BUS) VHM * VLM tSAZ STo0 VHM to STo7 VLM * tSZA CSTo VHM VLM tXCD Figure 14 - Serial Outputs and External Control ODE VHM VLM STo0 to STo7 VHM * * VLM tOED tOED Figure 15 - Output Driver Enable 20 Zarlink Semiconductor Inc. MT89L85 Data Sheet AC Electrical Characteristics†- Microprocessor Bus Voltages are with respect to ground (VSS) unless otherwise stated . Characteristics Sym. Min. Typ.‡ Max. Units Test Conditions 1 CS Setup from DS rising tCSS 0 ns 2 R/W Setup from DS rising tRWS 5 ns 3 Add setup from DS rising tADS 5 ns 4 CS hold after DS falling tCSH 0 ns 5 R/W hold after DS falling tRWH 5 ns 6 Add hold after DS falling tADH 8 ns 7 Data setup from DTA Low on Read 0 ns CL=150 pF 8 Data hold on read tDDR tDHR 10 ns RL=1 KΩ*, CL=150 pF 9 Data setup on write (fast write) tDSW 0 10 Valid Data Delay on write (slow write) tSWD 11 Data hold on write tDHW 12 Acknowledgment Delay: Reading Data Memory Reading/Writing Conn. Memory Writing to Control Register Reading Control Register tAKD 13 Acknowledgment Hold Time tAKH 90 25 ns 122 5 10 ns ns 560 62/30 25 52 1220 120/53 65 120 ns ns ns ns 50 80 ns CL=150 pF RL=1 KΩ*, CL=150 pF † Timing is over recommended temperature & power supply voltages . ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 21 Zarlink Semiconductor Inc. MT89L85 Data Sheet VHM DS tCSS VLM tCSH VHM CS VLM tRWH tRWS VHM R/W VLM tADS tADH VHM A0-A6 VLM D0-D7 READ VHM VALID DATA VLM tDSW tSWD D0-D7 WRITE tDHR VHM VALID DATA tDDR tAKD VLM tDHW tAKH VHM DTA VLM Figure 16 - Motorola Non-Multiplexed Bus Timing 22 Zarlink Semiconductor Inc. Package Code c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. 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