VP5311C/VP5511C

Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
VP5311C/VP5511C
NTSC/PAL Digital Video Encoder
Supersedes May 1997 edition DS4575 - 1.0
The VP5311C/VP5511C converts digital Y, Cr, Cb,
data into analog NTSC/PAL composite video and S-video
signals. The outputs are capable of driving doubly
terminated 75 ohm loads with standard video levels.
The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Cb, Y, Cr, Y
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311C/
VP5511C is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.
All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.
The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.
Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.
FEATURES
■ Converts Y, Cr, Cb data to analog composite video and
S-video
■ Supports CCIR recommendations 601 and 656
■ All digital video encoding
■ Selectable master/slave mode for sync signals
■ Switchable chrominance and luma bandwidth
■ Switchable pedestal with gain compensation
■ SMPTE 170M NTSC or CCIR 624 PAL compatible
outputs
■ GENLOCK mode
■ Line 21 Closed Caption encoding
■ I2C bus serial microprocessor interface
■ VP5311C supports Macrovision V7.01anti-taping format
APPLICATIONS
■
■
■
■
■
■
Digital Cable TV
Digital Satellite TV
Multi-media
Video games
Karaoke
Digital VCRs
ORDERING INFORMATION
VP5311C/CG/GP1N
VP5511C/CG/GP1N
DS4773 - 2.3 March 1998
PIN 1 IDENT
PIN 52
PIN 1
GP52
Fig.1 Pin connections (top view)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
FUNCTION
D0 (VS I/O)
D1 (HS I/O)
D2 (FC0 O/P)
D3 (FC1 O/P)
D4 (FC2 O/P)
D5
D6 (SCSYNC I/P)
D7 (PALID I/P)
GND
VDD
GND
PXCK
VDD
CLAMP
COMPSYNC
TDO
TDI
TMS
TCK
GND
SA1
SA2
SCL
VDD
SDA
VDD
PIN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
FUNCTION
RESET
REFSQ
GND
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
VDD
AGND
VREF
DACGAIN
COMP
AVDD
LUMAOUT
AGND
COMPOUT
AGND
CHROMAOUT
AVDD
AVDD
AVDD
VP5311C/VP5511C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS
Parameter
Conditions
Digital Inputs TTL compatible (except SDA, SCL)
Input high voltage
Input low voltage
Digital Inputs SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Digital Outputs CMOS compatible
Output high voltage
Output low voltage
Digital Output SDA
Output low voltage
Symbol
Min.
VIH
VIL
2.0
VIH
0.7 VDD
Typ.
Max.
Units
0.8
V
V
V
VIN = VDD
VIL
IIH
0.3 VDD
10
V
µA
VIN = VSS
IIL
-10
µA
IOH = -1mA
IOL = +4mA
VOH
VOL
0.4
V
V
IOL = +6mA
VOL
0.6
V
Max.
Units
±1.5
±1
±5
LSB
LSB
%
3.7
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS DACs
Parameter
Symbol
Accuracy (each DAC)
Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity
LSB size
Internal reference voltage
Internal reference voltage output impedance
Reference Current (VREF/RREF) RREF = 769Ω
DAC Gain Factor (VOUT = KDAC x IREF x RL), VOUT = DAC code 511
Peak Glitch Energy (see fig.3)
Min.
Typ.
INL
DNL
guaranteed
µA
V
Ω
mA
66.83
1.050
27k
1.3699
24.93
50
pV-s
CVBS, Y and C - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
33.75
17.64
1.40
7.62
7.62
0.40
mA
mA
mA
mA
mA
mA
CVBS, Y and C - PAL
Maximum output
White level relative to black level
White level relative to sync level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
34.15
18.71
26.73
8.02
8.02
0.00
mA
mA
mA
mA
mA
mA
VREF
ZR
IREF
KDAC
Note: All figures are for: RREF = 769Ω RL = 37.5Ω. When the device is set up in NTSC mode there is a +0.25% error in the PAL
levels. If RL = 75Ω then RREF = 1538Ω.
ABSOLUTE MAXIMUM RATINGS
Supply voltage
VDD, AVDD
Voltage on any non power pin
Ambient operating temperature
Storage temperature
2
-0·3 to 7·0V
-0·3 to VDD+0·3V
0 to 70°C
-55°C to 150°C
Note: Stresses exceeding these listed under Absolute
Maximum Ratings may induce failure. Exposure to Absolute
Maximum Ratings for extended periods may reduce
reliability. Functionality at or above these conditions is not
implied.
VP5311C/VP5511C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power supply voltage
Power supply current (including analog outputs)
Input clock frequency
SCL clock frequency
Analog video output load
DAC gain resistor
Ambient operating temperature
Min.
VDD, AVDD
4.75
IDD
PXCK
-50ppm
fSCL
0
Typ.
Units
Max.
5.25
5.00
150
27.00 +50ppm
500
37.5
769
70
V
mA
MHz
kHz
Ω
Ω
°C
VIDEO CHARACTERISTICS
Parameter
Symbol
Luminance bandwidth (high)
Luminance bandwidth (medium)
Luminance bandwidth (low)
Chrominance bandwidth (Extended B/W mode)
Chrominance bandwidth (Reduced B/W mode)
Burst frequency (NTSC)
Burst frequency (PAL-B, D,G,H,I)
Burst frequency (PAL-M)
Burst frequency (PAL-N Argentina)
Burst cycles (NTSC and PAL-M,N)
Burst cycles (PAL-B, D, G, H,I)
Burst envelope rise / fall time (all standards)
Analog video sync rise / fall time (NTSC and PAL-M,N)
Analog video sync rise / fall time (PAL-B, D, G, H,I)
Differential gain
Differential phase
Signal to noise ratio (unmodulated ramp)
Chroma AM signal to noise ratio (100% red field)
Chroma PM signal to noise ratio (100% red field)
Hue accuracy
Colour saturation accuracy
Residual sub carrier
Luminance / chrominance delay
Typ.
Min.
Max.
6.16
4.34
2.79
1.3
650
3.57954545
4.43361875
3.57561189
3.58205625
9
10
300
145
245
1.0
0.5
-61
-56
-58
2.5
2.5
-5
-60
0
+5
Units
MHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
Fsc cycles
Fsc cycles
ns
ns
ns
% pk-pk
° pk-pk
dB
dB
dB
%
%
dB
ns
ESD COMPLIANCE
Pins
Test
Test Levels
All pins
Human body model
2kV on 100pF through 1k5Ω
All pins
Machine model
200V on 200pF through 0Ω & 500nH
Notes
Meets Mil-Std-883 Class 2
3
VP5311C/VP5511C
SDA
SCL
SA1
SA2
SET-UP
REGISTERS
I2C INTERFACE
ANTI-TAPING
CONTROL
CLOSED
CAPTION
CLAMP
RESET
VIDEO TIMING GENERATOR
+
SYNC
BLANK
INSERT
Y
+
INTERPOLATOR
INPUT
DEMUX
&
8
PD7-0 CHROMA
INTERP
COMPSYNC
LUMA OUT
LUMA
DAC
+
COMP
DAC
CHROMA
LOW -PASS
FILTER
Cb
D7-0
OUT
Cr
INTERPOLATOR
CHROMA
DAC
MODULATOR
CHROMA OUT
PXCK
8
COMP
GENERAL
PURPOSE PORT
DIGITAL
PHASE COMP
COLOUR SUBCARRIER
GENERATOR
DACREF
VREF
TDI
REFSQ
DAC
REF
JTAG.
TDO
COMP
TMS TCK
Fig.2 Functional block diagram of the VP5311C, the VP5511C is identical except there is no Anti-Taping Control
V
W
H
Peak Glitch Area = H x W/2
t(ps)
The glitch energy is calculated by measuring the area under the voltage
time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)
Fig.3 Glitch Energy
4
VP5311C/VP5511C
PIN DESCRIPTIONS
Pin Name
Pin No.
Description
PD7-0
30 - 37
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
37. These pins are internally pulled low.
D0-7
1-8
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 1.
These pins are internally pulled low.
PXCK
12
27MHz Pixel Clock input. The VP5311C/5511C internally divides PXCK by two to provide the
pixel clock.
CLAMP
14
COMPSYNC
15
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC and PAL-M; lines 6-310 and 319-623
for PAL-B,D, G,I,N(Argentina)).
Composite sync pulse output. This is an active low output signal.
TDO
16
JTAG Data output port.
TDI
17
JTAG Data input port.
TMS
18
JTAG mode select input.
TCK
19
JTAG clock input.
SA1
21
I2C slave address select
SA2
22
I2C slave address select.
SCL
23
Standard I2C bus serial clock input.
SDA
25
Standard I2C bus serial data input/output.
RESET
27
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5311C/5511C.
REFSQ
28
Reference square wave input used only during Genlock mode.
VREF
41
Voltage reference input/output. This pin is nominally 1.055V and should be decoupled with a
100nF capacitor to GND.
DAC GAIN
42
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.
COMP
43
DAC compensation. A 100nF ceramic capacitor must be connected between pin 43 and pin
44.
LUMAOUT
45
True luminance, composite and chrominance video signal outputs. These are high
COMPOUT
47
impedance current source outputs. A DC path to GND must exist from each of these pins.
CHROMAOUT
49
VDD
10, 13, 24, Positive supply input. All VDD pins must be connected.
26, 39
AVDD
44, 50,
Analog positive supply input. All AVDD pins must be connected.
51, 52
GND
9, 11, 20,
AGND
40, 46, 48
Negative supply input. All GND pins must be connected.
29, 38
Negative supply input. All AGND pins must be connected.
5
VP5311C/VP5511C
REGISTERS MAP
See Register Details for further explanations.
ADDRESS REGISTER
NAME
hex
DEFAULT
hex
7
6
5
4
3
2
1
0
R/W
BAR
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
W
00
01
02
03
PART ID2
PART ID1
PART ID0
REV ID
ID17
ID0F
ID07
REV7
ID16
ID0E
ID06
REV6
ID15
ID0D
ID05
REV5
ID14
ID0C
ID04
REV4
ID13
ID0B
ID03
REV3
ID12
ID0A
ID02
REV2
ID11
ID09
ID01
REV1
ID10
ID08
ID00
REV0
R
R
R
R
13
66
58
06
04
05
06
07
08
09
0A
0B
0C
0D
GCR
VOCR
HANC
ANCID
SC_ADJ
FREQ2
FREQ1
FREQ0
SCHPHM
SCHPHL
LBW1
AN7
SC7
FR17
FR0F
FR07
SCH7
YCDELAY RAMPEN
CLAMPDIS CHRBW SYNCDIS
DF1
DF2
LBW0
AN5
AN4
AN6
SC5
SC4
SC6
FR15
FR14
FR16
FR0D
FR0C
FR0E
FR05
FR04
FR06
SCH5
SCH4
SCH6
SLH&V
BURDIS
DF0
AN3
SC3
FR13
FR0B
FR03
SCH3
CVBSCLP
LUMDIS
Reserved
AN2
SC2
FR12
FR0A
FR02
SCH2
VFS1
CHRDIS
Reserved
AN1
SC1
FR11
FR09
FR01
SCH1
VFS0
PEDEN
ACTREN
PARITY
SC0
FR10
FR08
FR00
SCH8
SCH0
R/W
R/W
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
00
00
00
9C
87
C1
F1
00
00
0E to 1F
Reserved
20
21
22
23-33
34 to EF
F0
F1
F2
F3
F4
F5 to F7
F8
F9
FA
FB
FC
FD
FE
FF
GPPCTL
GPPRD
GPPWR
Reserved
Not used
CCREG1
CCREG2
CCREG3
CCREG4
CC_CTL
Reserved
HSOFFL
HSOFFM
Reserved
SLAVE1
SLAVE2
TEST1
TEST2
GPSCTL
CTL7
RD7
WR7
CTL6
RD6
WR6
CTL5
RD5
WR5
CTL4
RD4
WR4
CTL3
RD3
WR3
CTL2
RD2
WR2
CTL1
RD1
WR1
CTL0
RD0
WR0
W
R
W
FF
00
-
F1W1D6
F1W2D6
F2W1D6
F2W2D6
-
F1W1D5
F1W2D5
F2W1D5
F2W2D5
-
F1W1D4
F1W2D4
F2W1D4
F2W2D4
-
F1W1D3
F1W2D3
F2W1D3
F2W2D3
F2ST
F1W1D2
F1W2D2
F2W1D2
F2W2D2
F1ST
F1W1D1
F1W2D1
F2W1D1
F2W2D1
F2EN
F1W1D0
F1W2D0
F2W1D0
F2W2D0
F1EN
R/W
R/W
R/W
R/W
R/W
----0C
HSOFF7
-
HSOFF6
-
HSOFF5
-
HSOFF4
-
HSOFF3
-
HSOFF2
-
HSOFF1
HSOFF9
HS0FF0
HSOFF8
R/W
R/W
7E
00
NCORSTD
HCNT7
VBITDIS
HCNT6
SL_HS1
F_SWAP
HCNT3
HCNT4
RESERVED
FOR
RESERVED
FOR
NOLOCK PALIDEN
SL_HS0
HCNT2
TEST
TEST
TSURST
HCNT9
HCNT1
HCNT8
HCNT0
00
00
CHRMCLIP
TRSEL
R/W
R/W
R/W
R/W
R/W
VSMODE
HCNT5
REGISTER
REGISTER
FSC4SEL GENDITH GENLKEN
00
Table.1 Register map
NOTE * For register HANC, bits 3, 4 and 5 are read only. Bits 1 and 2 are reserved. N/A = not applicable.
For register PART ID0 the VP5511C value is AB
Standard
NTSC (default)
PAL-B, G, H, I
PAL-M
PAL-N (Argentina)
xx = don’t care.
Lines/ Field
field freq. Hz
59.94
525
625
525
625
50
59.94
50
SC_ADJ
Number of Horizontal Subcarrier
fSC/fH
register
pixels/line freq. kHz.
freq. kHz.
hex
at 27MHz
fH
fSC
15.734266 3.57954545
1716
xx
(455/2)
15.625000 4.43361875 (1135/4+1/625)
1728
9C
15.734266 3.57561189
1716
xx
(909/4)
15.625000 3.58205625 (917/4+1/625)
1728
57
FREQ2-0
registers hex
87 C1 F1
A8 26 2B
87 9B C0
87 DA 51
Table.2 Line, field and subcarrier standards and register settings
The calculation of the FREQ register value is according to the following formula:FREQ = 226 x fSC/PXCK hex, where PXCK = 27.00MHz
Both NTSC and PAL-M values are rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN.
The SC_ADJ value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier
frequency. Note the SC_ADJ value of 9C required for PAL-B, D, G, H, I, is different to the default state of the register.
In NTSC the NCO is reset at the end of every line, this can be disabled by setting the NCORSTD bit in SLAVE1, this allows the
VP5311C to cope with line lengths that are not exactly as specified in REC656.
6
VP5311C/VP5511C
REGISTER DETAILS
BAR
RA7-0
Base register
Register address.
PART ID 2-0
ID17-00
Part number
Chip part identification (ID) number.
REV ID
REV7-0
Revision number
Chip revision ID number.
GCR
YCDELAY
Global Control
Luma to Chroma delay.
High = 37ns luma delay, this may be
used to compensate for group delay in
external filters.
Low = normal operation (default).
RAMPEN
SLH&V
CVBSCLMP
VFS1-0
Modulated ramp enable.
High = ramp output for differential phase
and gain measurements. A 27MHz clock
must be applied to PXCK pin.
Low = normal operation (default).
1 = Slave to HS and VS inputs
1 = Enables clamp on composite output,
to prevent flatenning of chroma peaks
and troughs.
VOCR
CLAMPDIS
Video Output Control
High = Clamp signal disable
Low = normal operation with clamp signal
enabled (default).
CHRBW
Chroma bandwidth select.
High = ±1·3MHz.
Low = ±650kHz (default)
SYNCDIS
High = Sync disable (in composite video
signal). COMPSYNC is not affected.
Low = normal operation with sync
enabled (default).
LUMDIS
CHRDIS
High = Pedestal (set-up) enable a
7·5 IRE pedestal on lines 23-262 and
286-525. Valid for NTSC/PAL-M only
HANC
LBW1-0
Horizontal Ancillary Data Control
Luma filter control
LBW1 LBW0
0
0
0
1
1
X
-3dB Bandwidth
6.16MHz
4.34MHz
2.79MHz
DF2-0(read only) Digital Field Identification, 000=Field1
ANCTREN
Ancillary timing reference enable. When
High use FIELD COUNT from ancillary
data stream. When low, data is ignored.
ANCID
AN7-1
Parity
Ancillary data ID
Ancillary data ID
Parity bit (odd)
Only ancillary data in REC 656 data
stream with the same ID as this byte will
be decoded by the VP5311C/VP5511C to
produce H and V synchronisation and
FIELD COUNT.
SC_ADJ
SC7-0
Sub Carrier Adjust
Sub carrier frequency seed value, see
table 2.
FREQ2-0
FR17-00
Sub carrier frequency
24 bit Sub carrier frequency programmed
via I2C bus, see table 2. FREQ2 is the
most significant byte (MSB).
SCHPHM-L
SCH8-0
Sub carrier phase offset
9 bit Sub carrier phase relative to the
50% point of the leading edge of the
horizontal part of composite sync.
SCHPHM bit 0 is the MSB. The nominal
value is zero. This register is used to
compensate for delays external to the
VP5311C/VP5511C.
GPPCTL
CTL7-0
General purpose port control
Each bit controls port direction
Low = output
High = input
GPPRD
RD7-0
General purpose port read data
I2C bus read from general purpose port
(only INPUTS defined in GPPCTL)
GPPWR
WR7-0
General purpose port write data
I2C bus write to general purpose port
(only OUTPUTS defined in GPPCTL)
CCREG1
F1W1D6-0
Closed Caption register 1
Field one (line 21), first data byte
CCREG2
F1W2D6-0
Closed Caption register 2
Field one (line 21), second data byte
CCREG3
F2W1D6-0
Closed Caption register 3
Field two (line 284), first data byte
Video format select
VFS1 VFS0
0
0
NTSC (default)
PAL-B,D,G,H,I,N(Argentina)
0
1
1
0
PAL-M
1
1
Reserved
BURDIS
PEDEN
High = Chroma burst disable.
Low = normal operation, with burst
enabled (default).
High = Luma input disable - force black
level with synchronisation pulses maintained.
Low = normal operation, with Luma input
enabled (default).
High = Chroma input disable - force
monochrome.
Low = normal operation, with Chroma
input enabled (default).
7
VP5311C/VP5511C
CCREG4
F2W2D6-0
Closed Caption register 4
Field two (line 284), second data byte
CC_CTL
F1ST
Closed Caption control register
Field one (line 21) status
High = data has been encoded
Low = new data has been loaded to
CCREG1-2
F2ST
Field two (line 284) status
High = data has been encoded
Low = new data has been loaded to
CCREG3-4
F1EN
Closed Caption field one (line 21)
High = enable
Low = disable (default)
F2EN
Closed Caption field two (line 284)
High = enable
Low = disable (default)
HSOFFM-L
HSOFF9-0
Low = normal operation, internal PAL ID
phase switch is used (default).
TSURST
High = chip soft reset. Registers are NOT
reset to default values.
Low = normal operation (default).
CHRMCLIP
High = enable clipping of chroma data
when luma goes below black level and is
clipped.
Low = no chroma clipping (default).
TRSEL
High = master mode, GPP bits D0 - 4 are
forced to become a video timing port with
VS, HS and FIELD outputs.
Low = slave mode, timing from REC656.
or H & V slave if SLH&V bit set
I2C BUS CONTROL INTERFACE
HS offset
This is a 10 bit number which allows the
user to offset the start of digital data input
with reference to the pulse HS.
I2C bus address
SLAVE1
NCORSTD
H &V Slave mode control register
1 = NCO Line Reset Disable (NTSC only)
VBITDIS
0 = Video blanked when Rec656 V bit set
1 = V bit is ignored
0 = Standard Vsync I/P
1 = Even/Odd Field I/P
The odd and even fields are swapped
Selects pixel sample (0 to 3)
As HCNT7-0 but MSBs
H &V Slave position register
Adjusts for delay at which pixel data
occurs relative to HS
The serial microprocessor interface is via the bidirectional port consisting of a data (SDA) and a clock (SCL)
line. It is compatible to the Philips I2C bus standard (Jan. 1992
publication number 9398 393 40011). The interface is a slave
transmitter - receiver with a sub-address capability. All
communication is controlled by the microprocessor. The SCL
line is input only. The most significant bit (MSB) is sent first.
Data must be stable during SCL high periods.
A bus free state is indicated by both SDA and SCL lines
being high. START of transmission is indicated by SDA being
pulled low while SCL is high. The end of transmission,
referred to as a STOP, is indicated by SDA going from low to
high while SCL is high. The STOP state can be omitted if a
repeated START is sent after the acknowledge bit. The
reading device acknowledges each byte by pulling the SDA
line low on the ninth clock pulse, after which the SDA line is
released to allow the transmitting device access to the bus.
The device address can be partially programmed by the
setting of the pins SA1 and SA2. This allows the device to
respond to one of four addresses, providing for system
flexibility. The I2C bus address is seven bits long with the last
bit indicating read / write for subsequent bytes.
The first data byte sent after the device address, is the
sub-address - BAR (base address register). The next byte will
be written to the register addressed by BAR and subsequent
bytes to the succeeding registers. The BAR maintains its data
after a STOP signal.
VSMODE
F_SWAP
SL_HS1-0
HCNT9-8
SLAVE2
HCNT7-0
GPSCTL
FSC4SEL
GPS Control
When high, REFSQ = 4xFSC and GPP
bit D6 is forced to become an input for a
SCSYNC signal (high = reset), which
provides a synchronous phase reset for
FSC divider. Low = normal operation with
REFSQ = 1xFSC. (default).
GENDITH
1 = Gen lock dither added.
GENLKEN
High = enable Genlock to REFSQ signal
input.
Low = internal subcarrier generation
(default).
NOLOCK
Genlock status bit (read only)
Low = Genlocked.
High = cannot lock to REFSQ. This bit is
cleared by reading and set again if lock
cannot be attained.
PALIDEN
High = enable external PAL ID phase
control and GPP bit D7 is forced to
become an input for PAL ID switch signal,
(GPP bit D7 - Low = +135°,High = -135°).
8
A6
A5
A4
A3
A2
A1
A0
0
0
0
1
1
SA2
SA1
R/ W
X
NTSC/PAL Video Standards
Both NTSC (4-field, 525 lines) and PAL (8-field, 625 lines)
video standards are supported by the VP5311C/VP5511C.
All raster synchronisation, colour sub-carrier and burst
characteristics are adapted to the standard selected. The
VP5311C/VP5511C generates outputs which follow the
requirements of SMPTE 170M and CCIR 624 for PAL signals.
The device supports the following:
NTSC,
PAL B, D, G, H, I, N (Argentina) and M.
VP5311C/VP5511C
Video Blanking
The VP5311C/VP5511C automatically performs standard
composite video blanking. Lines 1-9, 264-272 inclusive, as
well as the last half of line 263 are blanked in NTSC mode. In
PAL mode, lines 1-5, 311-318, 624-625 inclusive, as well as
the last half of line 623 are blanked.
The V bit within REC656 defines the video blanking when
TRSEL (bit 0 of GPSCTL register) is set low. When in
MASTER mode with TRSEL set high the video encoder is still
enabled. Therefore if these lines are required to be blank they
must have no video signal input.
Interpolator
The luminance and chrominance data are separately
passed through interpolating filters to produce output
sampling rates double that of the incoming pixel rate. This
reduces the sinx/x distortion that is inherent in the digital to
analog converters and also simplifies the analog
reconstruction filter requirements.
Digital to Analog Converters
The VP5311C/VP5511C contains three 9 bit digital to
analog converters which produce the analog video signals.
The DACs use a current steering architecture in which bit
currents are routed to one of two outputs; thus the DAC has
true and complementary outputs. The complementary output
is connected to GND internally. The use of identical current
sources and current steering their outputs means that
monotonicity is guaranteed. An on-chip voltage reference of
1.050V provides the necessary biasing. However, the
VP5311C/VP5511C may be used in applications where an
external 1V reference is provided on the VREF pin, to adjust
the video levels. In this case, the external reference should be
temperature compensated and provide a low impedance
output.
The full-scale output currents of the DACs is set by an
external 769Ω resistor between the DACGAIN and a GND
pins. An on-chip loop amplifier stabilises the full-scale output
current against temperature and power supply variations.
The analog outputs of the VP5311C/VP5511C are
capable of directly driving singly terminated 75Ω loads. For
this application the DACGAIN resistor is simply doubled.
Luminance, Chrominance and Composite Video Outputs
The Luminance video output (LUMAOUT pin 45) drives a
37.5Ω load at 1.0V, sync tip to peak white. It contains only the
luminance content of the image plus the composite sync
pulses. In the NTSC mode, a set-up level offset can be added
during the active video portion of the raster.
The Chrominance video output (CHROMAOUT pin 49)
drives a 37.5Ω load at levels proportional in amplitude to the
luma output (40 IRE pk-pk burst). This output has a fixed offset
current which will produce approximately a 0.5V DC bias
across the 37.5Ω load. Burst is injected with the appropriate
timing relative to the luma signal.
The composite video output (COMPOUT pin 47) will also
drive a 37.5Ω load at 1.0V, sync tip to peak white. It contains
both the luminance and chrominance content of the signal
plus the composite sync pulses.
The CVBS DAC output clipping feature limits the digital
data going into the DAC so that if it goes outside the range it
is limited to the maximum or minimum (511 or 000). This
feature is permanently enabled.
When CVBSCLP in register GCR is set to a '1' an envelope
prediction circuit is enabled that establishes if the chroma and
luma added together is likely to go outside the CVBS DAC
limits. If it is, then a smooth rounding of the chroma peaks is
made to stop this happening. This prevents any high
frequency components being produced as with the default
clipping function which will produce flat peaks. In practice
there will be some loss of saturation in the colour.
Output sinx/x compensation filters are required on all
video output, as shown in the typical application diagram, see
figs. 8 & 9.
Video Timing - Slave sync mode
The VP5311C/VP5511C has an internal timing generator
which produces video timing signals appropriate to the mode
of operation. In the default (following reset) slave mode, all
timing signals are derived from the input clock, PXCK, which
must be derived from a crystal controlled oscillator. Input pixel
data is latched on the rising edge of the PXCK clock.
The video timing generator produces the internal blanking
and burst gate pulses, together with the composite sync
output signal, using timing data (TRS codes) from the
Ancillary data in the REC656 input signal.
H & V Slave Mode
HCNT
To ensure that the incoming data is sampled correctly a 10
bit binary number (HCNT) has to be programmed into the
SLAVE1 and 2 registers. This will allow the device's internal
horizontal counter to align with the video data, each bit
represents one 13.5MHz cycle. To calculate this use the
formula below:
NTSC/PALM
HCNT = SN + 119 (SN = 0 - 738)
HCNT = SN - 739 (SN = 739 - 857)
PAL
HCNT = SN + 127 (SN = 0 - 736)
HCNT = SN - 737 (SN = 737 - 863)
where SN is Rec. 656/601 sample number on which the
negative edge of HSYNC occurs.
SL_HS
A further adjustment is also required to ensure that the
falling edge of HSYNC occurs on a Y sample that precedes a
Cr sample. The bits SL_HS1-0 introduce a delay of 0-3
27MHz samples in the CbYCrY sequence, failure to set this
correctly will mean corruption of the colour or colour being
interpreted as luma.
F_SWAP
If the field synchronisation is wrong it can be swapped by
setting this bit.
V_SYNC
When set to a '1' this bit allows an odd/even square wave
to provide the field synchronisation.
Example
NTSC
HSYNC occurs on Rec656 sample 721 (end of active
video), then;
HCNT = 721 + 119 = 839 = 348 Hex
SL_HS = 10 (for correct sample)
9
VP5311C/VP5511C
To set slave H & V the SLH&V bit should be set to '1' (reg 04).
Video Timing - Master sync mode
When TRSEL (bit 0 of GPSCTL register) is set high, the
VP5311C/5511C operates in a MASTER sync mode, all
REC656 timing reference codes are ignored and GPP bits D0
- 4 become a video timing port with VS, HS and FIELD
outputs. The PXCK signal is, however, still used to generate
all internal clocks. When TRSEL is set high, the direction
setting of bits 4 - 0 of the GPPCTL register is ignored.
VS is the start of the field sync datum in the middle of the
equalisation pulses. HS is the line sync which is used by the
preceding MPEG2 decoder to define when to output digital
video data to the VP5311C/5511C.
HS offset
The position of the falling edge of HS relative to the first
data Cb0, can be programmed in HSOFFM-L registers, see
figure 4, this is called the pipeline delay and may need
adjusting for a particular application. This is done by
programming a 10 bit number called HSOFF into the
HSOFFM and HSOFFL registers, HSOFFM being the most
significant two bits and HSOFFL the least significant eight bits.
A default value of 07EH is held in the registers.
The value to program into HSOFF can be looked up in
tables 3 &4:
where NCK = number of 13.5MHz clock cycles between the
falling edge of HS and Cb0 (first data I/P on PD7-0) see fig. 4.
NCK
HSOFF
Comment
0 to 120
126 to 6
HS normal (64 cks)
121 to 183
863 to 801
HS pulse shortened*
184 to 857
800 to 127
HS normal (64 cks)
Table.3 for NTSC and PAL-M
NCK
HSOFF
Comment
0 to 131
137 to 6
HS normal (64 cks)
132 to 194
869 to 807
HS pulse shortened*
195 to 863
806 to 138
HS normal (64 cks)
Table.4 for PAL-B, D, G, H, I, N
Decreasing HSOFF advances the HS pulse (numbers are in
decimal).
*HS pulse shortened means that the width of the pulse will be
less than the normal 64 13.5MHz clock cycles.
The interruption in the sequence of values is because the HS
signal is jumping across a line boundary to the previous line as
the offset is increased. The register default value is 7EH and
this sets Nck to 0, ie. the HS negative edge and Cb0 are coincident in NTSC mode.
Genlock using REFSQ input
The VP5311C/5511C can be Genlocked to another video
source by setting GENLKEN high (in GPSCTL register) and
feeding a phase coherent sub carrier frequency signal into
REFSQ. Under normal circumstances, REFSQ will be the
same frequency as the sub carrier. But by setting FSC4SEL
10
high (in GPSCTL register), a 4 x sub carrier frequency signal
may be input to REFSQ. In this case, the Genlock circuit can
be reset to the required phase of REFSQ, by supplying a pulse
to SCSYNC (pin 7). The frequency of SCSYNC can be at sub
carrier frequency, but once per line, or once per field could be
adequate, depending on the application. When GENLKEN is
set high, the direction setting of bit 6 in the GPPCTL register
is igonred.
PALID Input
When in Genlock mode with GENLKEN set high (in
GPSCTL register), the VP5311/5511C requires a PAL phase
identification signal, to define the correct phase on every line.
This is supplied to PALID input (pin 8), High = -135° and low
= +135°. The signal is asynchronous and should be changed
before the sub carrier burst signal. PALID input is enabled by
setting PALIDEN high (in GPSCTL register). When
GENLKEN is high, the direction setting of bit 7 of the GPPCTL
register is ignored
Master Reset
The VP5311C/VP5511C must be initialised with the
RESET pin 27. This is an asynchronous active low signal and
must be active for a minimum of 200ns in order for the
VP5311C/VP5511C to be reset. The device resets to line 254
in NTSC and line 301 in PAL and start of horizontal sync (i.e.
line blanking active). There is no on-chip power on reset
circuitry.
Line 21 coding
Two bytes of data are coded on the line 21 of each field,
see figure 7. In the NTSC Closed Caption service, the default
state is to code on line 21 of field one only. An additional
service can also be provided using line 21 (284) of the second
field. The data is coded as NRZ with odd parity, after a clock
run-in and framing code. The clock run-in frequency =
0.5034965MHz which is related to the nominal line period, D
= H / 32.
D = 63.55555556 / 32µs
Two data bytes per field are loaded via I2C bus registers
CCREG1-4. Each field can be independently enabled by
programming the enable bits in the control register (CC_CTL).
The data is cleared to zero in the Closed Caption shift
registers after it has been encoded by the VP5311C/
VP5511C. Two status bits are provided (in CC_CTL), which
are cleared when data is written to the registers and set high
when the data has been encoded on the Luma signal. The
data is cleared to zero in the Closed Caption shift registers
after it has been encoded by the VP5311C/VP5511C. The
next data bytes must be written to the registers when the
status bit goes high, otherwise the Closed Caption data output
will contain Null characters. Null characters are invisible to a
Closed Caption reciever. The MSB (bit 7) is the parity bit and
is automatically added by the encoder.
VP5311C/VP5511C
PXCK Input (27MHz)
t SU; PD
HS
Nck=1
t HD; PD
Nck=0
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
Pixel Data Input (PD[7,0])
Fig.4 REC 656 interface with HS output timing
2:1 mux
REFSQ
fSC
0
Divide by 4
Synchronous
Counter
1
Q
Input to
Genlocking
Block
RESET
FSC4_SEL
SC_SYNC
(register bit)
t PWH; SC_SYNC
REFSQ
tSU; SC_SYNC
t HD; SC_SYNC
SC_SYNC
Q
Fig.5 REFSQ and SC_SYNC input timing
11
VP5311C/VP5511C
Pixel Data Input (PD[7,0])
Sample Number
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
Y719 $FF
$00
$00
$XY
ANCILLARY DATA...
EAV SEQUENCE
t SU; PD
t HD; PD
t PWL; PXCK
t PWH; PXCK
PXCK Input (27MHz)
t DUR; PALID
t SU; PALID
t HD; PALID
PALID Stable
Input (PALID)
Fig.6 PALID input timing
TIMING INFORMATION
Parameters
Conditions
Symbol
Min.
Typ.
Max.
27.0
fPXCK
Master clock frequency (PXCK input)
Units
MHz
PXCX pulse width, HIGH
tPWH; PXCK
10
ns
PXCX pulse width, LOW
tPWL; PXCK
14.5
ns
PXCX rise time
10% to 90% points
tRP
TBD
ns
PXCX fall time
90% to 10% points
tFP
TBD
ns
PD7-0 set up time
tSU;PD
10
ns
PD7-0 hold time
tHD;PD
5
ns
SCSYNC set up time
tSU;SCSYNC
10
ns
SCSYNC hold time
tHD;SCSYNC
0
ns
PALID set up time
tSU;PALID
10
ns
PALID hold time
tHD;PALID
0
ns
PALID duration
tDUR;PALID
9
PXCX
periods
Output delay
PXCK to COMPSYNC
PXCK to CLAMP
Note: Timing reference points are at the 50% level. Digital C LOAD <40pF.
12
tDOS
25
ns
VP5311C/VP5511C
H
C
B
A
1
D
START BITS
CLOCK RUN-IN
HSYNC COLOUR BURST
13
E
DATA BYTE 1
DATA BYTE 2
50
P
P
0
S1
-40
IRE
S2
S3 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
0 1 0 0 0 0 1 1
FRAME CODE
P = Parity Bit
Fig.7 Closed Capation format
Interval
Description
A
H-sync to clock run-in
B
Clock
run-in 2, 3
C
Clock run-in to third start bit 3
Encoder minimum
Encoder nominal
Encoder maximum
10.250µs
10.500µs
10.750µs
6.5D (12.910µs)
2.0D (3.972µs)
D
Data
bit 1, 3
1.0D (1.986µs)
E
Data characters 4
16.0D (31.778µs)
H
Horizontal line 1
Rise / fall time of data bit
32.0D (63.556µs)
transitions 5
0.240µs
0.288µs
Data bit high (logic level one) 6
Clock run-in maximum
48 IRE
50 IRE
52 IRE
Data bit low (logic level zero) 6
Clock run-in minimum
0 IRE
0 IRE
2 IRE
Data bit differential (high - low)
Clock run-in differential (max. - min)
48 IRE
50 IRE
52 IRE
Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992)
Notes
1. The Horizontal line frequency fH is nominally 15734.26Hz ±0.05Hz. Interval D shall be adjusted to D = 1/(fH x 32) for the
instantaneous fH at line 21.
2. The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing
0 IRE points. The sine wave is to be symmetrical about the 25 IRE level.
3. The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the
Start and Data bit transitions.
4. Two characters, each consisting of 7 data bits and 1 odd parity bit.
5. 2 T Bar, measured between the 10% and 90% amplitude points.
6. The clock run-in maximum level shall not differ from the data bit high level by more than ±1 IRE. The clock run-in minimum
level shall not differ from the data bit low level by more than ±1 IRE.
13
VP5311C/VP5511C
FERRITE
+5V
BEAD
Vdd
10nF
2k2Ω
I2C
BUS
VDD, AVDD
23
45
SCL
LUMA
25
SDA
21
COMP 43
SA1
22 SA2
30-37
8
28
REFSQ
12
PXCK
AT EVERY
VDD PIN
GND
100µF
2k2Ω
SCL
SDA
SA1
SA2
VIDEO IN
VDD
OUTPUT
FILTER
LUMA OUT
100nF
Vdd
PD0-7
49
CHROMA
REFSQ
DACGAIN 42 769Ω
OUTPUT
FILTER
CHROMA OUT
PXCK
GND
1-8
GPP
D0-7
VREF
8
RESET
CLAMP
COMP
SYNC
27
14
15
41
VREF
100nF
RESET
COMP 47
OUT
OUTPUT
FILTER
COMP OUT
CLAMP
COMP
SYNC
GND, AGND
GND
Fig.8 Typical application diagram, SLAVE mode. (Output filter - see Fig.9)
15pF
1.0µH
470pF
220pF
75Ω
EXT
75Ω
GND
Fig.9 Output reconstruction filter
14
VP5311C/VP5511C
Overlay of High, Medium and Low Resolution Luma FIR Filters
0
2.5e+6
0
2.5e+6
5.e+6
7.5e+6
10.e+6
12.5e+6
5.e+6
7.5e+6
10.e+6
12.5e+6
0
-20
M
a
g
n
i
t
u
d
e
-40
d
B
-60
-80
Frequency in Hz (Res = 26.37e+3 Hz)
Fig.10 Response of Switchable Luma Filter
Switchable Luma Filter
The internal luma interpolation filter can be set to three different frequency responses; low, medium and high, the latter being
the default setting. Fig.10 above shows the three responses and Table.6 below shows important performance parameters.
Filter Setting
-3dB point
MHz
Pass Band
MHz
Pass Band Ripple
dB
Stop Band
dB
Low
2.79
1.36
0.052
-40 @ 5.3MHz
Medium
4.34
2.17
0.058
-35 @ 7.2MHz
High
6.16
4.86
0.138
-36 @ 8.6MHz
Table. 6 Luma Filter Performance
Note:
The VP5311C is only available to customers with a valid and existing authorisation to purchase issued by MACROVISION
CORPORATION.
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of
the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial, home and limited exhibition uses
only. Reverse engineering or disassembly is prohibited.
15
VP5311C/VP5511C
PACKAGE DETAILS
Dimensions are shown thus: mm (in).
0° - 7°
0·13/0·23
(0·005/0·009)
2·45 (0·096)
MAX.
1·90/2·10
(0·075/0·083)
9·90/10·10
(0·390/0·398)
SQ.
7·80 (0·307) 13·64/14·15
NOM.
(0·537/0·557)
PIN 1 IDENT
0·65/1·03
(0·026/0·041)
PIN 52
PIN 1
0·22/0·38
(0·009/0·015)
52 LEADS AT
0·65 (0·026)
NOM. SPACING
NOTES
1. Controlling dimensions are millimetres.
2. This package outline diagram is for guidance
only. Please contact your Zarlink Semiconductor
Customer Service Centre for further information.
52-LEAD QUAD FLATPACK – GP52
16
0·15/0·30
(0·006/0·012)
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE