Si52143 PCI-E XPRESS G EN 1, G EN 2, & G EN 3 Q UAD O UTPUT C L O C K G ENERATOR WITH 2 5 M H Z R E F E R E N C E C L O C K Features PCI-Express Gen 1, Gen 2 & Gen 3 compliant Supports Serial ATA (SATA) at 100 MHz Low power, push-pull HCSL compatible differential outputs No termination resistors required Dedicated output enable hardware pins for each clock output Spread enable pin on differential clocks Four PCI-Express clocks 25 MHz reference clock output 25 MHz crystal input or clock input Signal integrity tuning I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Industrial temperature –40 to 85 oC 3.3 V power supply 24-pin QFN package Wireless access point Routers Ordering Information: See page 18 Applications SCLK 22 VDD_CORE 23 SDATA XOUT 24 21 20 19 VDD_REF 1 1 18 OE[3:2] REF 2 17 VDD_DIFF SSON2 3 VSS_REF 4 1 OE_REF 5 VDD_DIFF 6 16 DIFF3 25 GND 15 DIFF3 14 DIFF2 8 9 10 11 12 DIFF1 DIFF1 VDD_DIFF 13 DIFF2 7 DIFF0 The Si52143 is a spread-spectrum enabled PCIe clock generator that can source four PCIe clocks and a 25 MHz reference clock. The device has three hardware output enable pins for enabling the outputs (on the fly while powered on), and one hardware pin to control spread spectrum on PCIe clock outputs. In addition to the hardware control pins, I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, compliment, or both differential signals on the PCIe clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the PCIe clock outputs. Refer to AN636 for signal integrity tuning and configurability. XIN/CLKIN Description VSS_CORE Pin Assignments DIFF0 Network attached storage Multi-function printer OE[1:0]1 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Functional Block Diagram Patents pending REF XIN/CLKIN XOUT DIFF0 DIFF1 PLL (SSC) Divider DIFF2 DIFF3 SCLK SDATA Control & Memory OE_REF OE [1:0] Control RAM OE [3:2] SSON Rev 1.2 2/14 Copyright © 2014 by Silicon Laboratories Si52143 Si52143 2 Rev 1.2 Si52143 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. SSON Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rev 1.2 3 Si52143 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ± 5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (Single-Ended Outputs) VOH IOH = –1 mA 2.4 — — V 3.3 V Output High Voltage (Single-Ended Outputs) VOL IOL = 1 mA – — 0.4 V High-impedance Output Current IOZ –10 — 10 µA Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH — — 55 mA Output Pin Capacitance Pin Inductance Dynamic Supply Current 4 IDD_3.3V All outputs enabled. Differential clocks with 5” traces and 2 pF load. Rev 1.2 Si52143 Table 2. AC Electrical Specification Parameter Symbol Test Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 45 — 55 % CLKIN Rising and Falling Slew Rate TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 µA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — µA TDC Measured at 0 V differential 45 — 55 % TSKEW Measured at 0 V differential — — 50 ps Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps PCIe Gen 1 Pk-Pk Jitter Pk-Pk PCIe Gen 1 0 40 50 ps PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 0 2 2.6 ps 1.5 MHz< F < Nyquist Rate 0 2 2.6 ps RMSGEN3 Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 0.5 0.9 ps LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew Rate TR / TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV — –0.5 — % 30 31.5 33 kHz Crystal Long-term Accuracy Clock Input Duty Cycle DIFF at 0.7 V Duty Cycle Output-to-Output Skew PCIe Gen 3 Phase Jitter Long Term Accuracy Crossing Point Voltage at 0.7 V Swing Spread Range SPR-2 Modulation Frequency FMOD Down spread Note: Visit www.pcisig.com for complete PCIe specifications. Rev 1.2 5 Si52143 Table 2. AC Electrical Specification (Continued) Parameter Symbol Test Condition Min Typ Max Unit TDC Measurement at 1.5 V 45 — 55 % TR / TF Measured between 0.8 and 2.0 V 1.0 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 300 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm REF(25 MHz) at 3.3 V Duty Cycle Rising and Falling Edge Rate Enable/Disable and Set-Up Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Note: Visit www.pcisig.com for complete PCIe specifications. Table 3. Absolute Maximum Conditions Parameter Symbol Test Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 35 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 Rev 1.2 Si52143 2. Functional Description 2.1. Crystal Recommendations If using crystal input, the device requires a parallel resonance 25 MHz crystal. Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. Crystal Loading Crystal loading is critical for ppm accuracy. In order to achieve low/zero ppm error, use the calculations below in section 2.1.2 to estimate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using two trim capacitors. It is important that the trim capacitors are in series with the crystal. Figure 1. Crystal Capacitive Clarification 2.1.2. Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. The capacitance on each side is in series with the crystal. The total capacitance on both sides is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Rev 1.2 7 Si52143 Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: Crystal load capacitance CLe: Actual loading seen by crystal using standard value trim capacitors Ce: External trim capacitors Cs: Stray capacitance (terraced) Ci : Internal capacitance (lead frame, bond wires, etc.) 2.2. OE Pin Definition The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins is required to be driven at all time and even though it has an internally 100 k resistor. 2.3. OE Assertion The OE signals are active high input used for synchronous stopping and starting the output clocks respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes stopped respective output clocks to resume normal operation. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles. 2.4. OE Deassertion When the OE pin is deasserted by making its logic low, the corresponding output clocks are stopped cleanly, and the final output state is driven low. 2.5. SSON Pin Definition SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread. 8 Rev 1.2 Si52143 3. Test and Measurement Setup Figure 3 shows the test load configuration for HCSL clock outputs. M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" M e a s u re m e n t P o in t L1 O U T- 5 0 2 pF Figure 3. 0.7 V Differential Load Configuration Please reference application note AN781 recommendations on how to terminate the differential outputs for LVDS, LVPECL, or CML signalling levels. Figure 4. Differential Output Measurement for Differential Signals (for AC Parameters Measurement) Rev 1.2 9 Si52143 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement L1 = 0.5", L2 = 5" Measurement 50 SE Clocks Point L1 33 L2 4 pF Figure 6. Single-Ended Clocks with Single Load Configuration Figure 7. Single-Ended Output Signal (for AC Parameter Measurement) 10 Rev 1.2 Si52143 4. Control Registers 4.1. I2C Interface To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. Through the I2C Interface, various device functions are available, such as individual clock enablement. The registers associated with the I2C Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. Power management functions can only be programed in program mode and not in normal operation modes. 4.2. Data Protocol The clock driver I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Block Read Protocol Description Bit 1 Start 8:2 Slave address—7 bits Description Start Slave address—7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 Command Code—8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Slave address—7 bits Data byte 1—8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2—8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N—8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Rev 1.2 Byte Count from slave—8 bits Acknowledge Data byte 1 from slave—8 bits Acknowledge Data byte 2 from slave—8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop 11 Si52143 Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address–7 bits 8:2 Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 Rev 1.2 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop Si52143 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D1 D0 R/W R/W R/W D2 D1 D0 REF_OE Name Type D2 R/W R/W R/W R/W R/W Reset settings = 00000100 Bit Name Function 7:3 Reserved 2 REF_OE Output Enable for REF. 0: Output disabled. 1: Output enabled. 1:0 Reserved Control Register 1. Byte 1 Bit D7 D6 D5 D4 D3 Name Type DIFF0_OE R/W R/W R/W R/W R/W R/W DIFF1_OE R/W R/W Reset settings = 00000101 Bit Name 7:3 Reserved 2 DIFF0_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 1 Reserved 0 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. Rev 1.2 13 Si52143 Control Register 2. Byte 2 Bit D7 D6 Name DIFF2_OE DIFF3_OE Type R/W R/W D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W D2 D1 D0 Reset settings = 11000000 Bit Name Function 7 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 6 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. 5:0 Reserved Control Register 3. Byte 3 Bit D7 D6 Name Type D5 D4 D3 Rev Code[3:0] R/W R/W R/W Vendor ID[3:0] R/W R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W Reset settings = 00001000 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Control Register 4. Byte 4 Bit D7 D6 D5 D4 Name Type BC[7:0] R/W R/W R/W R/W Reset settings = 00000110 14 Bit Name 7:0 BC[7:0] Function Byte Count Register. Rev 1.2 Si52143 Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W Reset settings = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV Rev 1.2 011: 600 mV 111: 1000 mV 15 Si52143 VSS_CORE XIN/CLKIN XOUT VDD_CORE SDATA SCLK 5. Pin Descriptions: 24-Pin QFN 24 23 22 21 20 19 VDD_REF 1 1 18 OE[3:2] REF 2 17 VDD_DIFF SSON2 3 VSS_REF 4 OE_REF1 5 VDD_DIFF 6 16 DIFF3 25 GND 15 DIFF3 14 DIFF2 7 8 9 10 11 12 OE[1:0]1 DIFF0 DIFF0 DIFF1 DIFF1 VDD_DIFF 13 DIFF2 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Table 7. Si52143 24-Pin QFN Descriptions Pin # Name 1 VDD_REF 2 REF 3 SSON I,PD Active high input pin enables –0.5% spread on DIFF outputs (internal 100 k pull-down). 4 VSS_REF GND Ground 5 OE_REF I,PU Active high input to enable or disable REF clock. 6 VDD_DIFF 7 OE[1:0] 8 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 9 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 10 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output. 16 Type Description PWR 3.3 V power supply. O, SE 3.3 V, 25 MHz crystal reference clock output. PWR 3.3 V power supply. I,PU Active high input to enable or disable DIFF0 and DIFF1 clocks. Rev 1.2 Si52143 Table 7. Si52143 24-Pin QFN Descriptions (Continued) Pin # Name Type Description 11 DIFF1 12 VDD_DIFF 13 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output. 14 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output. 15 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output. 16 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output. 17 VDD_DIFF 18 OE[3:2] I,PU 19 SCLK I 20 SDATA I/O 21 VDD_CORE 22 XOUT O 25.00 MHz crystal output, Float XOUT if using only CLKIN (Clock input). 23 XIN/CLKIN I 25.00 MHz crystal input or 3.3 V, 25 MHz Clock Input. 24 VSS_CORE GND Ground. 25 GND GND Ground for bottom pad of the IC. O, DIF 0.7 V, 100 MHz differential clock output. PWR 3.3 V power supply. PWR 3.3 V power supply. Active high input to enable or disable DIFF2 and DIFF3 clocks. I2C SCLOCK. I2C SDATA. PWR 3.3 V power supply. Rev 1.2 17 Si52143 6. Ordering Guide Part Number Package Type Temperature Si52143-A01AGM 24-pin QFN Industrial, –40 to 85 C Si52143-A01AGMR 24-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 18 Rev 1.2 Si52143 7. Package Outline Figure 8 illustrates the package details for the Si52142. Table 8 lists the values for the dimensions shown in the illustration. Figure 8. 24-Pin Quad Flat No Lead (QFN) Package Table 8. Package Diagram Dimensions Symbol Millimeters Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.20 0.25 0.30 D D2 4.00 BSC 2.60 e 2.70 2.80 0.50 BSC E 4.00 BSC E2 2.60 2.70 2.80 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.2 19 Si52143 DOCUMENT CHANGE LIST Revision 0.1 to Revision 1.0 Updated Features on page 1. Updated Description on page 1. Updated Table 1 on page 4. Updated Table 2 on page 5. Updated Section 2.1 on page 7. Updated Section 2.1.1 on page 7. Updated Section 4.1 on page 11. Updated Section 4.2 on page 11. Updated Pin Descriptions on page 16. Revision 1.0 to Revision 1.1 Removed Moisture Sensitivity Level specification from Table 3. Revision 1.1 to Revision 1.2 20 Updated Table 2. Updated Section 3. Rev 1.2 Si52143 NOTES: Rev 1.2 21 Si52143 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Rev 1.2