CY28405-3 Clock Synthesizer with Differential SRC and CPU Outputs Features • Three differential CPU clock pairs • One differential SRC clock • Supports Intel Pentium® 4-type CPUs • Support SMBus/I2C Byte, Word and Block Read/ Write • Selectable CPU frequencies • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • Nine copies of PCI clocks • Four copies of 3V66 with one optional VCH • Two copies 48-MHz clock • 48-pin SSOP package CPU SRC 3V66 PCI REF 48M x3 x1 x4 x9 x2 x2 • Two copies of REF [1] Block Diagram XIN XOUT XTAL OSC FS_(A:B) VTT_PWRGD# VDD_REF REF(0:1) PLL Ref Freq VDD_CPU CPUT(0:1, ITP), CPUC(0:1, ITP) Divider Network VDD_SRCT SRCT, SRCC ~ PLL 1 Pin Configuration IREF VDD_3V66 3V66_(0:2) 2 PCI(0:5) 3V66_3/VCH VDD_48MHz DOT_48 PD# USB_48 SDATA SCLK I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28405-3 VDD_PCI PCIF(0:2) PLL2 *FS_A/REF_0 *FS_B/REF_1 VDD_REF XIN XOUT VSS_REF PCIF0 PCIF1 PCIF2 VDD_PCI VSS_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI VSS_PCI PCI4 PCI5 PD# DOT_48 USB_48 VSS_48 VDD_48 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA VSSA IREF CPUT_ITP CPUC_ITP VSS_CPU CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS_SRC SRCT SRCC VDD_SRC VTT_PWRGD# SDATA* SCLK* 3V66_0 3V66_1 VSS_3V66 VDD_3V66 3V66_2 3V66_3/VCH SSOP-48 * 100k Internal Pull-up Note: 1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively. Cypress Semiconductor Corporation Document #: 38-07584 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 23, 2003 CY28405-3 Pin Description Pin No. Name Type Description 1 FS_A/REF_0 I/O, SE This pin is the FS_A at power-up and VTT_PWRGD# = 0, then it becomes REF_0 output. (3.3V 14.318-MHz clock output.) 2 FS_B/REF_1 I/O, SE This pin is the FS_B at power up and VTT_PWRGD# = 0, then it becomes REF_1 output. (3.3V 14.318-MHz clock output.) 4 XIN 5 I Crystal connection or external reference frequency input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. XOUT O, SE Crystal connection. Connection for an external 14.318-MHz crystal output. 39, 42, 38, 41, 45, 44 CPUT(0:1), CPUC(0:1), CPUT_ITP, CPUC_ITP O, DIF CPU clock output. Differential CPU clock outputs. See Table 1 for frequency configuration. 36, 35 SRCT, SRCC O, DIF Differential serial reference clock. 26, 29, 30 3V66(2:0) O, SE 66-MHz clock output. 3.3V 66-MHz clock from internal VCO. 25 3V66_3/VCH O, SE 48- or 66-MHz clock output. 3.3V selectable through SMBUS to be 66 MHz or 48 MHz. Default is 66 MHz. 7, 8, 9 PCI_F(0:2) O, SE Free-running PCI Output. 33-MHz clocks divided down from 3V66. O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66. 12, 13, 14, 15, 18, PCI(0:5) 19 22 USB_48 O, SE Fixed 48-MHz clock output. 21 DOT_48 O, SE Fixed 48-MHz clock output. 46 IREF I 20 PD# I, PU 33 VTT_PWRGD# 32 SDATA I I/O, PU Current Reference. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for PowerDown# active low. 3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E] input (active low). SMBus-compatible SDATA. 31 SCLK I, PU SMBus-compatible SCLOCK. 48 VDDA PWR 3.3V power supply for PLL. 47 VSSA GND Ground for PLL. 3, 10, 16, 24, 27, 34, 40 VDD PWR 3.3V power supply for outputs. 6, 11, 17, 23, 28, 37, 43 VSS GND Ground for outputs. Frequency Select Pins (FS_A, FS_B) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A and FS_B inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A & FS_B input values. For all logic levels of FS_A and FS_B VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled low, all further VTT_PWRGD#, FS_A, and FS_B transitions will be ignored. Once “Test Clock Mode” has been invoked, all further FS_B transitions will be ignored and FS_A will asynchronously select between the Hi-Z and REF/N mode. Exiting test mode is accomplished by cycling power with FS_B in a high or low state. Document #: 38-07584 Rev. ** Page 2 of 16 CY28405-3 Table 1. Frequency Select Table (FS_A FS_B) FS_A FS_B CPU SRC 3V66 PCIF/PCI REF0 REF1 USB/DOT 0 0 100 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz 0 B6b7 REF/N REF/N REF/N REF/N REF/N REF/N REF/N 0 1 200 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz 1 0 133 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz 1 B6b7 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1 FS_A FS_B CPU SRC 3V66 PCIF/PCI REF0 REF1 USB/DOT 0 0 200 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz 0 1 400 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz 1 0 266 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 19 20 21:27 Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Document #: 38-07584 Rev. ** 30:37 38 Byte count from slave – 8 bits Acknowledge from master Page 3 of 16 CY28405-3 Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Block Read Protocol Description Bit 39:46 Description .... ...................... Data byte from slave – 8 bits .... Data Byte (N–1) –8 bits 47 .... Acknowledge from slave 48:55 .... Data Byte N –8 bits 56 Acknowledge from master .... Acknowledge from slave .... Data byte N from slave – 8 bits .... Stop .... Acknowledge from master .... Stop Acknowledge from master Data byte from slave – 8 bits Table 5. Byte Read and Byte Write protocol Byte Write Protocol Bit 1 2:8 Byte Read Protocol Description Bit Start 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte from master – 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Acknowledge from master 39 Stop Byte Configuration Map Byte 0: Control Register Bit @Pup Name Description 7 0 Reserved Reserved, set = 0 6 1 PCIF PCI PCI Drive Strength Override 0 = Force All PCI and PCIF Outputs to Low Drive Strength 1 = Force All PCI and PCIF Outputs to High Drive Strength 0 Reserved Reserved, set = 0 4 5 0 Reserved Reserved, set = 0 3 1 Reserved Reserved, set = 1 2 1 Reserved Reserved, set = 1 1 HW FS_B Power up latched value of FS_B pin 0 HW FS_A Power up latched value of FS_A pin Document #: 38-07584 Rev. ** Page 4 of 16 CY28405-3 Byte 1: Control Register Bit @Pup Name Description 7 0 SRCT SRCC Allow control of SRC during SW PCI_STP assertion 0 = Free Running, 1 = Stopped with SW PCI_STP 6 1 SRCT SRCC SRC Output Enable 0 = Disabled (three-state), 1 = Enabled 5 1 Reserved Reserved, set = 1 4 1 Reserved Reserved, set = 1 3 1 Reserved Reserved, set = 1 2 1 CPUT_ITP, CPUC_ITP CPU_ITP Output Enable 0 = Disabled (three-state), 1 = Enabled 1 1 CPUT1, CPUC1 CPU(T/C)1 Output Enable, 0 = Disabled (three-state), 1 = Enabled 0 1 CPUT0, CPUC0 CPUT/C)0 Output Enable 0 = Disabled (three-state), 1 = Enabled Byte 2: Control Register Bit @Pup Name Description 7 0 SRCT, SRCC SRCT/C Pwrdwn drive mode 0 = Driven in power down, 1 = three-state in power down 6 0 SRCT, SRCC SRC Stop drive mode 0 = Driven in PCI_STP, 1 = three-state in power down 5 0 CPUT_ITP, CPUC_ITP CPU(T/C)_ITP Pwrdwn drive mode 0 = Driven in power down, 1 = three-state in power down 4 0 CPUT1, CPUC1 CPU(T/C)1 Pwrdwn drive mode 0 = Driven in power down, 1 = three-state in power down 3 0 CPUT0, CPUC0 CPU(T/C)0 Pwrdwn drive mode 0 = Driven in power down, 1 = three-state in power down 2 0 Reserved Reserved, set = 0 1 0 Reserved Reserved, set = 0 0 0 Reserved Reserved, set = 0 Byte 3: Control Register Bit @Pup Name Description 7 1 SW PCI STOP SW PCI_STP Function 0= PCI_STP assert, 1= PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses. 6 1 Reserved Reserved 5 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 3 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 2 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 0 1 PCI0 PCI0 Output Enable 0 = Disabled, 1 = Enabled Document #: 38-07584 Rev. ** Page 5 of 16 CY28405-3 Byte 4: Control Register Bit @Pup Name Description 7 0 USB_48 USB_48MHz Drive Strength Control 0 = Low Drive Strength, 1 = High Drive Strength 6 1 USB_48 USB_48MHz Output Enable 0 = Disabled, 1 = Enabled 5 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP 4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP 3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP 2 1 PCIF2 PCIF2 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled 0 1 PCIF0 PCIF0 Output Enable 0 = Disabled, 1 = Enabled Byte 5: Control Register Bit 7 @Pup Name Description 1 DOT_48 DOT_48MHz Output Enable 0 = Disabled, 1 = Enabled 6 1 Reserved Reserved 5 0 3V66_3/VCH 3V66_3/VCH Frequency Select 0 = 3V66 mode, 1 = VCH (48MHz) mode 4 1 3V66_3/VCH 3V66_3/VCH Output Enable 0 = Disabled, 1 = Enabled 3 1 Reserved Reserved, set = 1 2 1 3V66_2 3V66_2 Output Enable 0 = Disabled, 1 = Enabled 1 1 3V66_1 3V66_1 Output Enable 0 = Disabled, 1 = Enabled 0 1 3V66_0 3V66_0 Output Enable 0 = Disabled, 1 = Enabled Byte 6: Control Register Bit @Pup Name Description 7 0 Reserved Reserved, set = 0 6 0 Reserved Reserved, set = 0 5 0 CPUC0, CPUT0 CPUC1, CPUT1 CPUT_ITP,CPUC_ITP FS_A & FS_B Operation 0 = Normal, 1 = Test mode 4 0 SRCT, SRCC SRCT/C Frequency Select 0 = 100Mhz, 1 = 200MHz 3 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP Spread Spectrum Mode 0 = down (default), 1 = center Document #: 38-07584 Rev. ** Page 6 of 16 CY28405-3 Byte 6: Control Register (continued) Bit @Pup Name Description 2 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP Spread Spectrum Enable 0 = Spread Off, 1 = Spread On 1 1 REF_1 REF_1 Output Enable 0 = Disabled, 1 = Enabled 0 1 REF_0 REF_0 Output Enable 0 = Disabled, 1 = Enabled Byte 7: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 1 0 0 0 Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Crystal Recommendations The CY28405-3 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28405-3 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Table 6. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 50 ppm 50 ppm 5 ppm 20 pF Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Document #: 38-07584 Rev. ** Figure 1. Crystal Capacitive Clarification Page 7 of 16 CY28405-3 Calculating Load Capacitors Clock Chip (CY28405-2) In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Ci2 Ci1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values from Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal ......................................using standard value trim capacitors Ce .....................................................External trim capacitors Cs..............................................Stray capacitance (trace,etc) Ci ............. Internal capacitance (lead frame, bond wires etc) PD# (Power-down) Clarification The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# Document #: 38-07584 Rev. ** Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD# – Assertion When PD# is sampled low by two consecutive rising edges of CPUC clock then all clock outputs (except CPU) clocks must be held low on their next high to low transition. CPU clocks must be hold with CPU clock pin driven high with a value of 2x Iref and CPUC undriven. Due to the state of itnernal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete Page 8 of 16 CY28405-3 PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Figure 3. Power-down Assertion Timing Waveforms PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. Tstable <1.8nS PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Tdrive_PWRDN# <300µS, >200mV Figure 4. Power-down Deassertion Timing Waveforms Document #: 38-07584 Rev. ** Page 9 of 16 CY28405-3 FS_A, FS_B VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen Clock State Clock Outputs Clock VCO State 0 W ait for VTT_PW RGD# State 1 Device is not affected, VTT_PW RGD# is ignored Sample Sels State 2 Off State 3 On On Off Figure 5. VTT_PWRGD# Timing Diagram S2 S1 Delay >0.25mS VTT_PWRGD# = Low Sample Inputs straps VDD_A = 2.0V Wait for <1.8ms S0 Power Off S3 VDD_A = off Normal Operation Enable Outputs VTT_PWRGD# = toggle Figure 6. Clock Generator Power-up/Run State Diagram Document #: 38-07584 Rev. ** Page 10 of 16 CY28405-3 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 36.9 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 83.5 °C/W UL–94 Flammability Rating At 1/8 in. V–0 MSL Moisture Sensitivity Level 2000 – V 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V VDD, VDDA 3.3 Operating Voltage 3.3V ± 5% VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VIL Input Low Voltage VSS–0.5 0.8 V VIH Input High Voltage Except SDATA and SCLK 2.0 VDD+0. 5 V IIL Input Leakage Current except Pull ups or Pull downs 0 < VIN < VDD –5 5 µA IILI2C Forward Bias Current VDD = OFF, SCLK and SDATA at 0V or 3.3V –5 5 µA VOL Output Low Voltage IOL = 1 mA – 0.4 V VOH Output High Voltage IOH = –1 mA 2.4 – V IOZ High-Impedance Output Current –10 10 µA CIN Input Pin Capacitance 2 5 pF COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD Dynamic Supply Current At 200 MHz and all outputs loaded per Table 9 and Figure 7 – 350 mA IPD Power-down Supply Current PD# asserted, all differential outputs three-stated. – 2 mA Document #: 38-07584 Rev. ** Page 11 of 16 CY28405-3 AC Electrical Specifications Parameter Description Condition Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN period When Xin is driven from an external clock source TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps LACC Long-term Accuracy Over 150 ms 300 ppm CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.9970 10.003 ns TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.4978 7.5023 ns TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.9985 5.0015 ns TSKEW Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX – 100 ps TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps TR / TF CPUT and CPUC Rise and Fall Times Measured from Vol = 0.175 to Voh = 0.525V 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR-TF)/(TR+TF) – 20 % ∆TR Rise Time Variation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 7 660 850 mV VLOW Voltage Low Math averages Figure 7 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 7. Measure SE – 0.2 V SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100 MHz SRCT and SRCC Period Measured at crossing point VOX 9.9970 10.003 ns TPERIOD 200 MHz SRCT and SRCC Period Measured at crossing point VOX 4.9985 5.0015 ns LACC Long Term Accuracy Measured at crossing point VOX – 300 ppm TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX TR / TF SRCT and SRCC Rise and Fall Times Measured from Vol= 0.175 to Voh = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR-TF)/(TR+TF) ∆TR Rise Time Variation ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 7 660 850 mv VLOW Voltage Low Math averages Figure 7 –150 – mv VOX Crossing Point Voltage at 0.7V Swing 250 550 mV Document #: 38-07584 Rev. ** – 125 ps 175 700 ps – 20 % – 125 ps Page 12 of 16 CY28405-3 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit – VHIGH + 0.3 V VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage VRB Ring Back Voltage 3V66 TDC 3V66 Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled 3V66 Period Measurement at 1.5V 14.9955 15.0045 ns TPERIOD Spread Enabled 3V66 Period Measurement at 1.5V 14.9955 15.0799 ns THIGH 3V66 High Time Measurement at 2.0V 4.9500 – ns TLOW 3V66 Low Time Measurement at 0.8V 4.5500 – ns TR / TF 3V66 Rise and Fall Times Measured between 0.8V and 2.0V 0.5 2.0 ns TSKEW Any 3V66 to Any 3V66 Clock Skew Measurement at 1.5V – 250 ps TCCJ 3V66 Cycle-to-Cycle Jitter Measurement at 1.5V – 250 ps PCI/PCIF TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.9910 30.0009 ns TPERIOD Spread Enabled PCIF/PCI Period Measurement at 1.5V 29.9910 30.1598 ns THIGH PCIF and PCI High Time Measurement at 2.0V 12.0 – ns TLOW PCIF and PCI Low Time Measurement at 0.8V 12.0 – ns TR / TF PCIF and PCI Rise and Fall Times Measured between 0.8V and 2.0V 0.5 2.0 ns TSKEW Any PCI clock to Any PCI Clock Skew Measurement at 1.5V – 500 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 250 ps DOT TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.8271 20.8396 ns THIGH USB High Time Measurement at 2.0V 8.094 10.036 ns TLOW USB Low Time Measurement at 0.8V 7.694 9.836 ns TR / TF Rise and Fall Times Measured between 0.8V and 2.0V 1.0 2.0 ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps TSKEW Any 48 MHz to 48 MHz clock skew Measurement @1.5V – 500 ps USB TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.8271 20.8396 ns THIGH USB High Time Measurement at 2.0V 8.094 10.036 ns TLOW USB Low Time Measurement at 0.8V 7.694 9.836 ns TR / TF Rise and Fall Times Measured between 0.8V and 2.0V 1.0 2.0 ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps TSKEW Any 48 MHz to 48 MHz Clock Skew Measurement @1.5V – 500 ps REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.827 69.855 ns TR / TF REF Rise and Fall Times Measured between 0.8V and 2.0V 1.0 4.0 V/ns Document #: 38-07584 Rev. ** See Figure 7. Measure SE –0.3 – V – 0.2 V Page 13 of 16 CY28405-3 AC Electrical Specifications (continued) Min. Max. Unit TCCJ Parameter REF Cycle to Cycle Jitter Description Measurement at 1.5V Condition – 1000 ps TSKEW Any REF to REF clock skew Measurement @1.5V – 500 ps – 1.8 ms 10.0 – ns 0 – ns ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time TSH Stopclock Hold Time Table 7. Group Timing Relationship and Tolerances Offset Group Conditions Min. Max. 3V66 to PCI 3V66 Leads PCI 1.5ns 3.5ns Table 8. USB to DOT Phase Offset Parameter Typical Value Tolerance DOT Skew 0° 0.0ns 1000 ps USB Skew 180° 0.0ns 1000 ps VCH SKew 0° 0.0ns 1000 ps Test and Measurement Set-up Table 9. Maximum Lumped Capacitive Output Loads Clock Max Load Units PCI Clocks 30 pF 3V66 Clocks 30 pF USB Clock 20 pF DOT Clock 10 pF REF Clock 30 pF For Differential CPU and SRC Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. CPUT CPUC IR E F TPCB 33Ω 4 9 .9 Ω 33Ω M e a s u re m e n t P o in t 2pF TPCB 4 9 .9 Ω M e a s u re m e n t P o in t 2pF 475Ω Figure 7. 0.7V Load Configuration Document #: 38-07584 Rev. ** Page 14 of 16 CY28405-3 O u tp u t u n d e r T e s t P ro b e Load Cap 3 .3 V s ig n a l s tD C - - 3 .3 V 2 .0 V 1 .5 V 0 .8 V 0V Tf Tr Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement) Table 10.CPU Clock Current Select Function Board Target Trace/Term Z Reference R, IREF – VDD (3*RREF) Output Current VOH @ Z 50 Ohms RREF = 475 1%, IREF = 2.32mA IOH = 6*IREF 0.7V @ 50 Ordering Information Part Number CY28405OC-3 CY28405OC-3T Package Type 48-pin SSOP 48-pin SSOP – Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 51-85061-*C Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips 2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification I as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07584 Rev. ** Page 15 of 16 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28405-3 Document History Page Document Title: CY28405-3 Clock Synthesizer with Differential SRC and CPU Outputs Document Number: 38-07584 REV. ECN NO. Issue Date Orig. of Change ** 129683 09/25/03 RGL Document #: 38-07584 Rev. ** Description of Change New Data Sheet Page 16 of 16