Application Note Rev. 1.20 / July 2013 ZSPM401x Application Circuit Layout and Component Selection Analog Power ICs Powerful and Determined ZSPM401x Application Circuit Layout and Component Selection Contents 1 2 3 4 5 6 Introduction ......................................................................................................................................................... 3 Typical Application Schematic............................................................................................................................ 3 Printed Circuit Board (PCB) Layout Guidelines ................................................................................................. 4 Recommended Bill of Materials ......................................................................................................................... 6 Component Selection ......................................................................................................................................... 7 ZSPM401x Evaluation Board Example .............................................................................................................. 8 6.1. Input Capacitor Selection for Evaluation Board Example ........................................................................... 8 6.2. Output Capacitor Selection for Evaluation Board Example ......................................................................... 9 7 Thermal Consideration ....................................................................................................................................... 9 8 Document Revision History ................................................................................................................................ 9 For more information, contact ZMDI via [email protected]. Application Note July 10, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 2 of 9 ZSPM401x Application Circuit Layout and Component Selection 1 Introduction This application note covers layout guidelines and application details for the ZSPM401x family of DC/DC synchronous switching regulators. The ZSPM401x provides fully integrated power switches, internal compensation, and full fault protection for a broad range of applications. Depending on the product version, the output can either be a fixed value or an adjustable voltage determined by external components. Typical applications include wireless access points; cable modems; printers; set-top boxes; supplies for DVDs, LCDs, and LEDs; and portable products including GPS devices, smart phones, and tablet PCs. 2 Typical Application Schematic The typical ZSPM401x application circuit for the product version with an adjustable output (ZSPM401xBA1W00) includes bypass capacitors on the VCC input pin, a resistive voltage divider to set the voltage on the FB feedback pin, an optional pull-up resistor for the power-good signal on the PG pin, a bootstrap capacitor on the BST pin, an output inductor, output filtering capacitors, and an optional output diode for improving load regulation and efficiency. (See Figure 2.1.) The typical ZSPM401x application circuit for the product version with a fixed voltage output is the same except the voltage divider is not used and the FB feedback pin is connected directly to V OUT. (See Figure 2.2.) Refer to the ZSPM401x Data Sheet for requirements and recommendations for external components. Figure 2.1 ZSPM4011/12/13 Application Schematic for Adjustable Output ZSPM401xBA1W00 BST VCC VCC 10µF 35V 0.1µF (optional) EN GND EN 22nF ZSPM401xB00 CBYPASS2 Application Note July 10, 2013 PGND CBYPASS1 CBST VSW VOUT LOUT 4.7µH DCATCH (optional) RTOP FB RBOT COUT1 COUT2 22µF 10V 22µF 10V VOUT RPUP 10 kΩ (optional) PG PG © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 3 of 9 ZSPM401x Application Circuit Layout and Component Selection Figure 2.2 ZSPM4011/12/13 Application Schematic for Fixed Voltage Output BST VCC VCC 10µF 35V 0.1µF (optional) EN GND EN 3 CBST 22nF ZSPM401xB00 CBYPASS2 PGND CBYPASS1 VSW VOUT LOUT 4.7µH DCATCH (optional) COUT1 COUT2 22µF 10V 22µF 10V VOUT FB RPUP 10 kΩ (optional) PG PG Printed Circuit Board (PCB) Layout Guidelines For proper operation and minimum EMI, care must be taken during PCB layout. An improper layout can lead to issues such as poor stability and regulation, noise sensitivity, and increased EMI radiation. Figure 3.1 provides an example of a proper layout for the adjustable output version of the ZSPM401x. The main guidelines are the following: Provide low inductive and resistive paths for loops with high di/dt Provide low capacitive paths with respect to all the other nodes for traces with high di/dt Ensure that sensitive nodes not assigned to power transmission are referenced to the analog signal ground (GND) and always separated from the power ground (PGND) The negative ends of CBYPASS, COUT, and the optional Schottky diode DCATCH should be placed close to each other and connected using a wide trace. Use vias to connect the PGND node to the ground plane. To avoid additional voltage drop in traces, place the PGND node as close as possible to the ZSPM401x PGND pins. Place the bypass capacitor CBYPASS (optionally paralleled to a 0.1µF capacitor) as close as possible to the VCC pins of ZSPM401x. In order to minimize the area between the VSW pins and the output components (LOUT and COUT), place the inductor close to the VSW pins and connected directly to VOUT, the output inductor LOUT, the output capacitor COUT, and the PGND pins. Minimize the trace area and length of the switching nodes VSW and BST. Application Note July 10, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 4 of 9 ZSPM401x Application Circuit Layout and Component Selection Keep the traces of the sensitive node FB as short as possible and away from switching signals. For the adjustable output voltage version of the ZSPM401x, feedback resistors R BOT and RTOP are required and should be placed close to the ZSPM401x. RBOT must be connected to the analog ground pin (GND) directly and must never be connected to the ground plane. The analog ground trace (GND) should be connected in only one point to the power ground (PGND). A good connection point is the exposed thermal pad and vias under the ZSPM401x package, which are connected to PGND. Use a trace that ends close to the actual load to connect R TOP to the VOUT node. Connect the FB pin directly to VOUT for fixed output voltage versions of the ZSPM401x where R BOT and RTOP are not required. The exposed thermal pad must be soldered to the PCB for mechanical reliability and to achieve good power dissipation. Vias must be placed under the pad to transfer the heat to the ground plane. Figure 3.1 provides an example of a layout for an application board that follows these guidelines and is designed for the adjustable output version of the ZSPM401xB. See section 4 for recommended parts for this layout. Figure 3.1 ZSPM401X PCB Example Layout, Top View for Adjustable Output Version ZSPM401xBA1W00 VOUT COUT2 LOUT VSW VCC VCC BST GND EN PG NC FB July 10, 2013 VSW VCC RPUP CBYPASS1 PGND Application Note VSW NC Vias to Ground Plane PGND VSW CBYPASS2 PGND DCATCH Switching Node CBST COUT1 RBOT VCC Analog Ground (GND) RTOP Vias to Ground Plane © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 5 of 9 ZSPM401x Application Circuit Layout and Component Selection 4 Recommended Bill of Materials Table 4.1 provides recommended values and possible sources for external components for a typical application circuit. As discussed in section 6, the ZSPM401xB Evaluation Board in the ZSPM401xB Evaluation Kit is an example of a typical application circuit. Table 4.1 correlates the parts on the Evaluation Board (see Figure 6.1) with components in Figure 2.1. “NL” (no linkage) indicates the component is not placed on the Evaluation Board. Components marked with an asterisk (*) are only used with the adjustable versions of the ZSPM401x. Table 4.1 External Components and Sources Evaluation Kit Reference Functional Reference Functional Description Part Footprint Manufacturer Manufacturer P/N C1 CBYPASS1 Input Supply Bypass Cap. 10μF 0805 TDK C2012X5R1E106M C2 CBYPASS1 Input Supply Bypass Cap. 10μF 0805 TDK C2012X5R1E106M CBYPASS2 Bypass Capacitor (optional) 0.1μF C3 CBST Boost Capacitor 22nF 0603 TDK C2012C0G1E223J C4 COUT1 Output Filter Capacitor 22μF 0805 Murata GRM21BR60J226ME39L C5 COUT2 Output Filter Capacitor 22μF 0805 Murata GRM21BR60J226ME39L NL 0603 C6 Use if CBYPASS1 low ESR ceramic cap. NL on Eval. Board. D1 DCATCH Catch Diode (optional) Schottky L1 LOUT Output Filter Inductor 4.7μH R1 RTOP Voltage Feedback Resistor* 6.04kΩ 0603 R2.1 RBOT Voltage Feedback Resistor* NL 0603 R2.2 RBOT Voltage Feedback Resistor* R2.3 RBOT Voltage Feedback Resistor* R2.4 RBOT Voltage Feedback Resistor* R2.5 RBOT Voltage Feedback Resistor* R2.6 RBOT Voltage Feedback Resistor* R2.7 RBOT Voltage Feedback Resistor* R2.8 RBOT Voltage Feedback Resistor* R3 RPUP PG Pin Pull-up Resistor U1 Application Note July 10, 2013 53.6kΩ 17.8kΩ 9.09kΩ 6.04kΩ 3.40kΩ 2.26kΩ 1.33kΩ 10kΩ ZSPM401x DC/DC Regulator ZSPM401XB Recommended for ZSPM4013BA1Wxx. NL on Eval. Board. Wurth 7447779004 Susumu RR0816P-6041-D-76H 0603 Susumu RR0816P-5362-D-71C 0603 Susumu RR0816P-1782-D-25C 0603 Susumu RR0816P-9091-D-93H 0603 Susumu RR0816P-6041-D-76H 0603 Susumu RG1608P-3401-B-T5 0603 Susumu RG1608P-2261-B-T5 0603 Welwyn PCF0603R-1K33BT1 0603 QFN 3mm x 3mm x 1mm Required if PG is used. NL on Eval. Board ZSPM401xBA1Wxx ZMDI (ZSPM401xBA1W00 is used on the Eval. Bd.) © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 6 of 9 ZSPM401x Application Circuit Layout and Component Selection 5 Component Selection The 1MHz internal switching frequency of the ZSPM401x facilitates low-cost LC filter combinations. The fixed output versions allow a minimum external component count while providing a complete regulation solution with only four external components: an input bypass capacitor, an inductor, an output capacitor, and the bootstrap capacitor. The internal compensation is optimized for a total of 44µF of output capacitance and a 4.7µH inductor. For best performance, a low ESR ceramic capacitor should be used for C BYPASS. If CBYPASS is not a low ESR ceramic capacitor, a 0.1µF ceramic capacitor should be added in parallel to CBYPASS. The minimum allowable value for the total output capacitance is 33µF. To keep the output ripple low, a low ESR (less than 35mΩ) ceramic is recommended. Multiple capacitors can be used in parallel to reduce the ESR. The inductor range is 4.7µH +/-20%. For optimal over-current protection, the inductor should be able to handle up to the regulator current limit without saturation. Otherwise, an inductor with a saturation current rating higher than the maximum IOUT load requirement plus the inductor current ripple should be used. For high current modes (3A for example), the optional Schottky diode DCATCH will improve the overall efficiency and reduce heat. It is up to the user to determine the cost/benefit of adding this additional component in the user’s application. The diode is typically not needed. For the adjustable output version of the ZSPM401x, the output voltage can be adjusted by sizing the RTOP and RBOT feedback resistors. The equation for the output voltage is ( ( )) . For the adjustable version, the ratio of VCC/VOUT cannot exceed 16. The 10kΩ pull-up resistor RPUP is only required when the Power Good signal (PG) is utilized. The recommended tolerance is 0.5%. The value of the bootstrap capacitor CBST for the high-side FET gate driver is 22nF. Connect the capacitor from the BST pin to the VSW pin as shown in Figure 2.1. Application Note July 10, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 7 of 9 ZSPM401x Application Circuit Layout and Component Selection 6 ZSPM401x Evaluation Board Example The ZSPM401x Evaluation Kit uses a board that provides a good example of proper layout and component selection. It is designed to allow evaluating various combinations of the voltage divider feedback resistors (R1 and R2.x) and input/output capacitors. Refer to the ZSPM401x Evaluation Kit Description for details. 6.1. Input Capacitor Selection for Evaluation Board Example There are two locations, C1 and C2, for the input capacitors on the Evaluation Board to evaluate different ESR and capacitances for the application. One of these capacitors should be a low ESR ceramic type, with a recommended minimum value of 10µF. See Table 4.1 for the capacitor values, suppliers, and part locations. Figure 6.1 Schematic for ZSPM401x Evaluation Board as an Application Circuit Example Application Note July 10, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 8 of 9 ZSPM401x Application Circuit Layout and Component Selection 6.2. Output Capacitor Selection for Evaluation Board Example There are two locations, C4 and C5, for the output capacitors on the Evaluation Board. Low ESR single or parallel ceramic capacitors are recommended to keep the output ripple low. However, other capacitors can be evaluated. One capacitor should be of low ESR ceramic type. 7 Thermal Consideration ZSPM401x is designed for a maximum operating junction temperature T j of 125°C. The maximum output power is limited by the power losses that can be dissipated over the thermal resistance given by the package and the PCB structures. The PCB must provide heat sinking to prevent overheating of the ZSPM401x. The exposed metal on the bottom of the QFN package must be soldered to a ground plane. It is strongly recommended that the ground be tied to other copper layers below with thermal vias. Adding more copper to the top and the bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. For a hi-K JEDEC board and 13.5 square inch of 1 oz. copper, the thermal resistance from junction to ambient can be reduced to JA = 38°C/W. The power dissipation of other power components (catch diode, inductor) cause additional copper heating and can further increase the effective ambient temperature of the ZSPM401x. 8 Document Revision History Revision Date Description 1.00 January 23, 2012 First release. 1.10 January 28, 2012 Content update 1.20 July 10, 2013 Updates for schematic and bill of materials. Updates for contact information and imagery on cover and headers. Sales and Further Information www.zmdi.com [email protected] Zentrum Mikroelektronik Dresden AG Global Headquarters Grenzstrasse 28 01109 Dresden, Germany ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Central Office: Phone +49.351.8822.0 Fax +49.351.8822.600 USA Phone +855.275.9634 Phone +408.883.6310 Fax +408.883.6358 European Technical Support Phone +49.351.8822.7.772 Fax +49.351.8822.87.772 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. 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European Sales (Stuttgart) Phone +49.711.674517.55 Fax +49.711.674517.87955 Application Note July 10, 2013 Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +82.31.950.7679 Fax +82.504.841.3026 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 9 of 9