4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Features
1.35V DDR3L-RS SDRAM SODIMM
MT8MTF51264HSZ – 4GB
MT8MTF51264HRZ – 4GB
Features
Figure 1: 204-Pin SODIMMs
(MO-268 R/C G0, R/C H0)
• DDR3L-RS functionality and operations supported
as defined in the component data sheet
• 204-pin, small-outline dual in-line memory module
(SODIMM)
– Standard (front side) layout, PCB 1491, "HSZ"
– Reverse (back side) layout, PCB 1492, "HRZ"
• Fast data transfer rates: PC3-12800, PC3-10600
• 4GB (512 Meg x 64)
• VDD = 1.35V (1.283–1.45V)
• VDD = 1.5V (1.425–1.575V)
• Backward-compatible with standard 1.5V (±0.075V)
DDR3 systems
• VDDSPD = 3.0–3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single-rank
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Onboard I2C serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Module height: 30mm (1.18in)
No components this side of module
PCB 1491, front side populated
Module height: 30mm (1.18in)
No components this side of module
PCB 1492, back side populated
Options
Marking
• Operating temperature
– Commercial (0°C ≤ T A ≤ +70°C)
• Package
– 204-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
None
Z
-1G6
-1G4
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
-1G6
PC3-12800
1600
-1G4
PC3-10600
-1G1
PC3-8500
-1G0
-80B
tRP
tRC
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
(ns)
(ns)
(ns)
1333
1333
1066
1066
800
667
13.125
13.125
48.125
–
1333
1333
1066
1066
800
667
13.125
13.125
49.125
–
–
–
1066
1066
800
667
13.125
13.125
50.625
PC3-8500
–
–
–
1066
–
800
667
15
15
52.5
PC3-6400
–
–
–
–
–
800
667
15
15
52.5
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
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mtf8c512x64hz_g0_h0.pdf - Rev. D 5/13 EN
CL = 11 CL = 10
tRCD
Products and specifications discussed herein are subject to change by Micron without notice.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Features
Table 2: Addressing
Parameter
4GB
Refresh count
8K
Row address
64K A[15:0]
Device bank address
8 BA[2:0]
Device configuration
4Gb (512 Meg x 8)
Column address
1K A[9:0]
Module rank address
1 S0#
Table 3: Part Numbers and Timing Parameters – 4GB Modules, Standard (Front Side) Layout
Base device: MT41K512M8,1 1.35V 4Gb DDR3L-RS SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT8MTF51264HSZ-1G6__
4GB
512 Meg x 64
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT8MTF51264HSZ-1G4__
4GB
512 Meg x 64
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
Table 4: Part Numbers and Timing Parameters – 4GB Modules, Reverse (Back Side) Layout
Base device: MT41K512M8,1 1.35V 4Gb DDR3L-RS SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT8MTF51264HRZ-1G6__
4GB
512 Meg x 64
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT8MTF51264HRZ-1G4__
4GB
512 Meg x 64
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
Notes:
1. The data sheet for the base device can be found on Micron’s web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Examples: MT8MTF51264HSZ-1G6E2
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Pin Assignments
Pin Assignments
Table 5: Pin Assignments
204-Pin DDR3L-RS SODIMM Front
204-Pin DDR3L-RS SODIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
VREFDQ
53
DQ19
105
VDD
157
DQ42
2
VSS
54
VSS
106
VDD
158
DQ46
3
VSS
55
VSS
107
A10
159
DQ43
4
DQ4
56
DQ28
108
BA1
160
DQ47
5
DQ0
57
DQ24
109
BA0
161
VSS
6
DQ5
58
DQ29
110
RAS#
162
VSS
7
DQ1
59
DQ25
111
VDD
163
DQ48
8
VSS
60
VSS
112
VDD
164
DQ52
9
VSS
61
VSS
113
WE#
165
DQ49
10
DQS0#
62
DQ3#
114
S0#
166
DQ53
11
DM0
63
DM3
115
CAS#
167
VSS
12
DQS0
64
DQ3
116
ODT0
168
VSS
13
VSS
65
VSS
117
VDD
169
DQS6#
14
VSS
66
VSS
118
VDD
170
DM6
15
DQ2
67
DQ26
119
A13
171
DQS6
16
DQ6
68
DQ30
120
NC
172
VSS
17
DQ3
69
DQ27
121
NC
173
VSS
18
DQ7
70
DQ31
122
NC
174
DQ54
19
VSS
71
VSS
123
VDD
175
DQ50
20
VSS
72
VSS
124
VDD
176
DQ55
21
DQ8
73
CKE0
125
NC
177
DQ51
22
DQ12
74
NC
126
VREFCA
178
VSS
23
DQ9
75
VDD
127
VSS
179
VSS
24
DQ13
76
VDD
128
VSS
180
DQ60
25
VSS
77
NC
129
DQ32
181
DQ56
26
VSS
78
A15
130
DQ36
182
DQ61
27
DQS1#
79
BA2
131
DQ33
183
DQ57
28
DM1
80
A14
132
DQ37
184
VSS
29
DQS1
81
VDD
133
VSS
185
VSS
30
RESET#
82
VDD
134
VSS
186
DQS7#
31
VSS
83
A12
135
DQS4#
187
DM7
32
VSS
84
A11
136
DM4
188
DQS7
33
DQ10
85
A9
137
DQS4
189
VSS
34
DQ14
86
A7
138
VSS
190
VSS
35
DQ11
87
VDD
139
VSS
191
DQ58
36
DQ15
88
VDD
140
DQ38
192
DQ62
37
VSS
89
A8
141
DQ34
193
DQ59
38
VSS
90
A6
142
DQ39
194
DQ63
39
DQ16
91
A5
143
DQ35
195
VSS
40
DQ20
92
A4
144
VSS
196
VSS
41
DQ17
93
VDD
145
VSS
197
SA0
42
DQ21
94
VDD
146
DQ44
198
NF
43
VSS
95
A3
147
DQ40
199
VDDSPD
44
VSS
96
A2
148
DQ45
200
SDA
45
DQS2#
97
A1
149
DQ41
201
SA1
46
DM2
98
A0
150
VSS
202
SCL
47
DQS2
99
VDD
151
VSS
203
VTT
48
VSS
100
VDD
152
DQS5#
204
VTT
49
VSS
101
CK0
153
DM5
–
–
50
DQ22
102
NC
154
DQS5
–
–
51
DQ18
103
CK0#
155
VSS
–
–
52
DQ23
104
NC
156
VSS
–
–
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
Check bits: Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
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© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Pin Descriptions
Table 6: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Description
Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT#
Output
Temperature event: The EVENT# pin is asserted by the temperature sensor when crit(open drain) ical temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The
component VDD and VDDQ are connected to the module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address VDD/2.
VREFDQ
Supply
Reference voltage: DQ, DM VDD/2.
VSS
Supply
Ground.
VTT
Supply
Termination voltage: Used for control, command, and address VDD/2.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
DQ Maps
DQ Maps
Table 7: Component-to-Module DQ Map, ('HSZ') Front Side Populated (PCB 1491)
Component
Reference
Number
Component
DQ
U1
U4
U6
U8
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
2
13
U2
0
19
51
1
1
7
1
17
39
2
3
15
2
18
49
3
0
5
3
16
37
4
6
16
4
23
50
5
4
4
5
20
40
6
7
18
6
22
48
7
5
6
7
21
42
0
43
161
0
58
191
1
40
151
1
57
185
2
42
159
2
59
193
3
41
153
3
56
183
4
47
162
4
62
192
5
45
150
5
61
182
6
46
160
6
63
194
7
44
148
7
60
180
0
9
21
0
26
63
1
10
31
1
24
55
2
8
19
2
27
65
3
11
33
3
25
57
4
12
22
4
30
66
5
15
36
5
29
56
6
13
24
6
31
68
7
14
34
7
28
54
0
34
145
0
49
167
1
33
135
1
51
179
2
35
147
2
48
165
3
32
133
3
50
177
4
38
142
4
52
166
5
37
136
5
54
174
6
39
144
6
53
168
7
36
134
7
55
176
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U5
U7
U9
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
DQ Maps
Table 8: Component-to-Module DQ Map, ('HRZ') Back Side Populated (PCB 1492)
Component
Reference
Number
Component
DQ
U2
U4
U6
U8
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
57
185
U3
0
41
153
1
59
193
1
43
161
2
56
183
2
40
151
3
58
191
3
42
159
4
61
182
4
44
148
5
63
194
5
47
162
6
60
180
6
45
150
7
62
192
7
46
160
0
16
37
0
0
5
1
19
51
1
3
15
2
17
39
2
1
7
3
18
49
3
2
13
4
21
42
4
5
6
5
22
48
5
7
18
6
20
40
6
4
4
7
23
50
7
6
16
0
50
177
0
32
133
1
49
167
1
35
147
2
51
179
2
33
135
3
48
165
3
34
145
4
54
174
4
36
134
5
53
168
5
39
144
6
55
176
6
37
136
7
52
166
7
38
142
0
25
57
0
10
31
1
27
65
1
8
19
2
24
55
2
11
33
3
26
63
3
9
21
4
28
54
4
14
34
5
30
66
5
12
22
6
29
56
6
15
36
7
31
68
7
13
24
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U5
U7
U9
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: Functional Block Diagram, 'HSZ' Front Side Populated (PCB 1491)
S0#
DQS0#
DQS0
DM0
DQS1#
DQS1
DM1
DQS2#
DQS2
DM2
SCL
DQS4#
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
DQS3#
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DQS6#
DQS6
DM6
U7
VSS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U2
DM CS# DQS DQS#
VSS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U6
Note:
PDF: 09005aef84fc0fd3
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DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U1
DQS7#
DQS7
DM7
U3
SPD EEPROM
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
BA[2:0]
A[14:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
U8
VSS
A1
SDA
A2
VSS SA0 SA1 VSS
DM CS# DQS DQS#
BA[2:0]: DDR3 SDRAM
A[14:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
DM CS# DQS DQS#
CK0
CK0#
U4
DDR3 SDRAM
Clock, control, command, and address line terminations:
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
CKE0, A[14:0],
RAS#, CAS#, WE#,
S0#, ODT0, BA[2:0]
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DDR3
SDRAM
VTT
DDR3
SDRAM
CK
CK#
VDDSPD
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP A0
VDD
SPD EEPROM
DM CS# DQS DQS#
U5
VDD
DDR3 SDRAM
VTT
Control, command and
address termination
VREFCA
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
8
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© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Functional Block Diagrams
Figure 3: Functional Block Diagram, 'HRZ' Back Side Populated (PCB 1492)
S0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1#
DQS1
DM1
DQS2#
DQS2
DM2
DQS3#
DQS3
DM3
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DQS6#
DQS6
DM6
U8
VSS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U4
DM CS# DQS DQS#
VSS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9
Note:
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DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U5
DQS7#
DQS7
DM7
U1
SPD EEPROM
SCL
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
BA[2:0]
A[14:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
U7
VSS
A1
SDA
A2
VSS SA0 SA1 VSS
DM CS# DQS DQS#
BA[2:0]: DDR3 SDRAM
A[14:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
DM CS# DQS DQS#
CK0
CK0#
U3
DDR3 SDRAM
Clock, control, command, and address line terminations:
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
CKE0, A[14:0],
RAS#, CAS#, WE#,
S0#, ODT0, BA[2:0]
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DDR3
SDRAM
VTT
DDR3
SDRAM
CK
CK#
VDDSPD
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP A0
VDD
SPD EEPROM
DM CS# DQS DQS#
U2
VDD
DDR3 SDRAM
VTT
Control, command and
address termination
VREFCA
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Temperature-Compensated Self Refresh
The DDR3 SDRAM on this module provides low-current self refresh via temperaturecompensated self refresh (TCSR) and substantially reduces self refresh current (IDD6)
values. TCSR takes affect when component case temperature (T C) is less than 45°C and
auto self refresh (ASR) is enabled. ASR is required to utilize the TCSR function. A detailed description of TCSR is available in the 1.35V DDR3L-RS SDRAM data sheet.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3.
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with
JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations between the master (system logic)
and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL
(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. For further information refer to Micron
technical note TN-04-42, "Memory Module Serial Presence-Detect."
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10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 9: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
Table 10: Operating Conditions
Symbol Parameter
VDD
VDD supply voltage
Min
Nom
Max
Units
1.283
1.35
1.45
V
1.425
1.5
1.575
V
Notes
1
VREFCA(DC) Input reference voltage command/ address bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
VREFDQ(DC) I/O reference voltage DQ bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
–600
–
600
mA
0.49 × VDD 20mV
0.5 × VDD
0.51 × VDD +
20mV
V
Address inputs, RAS#,
CAS#, WE#, S#,
CKE, ODT, BA,
CK, CK#
–16
0
16
µA
DM
–2
0
2
DQ, DQS,
DQS#
–5
0
5
µA
VREF supply leakage current; VREFDQ = VDD/2 or
VREFCA = VDD/2 (All other pins not under test = 0V)
–8
0
8
µA
TA
Module ambient operating temperature
0
–
70
°C
3, 4
TC
DDR3 SDRAM component case operating temperature
0
–
95
°C
3, 4 , 5
IVTT
Termination reference current from VTT
VTT
Termination reference voltage (DC) – command/
address bus
II
IOZ
IVREF
Input leakage current;
Any input 0V ≤ VIN ≤ VDD; VREF
input 0V ≤ VIN ≤ 0.95V (All other
pins not under test = 0V)
Output leakage current;
0V ≤ VOUT ≤ VDD; DQ and ODT are
disabled; ODT is HIGH
Notes:
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2
1. Module is backward-compatible with 1.5V operation. Refer to device specification for
details and operation guidance.
2. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
3. TA and TC are simultaneous requirements.
4. For further information, refer to technical note TN-00-08: “Thermal Applications,”
available on Micron’s Web site.
5. The refresh rate is required to double when 85°C < TC ≤ 95°C.
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s web site. Module speed grades correlate with component speed grades, as shown below.
Table 11: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G1
-093
-1G9
-107
-1G6
-125
-1G4
-15E
-1G1
-187E
-1G0
-187
-80C
-25E
-80B
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
IDD Specifications
IDD Specifications
Table 12: DDR3 IDD Specifications and Conditions – 4GB (Die Revision E)
Values are for the MT41K512M8 DDR3L-RS SDRAM only and are computed from values specified in the 1.35V DDR3L-RS
4Gb (512 Meg x 8) component data sheet
Parameter
Symbol
1600
1333
Units
IDD01
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
1
376
mA
528
469
mA
1
96
96
mA
Precharge power-down current: Fast exit
IDD2P1
1
240
208
mA
Precharge quiet standby current
IDD2Q1
216
192
mA
Precharge standby current
IDD2N1
208
192
mA
1
272
240
mA
Precharge power-down current: Slow exit
IDD1
440
IDD2P0
Precharge standby ODT current
IDD2NT
Active power-down current
IDD3P
1
264
240
mA
Active standby current
IDD3N1
280
256
mA
Burst read operating current
IDD4R1
1192
1056
mA
944
824
mA
1848
1792
mA
28
28
mA
1
Burst write operating current
IDD4W
1
Refresh current
IDD5
Self refresh temperature current
IDD62
Self refresh temperature current
3
29.6
29.6
mA
4
56
56
mA
IDD6
Self refresh temperature current
IDD6
5
Self refresh temperature current
IDD6
68
68
mA
Self refresh temperature current – Extended Temperature
IDD6ET6
112
112
mA
Self refresh temperature current – Extended Temperature
7
IDD6ET
All banks interleaved read current
144
144
mA
1
1704
1456
mA
1
112
112
mA
IDD7
Reset current
IDD8
Notes:
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1.
2.
3.
4.
5.
6.
7.
TC = +80°C, SRT and ASR disabled (MAX)
TC ≤ TA, SRT disabled ASR enabled (TYP)
TC ≤ +45°C, SRT disabled ASR enabled (TYP)
TC = +80°C, SRT disabled ASR enabled (TYP)
+45°C < TC ≤ +80°C, SRT disabled ASR enabled (MAX)
TC = +95°C, SRT disabled ASR enabled (TYP)
+85°C < TC ≤ +95°C, SRT disabled ASR enabled (MAX)
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Serial Presence-Detect EEPROM
Serial Presence-Detect EEPROM
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 13: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VDDSPD
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
3.0
3.6
V
VIL
–0.45
VDDSPD x 0.3
V
Input high voltage: Logic 1; All inputs
VIH
VDDSPD x 0.7
VDDSPD + 1.0
V
Output low voltage: IOUT = 3mA
VOL
–
0.4
V
Input leakage current: VIN = GND to VDD
ILI
0.1
2.0
µA
Output leakage current: VOUT = GND to VDD
ILO
0.05
2.0
µA
Supply voltage
Input low voltage: Logic 0; All inputs
Table 14: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
tSCL
10
400
kHz
Clock frequency
Notes
Clock pulse width HIGH time
tHIGH
0.6
–
µs
Clock pulse width LOW time
tLOW
1.3
–
µs
SDA rise time
tR
–
300
µs
1
SDA fall time
tF
20
300
ns
1
Data-in setup time
tSU:DAT
100
–
ns
Data-in hold time
tHD:DI
0
–
µs
Data-out hold time
tHD:DAT
200
900
ns
Data out access time from SCL LOW
tAA:DAT
0.2
0.9
µs
2
Start condition setup time
tSU:STA
0.6
–
µs
3
Start condition hold time
tHD:STA
0.6
–
µs
Stop condition setup time
tSU:STO
0.6
–
µs
tBUF
1.3
–
µs
tW
–
10
ms
Time the bus must be free before a new transition can
start
WRITE time
Notes:
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1. Guaranteed by design and characterization, not necessarily tested.
2. To avoid spurious start and stop conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA.
3. For a restart condition, or following a WRITE cycle.
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Module Dimensions
Module Dimensions
Figure 4: 204-Pin DDR3 SODIMM, Standard Layout, PCB 1491 (HSZ)
PCB 1491, front side populated
2.45 (0.96)
MAX
Front view
67.75 (2.667)
67.45 (2.656)
2.0 (0.079) R
(2X)
U1
U2
U4
U3
U5
30.15 (1.187)
29.85 (1.175)
1.8 (0.071) D
(2X)
U6
U7
U8
U9
20.0 (0.787)
TYP
6.0 (0.236)
TYP
Pin 1
2.0 (0.079)
TYP
1.0 (0.039)
TYP
0.45 (0.018)
TYP
0.6 (0.024)
TYP
Pin 203
1.10 (0.043)
0.90 (0.035)
63.6 (2.504)
TYP
Back view
0.6 (0.024) x 45° 3X
No components this side of module
4.0 (0.157)
TYP
1.0 (0.039) R
2.55 (0.10)
TYP
3.0 (0.12)
TYP
Pin 204
39.0 (1.535)
TYP
Pin 2
21.0 (0.827)
TYP
24.8 (0.976)
TYP
Notes:
PDF: 09005aef84fc0fd3
mtf8c512x64hz_g0_h0.pdf - Rev. D 5/13 EN
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
4GB (x64, SR) 204-Pin DDR3L-RS SODIMM
Module Dimensions
Figure 5: 204-Pin DDR3 SODIMM, Reverse Layout, PCB 1492 (HRZ)
PCB 1492, back side populated
Front view
2.45 (0.96)
MAX
67.75 (2.667)
67.45 (2.656)
2.0 (0.079) R
(2X)
30.15 (1.187)
29.85 (1.175)
No components this side of module
1.8 (0.071) D
(2X)
20.0 (0.787)
TYP
6.0 (0.236)
TYP
Pin 1
2.0 (0.079)
TYP
1.0 (0.039)
TYP
0.45 (0.018)
TYP
0.6 (0.024)
TYP
Pin 203
1.10 (0.043)
0.90 (0.035)
63.6 (2.504)
TYP
Back view
0.6 (0.024) x 45° 3X
U1
4.0 (0.157)
TYP
U2
U3
U4
U5
U6
U7
U8
U9
1.0 (0.039) R
3.0 (0.12)
TYP
Pin 204
39.0 (1.535)
TYP
2.55 (0.10)
TYP
Pin 2
21.0 (0.827)
TYP
24.8 (0.976)
TYP
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef84fc0fd3
mtf8c512x64hz_g0_h0.pdf - Rev. D 5/13 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.