16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM

16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Features
DDR4 SDRAM RDIMM
MTA36ASF2G72PZ – 16GB
Features
Figure 1: 284-Pin RDIMM (MO-309, R/C-B)
• DDR4 functionality and operations supported as
defined in the component data sheet
• 284-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC4-2400, PC4-2133, or
PC4-1866
• 16GB (2 Gig x 72)
• VDD = 1.2V ±60mV
• VPP = 2.5V ±125mV
• VDDSPD = 3.0–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die V REFDQ generation and calibration
• Dual-rank
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Module height: 31.25mm (1.23in)
Options
Marking
• Operating temperature
– Commercial (0°C ≤ T A ≤ +95°C)
• Package
– 284-pin DIMM (halogen-free)
• Frequency/CAS latency
– 0.83ns @ CL = 16 (DDR4-2400)
– 0.93ns @ CL = 15 (DDR4-2133)
– 1.07ns @ CL = 13 (DDR4-1866)
None
Z
-2G4
-2G1
-1G9
Table 1: Key Timing Parameters
Speed
Grade
Data Rate (MT/s)
Industry
Nomenclature CL = 18 CL = 16 CL = 15 CL = 14 CL = 13 CL = 12 CL = 11 CL = 9
tRCD
tRP
tRC
(ns)
(ns)
(ns)
-2G4
PC4-2400
2400
2133
2133
1866
1866
1600
1600
1333
13.32 13.32 45.32
-2G1
PC4-2133
–
2133
2133
1866
1866
1600
1600
1333
13.5
13.5
46.5
-1G9
PC4-1866
–
–
–
1866
1866
1600
1600
1333
13.5
13.5
47.5
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Features
Table 2: Addressing
Parameter
16GB
Row address
64K A[15:0]
Column address
1K A[9:0]
Device bank group address
4 BG[1:0]
Device bank address per group
4 BA[1:0]
Device configuration
4Gb (1 Gig x 4), 16 banks
Module rank address
2 CS_n[1:0]
Table 3: Part Numbers and Timing Parameters – 16GB Modules
Base device: MT40A1G4,1 4Gb DDR4 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MTA36ASF2G72PZ-2G4__
16GB
2 Gig x 72
19.2 GB/s
0.83ns/2400 MT/s
16-16-16
MTA36ASF2G72PZ-2G1__
16GB
2 Gig x 72
17.0 GB/s
0.93ns/2133 MT/s
15-15-15
MTA36ASF2G72PZ-1G9__
16GB
2 Gig x 72
14.9 GB/s
1.07ns/1866 MT/s
13-13-13
Notes:
1. The data sheet for the base device can be found on Micron’s web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MTA36ASF2G72PZ-2G1A1.
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
284-Pin DDR4 RDIMM Front
284-Pin DDR4 RDIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
1
VSS
37
DQ24
73
CK0_t
109
DQS14_t
143
VREFCA
179
VSS
215
CK1_t
251
VSS
2
DQ4
38
VSS
74
CK0_c
110
DQS14_c
144
VSS
180
DQ25
216
CK1_c
252
DQS5_c
3
VSS
39
DQS12_t
75
VDD
111
VSS
145
DQ5
181
VSS
217
VDD
253
DQS5_t
4
DQ0
40
DQS12-c
76
VTT
112
DQ46
146
VSS
182
DQS3_c
218
VTT
254
VSS
5
VSS
41
VSS
77
EVENT_n
113
VSS
147
DQ1
183
DQS3_t
219
PARITY
255
DQ47
6
DQS9_t
42
DQ30
78
A0
114
DQ42
148
VSS
184
VSS
220
VDD
256
VSS
7
DQS09_c
43
VSS
79
VDD
115
VSS
149
DQS0_c
185
DQ31
221
BA1
257
DQ43
8
VSS
44
DQ26
80
BA0
116
DQ52
150
DQS0_t
186
VSS
222
A10_AP
258
VSS
9
DQ6
45
VSS
81
RAS_n/
A16
117
VSS
151
VSS
187
DQ27
223
VDD
259
DQ53
10
VSS
46
CB4
82
VDD
118
DQ48
152
DQ7
188
VSS
224
NC
260
VSS
11
DQ2
47
VSS
83
S0_n
119
VSS
153
VSS
189
CB5
225
WE_n/
A14
261
DQ53
12
VSS
48
CB0
84
VDD
120
DQS15_t
154
DQ3
190
VSS
226
VDD
262
VSS
13
DQ12
49
DQS8
85
CAS_n/
A15
121
DQS15_c
155
VSS
191
CB1
227
NC
263
DQ49
14
VSS
50
DQS17_t
86
ODT0
122
VSS
156
DQ13
192
VSS
228
VDD
264
VSS
15
DQ8
51
DQS17_c
87
VDD
123
DQ54
157
VSS
193
DQS8_c
229
A13
265
DQS6_c
16
VSS
52
VSS
88
S1_n
124
VSS
158
DQ9
194
DQS8_t
230
VDD
266
DQS6_t
17
DQS10_t
53
CB6
89
VDD
125
DQ50
159
VSS
195
VSS
231
A17
267
VSS
18
DQS10_c
54
VSS
90
ODT1
126
VSS
160
DQS1_c
196
CB7
232
NF
268
DQ55
19
VSS
55
CB2
91
VDD
127
DQ60
161
DQS1_t
197
VSS
233
VDD
269
VSS
20
DQ14
56
VSS
92
NF
128
VSS
162
VSS
198
CB3
234
NF
270
DQ51
21
VSS
57
RESET_n
93
VSS
129
DQ56
163
DQ15
199
VSS
235
SA2
271
VSS
22
DQ10
58
VDD
94
DQ36
130
VSS
164
VSS
200
CKE1
236
VSS
272
DQ61
23
VSS
59
CKE0
95
VSS
131
DQS16_t
165
DQ11
201
VDD
237
DQ37
273
VSS
24
DQ20
60
VDD
96
DQ32
132
DQS16_c
166
VSS
202
NC
238
VSS
274
DQS7_c
25
VSS
61
ACT_n
97
VSS
133
VSS
167
DQ21
203
VDD
239
DQ33
275
DQS7_t
26
DQ16
62
BG0
98
DQS13_t
134
DQ62
168
VSS
204
BG1
240
VSS
276
VSS
27
VSS
63
VDD
99
DQS13_c
135
VSS
169
DQ17
205
ALERT_n
241
DQS4_c
277
DQ63
28
DQS11_t
64
A12
100
VSS
136
DQ58
170
VSS
206
VDD
242
DQS4_t
278
VSS
29
DQS11_c
65
A9
101
DQ38
137
VSS
171
DQS2_c
207
A11
243
VSS
279
DQ59
30
VSS
66
VDD
102
Vss
138
SA0
172
DQS2_t
208
A7
244
DQ39
280
VSS
31
DQ22
67
A8
103
DQ34
139
SA1
173
VSS
209
VDD
245
VSS
281
VDDSPD
32
VSS
68
A6
104
VSS
140
SCL
174
DQ23
210
A5
246
DQ35
282
SDA
33
DQ18
69
VDD
105
DQ44
141
VPP
175
VSS
211
A4
247
VSS
283
VPP
34
VSS
70
A3
106
VSS
142
NF
176
DQ19
212
VDD
248
DQ45
284
NF
35
DQ28
71
A1
107
DQ40
177
VSS
213
A2
249
VSS
36
VSS
72
VDD
108
VSS
178
DQ19
214
VDD
250
DQ41
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asf36c2gx72pz.pdf - Rev. C 05/13 EN
3
Symbol
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR4
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 5: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVATE commands and the column
address for READ/WRITE commands to select one location out of the memory array in
the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have
additional functions; see individual entries in this table). The address inputs also provide the op-code during the MODE REGISTER SET command.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine
whether auto precharge should be performed to the accessed bank after a READ or
WRITE operation (HIGH = Auto precharge; LOW = No auto precharge). A10 is sampled
during a PRECHARGE command to determine whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by the bank group and bank addresses.
A12/BC_n
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if
burst chop (on-the-fly) will be performed. (HIGH = No burst chop; LOW = Burst-chopped). See the Command Truth Table.
ACT_n
Input
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with
CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row
address inputs for the ACTIVATE command. When ACT_n is HIGH (along with CS_n
LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal
commands that use the RAS_n, CAS_n, and WE_n signals. See the Command Truth Table.
BAx
Input
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determine which mode
register is to be accessed during a MODE REGISTER SET command.
BGx
Input
Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determine which mode
register is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in
the x4 and x8 configurations. BG1 is not used in the x16 configuration.
C0/CKE1
C1/CS1_n
C2/ODT1
Input
Stack address inputs: These inputs are used only when devices are stacked, i.e., 2H,
4H, and 8H stacks for x4 and x8 configurations. These pins are not used in the x16
configuration. DDR4 supports a traditional DDP package, which uses these three signals to control the second die (CS1_n, CKE1, ODT1). DDR4 is not anticipated to support a traditional QDP package. For all other stack configurations, such as a 4H or 8H,
it is assumed to be a single-load (master/slave)-type configuration where C0, C1, and
C2 are used as chip ID selects in conjunction with a single CS_n, CKE, and ODT.
CK_t
CK_c
Input
Clock: Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.
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asf36c2gx72pz.pdf - Rev. C 05/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
Type
Description
CKEx
Input
Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power-on and initialization sequence, it must be maintained
during all operations (including SELF REFRESH). CKE must be held HIGH throughout
read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE)
are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during self refresh.
CS_n
Input
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides
external rank selection on systems with multiple ranks. CS_n is considered part of the
command code.
DM_n
UDM_n
LDM_n
Input
Input data mask: DM_n is an input mask signal for write data. Input data is masked
when DM is sampled LOW coincident with that input data during a write access. DM
is sampled on both edges of DQS. DM is not supported in x4 configurations. The
UDM_n and LDM_n pins are used in the x16 configuration, UDM_n is associated with
DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register settings. See Data Mask (DM).
ODT
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR4 SDRAM. When ODT is enabled, on-die termination (RTT) is applied only to
each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for x4, x8 configurations (when the TDQS function is enabled via mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, UDM_n, and
LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to
disable RTT.
PAR
Input
Parity for command and address: This function can be enabled or disabled via the
mode register. When enabled, the PARITY signal covers all command and address inputs, including RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0],
BG[1:0], C0/A18, C1/A19, and C2/A20. Control pins CS_n, CKE, and ODT are not covered by the PARITY signal. Unused address pins that are density- and configurationspecific should be treated internally as 0s by the DRAM parity logic.
RAS_n/A16
CAS_n/A15
WE_n/A14
Input
Command inputs: RAS_n/A16 , CAS_n/A15, and WE_n/A14 (along with CS_n and
ACT_n) define the command and/or address being entered. See the ACT_n description
in this table.
RESET_n
Input
Active LOW asynchronous reset: Reset is active when RESET_n is LOW; inactive
when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a
CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD, i.e., 960mV
for DC HIGH; 240mV for DC LOW.
TEN
Input
Connectivity test mode: Active when TEN is HIGH; inactive when TEN is LOW. TEN
must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC HIGH
and LOW at 80% and 20% of VDD (960mV for DC HIGH; 240mV for DC LOW).
DQ
I/O
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and
DQ[15:0] for the x4, x8, and x16 configurations, respectively. If CRC is enabled via the
mode register, then CRC code is added at the end of the data burst. Either one or all
of DQ0, DQ1, DQ2, or DQ3 is/are used for monitoring of internal VREF level during test
via mode register setting MR[4] A[4] = HIGH; training times change when enabled.
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asf36c2gx72pz.pdf - Rev. C 05/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
Type
Description
DBI_n
UDBI_n
LDBI_n
I/O
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data
bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The
DBI feature is not supported on x4 configurations. DBI can be configured for both
READ (output) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See
data bus inversion (DBI).
DQS_t
DQS_c
DQSU_t
DQSU_c
DQSL_t
DQSL_c
I/O
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with
READ data, centered-aligned with WRITE data. For x16 configurations, DQSL corresponds to the data on DQ[7:0]; DQSU corresponds to the data on DQ[15:8]. For the x4
and x8 configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0] respectively. DDR4 SDRAM support a differential data strobe only and do not support a single-ended data strobe.
ALERT_n
Output
Alert output: This signal allows the SDRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include command/address
parity errors and CRC data errors when either of those functions is enabled in the
mode register.
TDQS_t
TDQS_c
Output
Termination data strobe: TDQS_t and TDQS_c are applicable for x8 SDRAM only.
When enabled via the mode register, the SDRAM enable the same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS
function is disabled via the mode register, the DM/TDQS_t pin provides the data mask
(DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in
the mode register for both the x4 and x16 configurations. The DM function is supported only in x8 and x16 configurations.
VDD
Supply
Power supply: 1.2V ±0.060V
VDDQ
Supply
DQ power supply: 1.2V ±0.060V
VPP
Supply
DRAM activating power supply: 2.5V -0.125V / +0.250V
VREFCA
Supply
Reference voltage for control, command, and address pins.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground.
ZQ
Reference
RFU
–
Reserved for future use.
NC
–
No connect: No internal electrical connection is present.
NF
–
No function: Internal connection may be present but has no function.
PDF: 09005aef84f8c349
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Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor
(RZQ), which is tied to VSSQ.
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
DQ Map
DQ Map
Table 6: Component-to-Module DQ Map Front
Component
Reference
Number
Component
DQ
U1
U2
U3
U4
U5
U7
U8
U9
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asf36c2gx72pz.pdf - Rev. C 05/13 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
3
154
U11
0
3
154
1
0
4
1
0
4
2
2
11
2
2
11
3
1
147
3
1
147
0
14
20
0
14
20
1
13
156
1
13
156
2
15
163
2
15
163
3
12
13
3
12
13
0
22
31
0
22
31
1
21
167
1
21
167
2
23
174
2
23
174
3
20
24
3
20
24
0
30
42
0
30
42
1
28
35
1
28
35
2
31
185
2
31
185
3
29
178
3
29
178
0
CB3
198
0
CB3
198
1
CB0
48
1
CB0
48
2
CB2
55
2
CB2
55
3
CB1
191
3
CB1
191
0
38
101
0
38
101
1
37
237
1
37
237
2
39
244
2
39
244
3
36
94
3
36
94
0
43
257
0
43
257
1
41
250
1
41
250
2
42
114
2
42
114
3
40
107
3
40
107
0
55
266
0
55
266
1
52
116
1
52
116
2
54
123
2
54
123
3
53
259
3
53
259
U12
U13
U14
U15
U17
U18
U19
7
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© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
DQ Map
Table 6: Component-to-Module DQ Map Front (Continued)
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
U10
0
62
134
U20
0
62
134
1
60
127
1
60
127
2
63
277
2
63
277
3
61
270
3
61
270
Table 7: Component-to-Module DQ Map Back
Component
Reference
Number
Component
DQ
U21
U22
U23
U24
U25
U26
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
60
127
U30
0
56
129
1
62
134
1
58
136
2
61
270
2
57
272
3
63
277
3
59
279
0
52
116
0
48
118
1
55
266
1
51
268
2
53
259
2
49
261
3
54
123
3
50
125
0
41
250
0
45
248
1
43
257
1
46
112
2
40
107
2
44
105
3
42
114
3
47
255
0
37
237
0
34
103
1
38
101
1
32
96
2
36
94
2
35
246
3
39
244
3
33
239
0
CB0
48
0
CB6
53
1
CB3
198
1
CB5
189
2
CB1
191
2
CB7
196
3
CB2
55
3
CB4
46
0
28
35
0
25
180
1
30
42
1
27
187
2
29
178
2
24
37
3
31
185
3
26
44
U31
U32
U33
U34
U35
8
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© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
DQ Map
Table 7: Component-to-Module DQ Map Back (Continued)
Component
Reference
Number
Component
DQ
U27
U28
U29
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
21
167
U36
0
18
33
1
22
31
1
17
169
2
20
24
2
19
176
3
23
174
3
16
26
0
13
156
0
9
158
1
14
20
1
11
165
2
12
13
2
8
15
3
15
163
3
10
22
0
0
4
0
5
145
1
3
154
1
6
9
2
1
147
2
4
2
3
2
11
3
7
152
U37
U38
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
A/B-CS0_n
A/B-CS1_n
DQS9_t
DQS9_c
DQS0_t
DQS0_c
CS_n DQS_t DQS_c
DQ0
DQ1
DQ2
DQ3
VSS
DQS1_t
DQS1_c
DQ
DQ
DQ
DQ
ZQ
DQ8
DQ9
DQ10
DQ11
VSS
DQ
DQ
DQ
DQ
ZQ
U1
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U29
ZQ
VSS
CS_n DQS_t DQS_c
U12
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
VSS
DQS3_t
DQS3_c
ZQ
VSS
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
U13
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U36
ZQ
VSS
CS_n DQS_t DQS_c
DQ24
DQ25
DQ26
DQ27
VSS
DQS8_t
DQS8_c
DQ
DQ
DQ
DQ
ZQ
CB0
CB1
CB2
CB3
VSS
DQ
DQ
DQ
DQ
ZQ
U14
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
VSS
CS_n DQS_t DQS_c
U5
U25
DQS5_t
DQS5_c
DQ40
DQ41
DQ42
DQ43
VSS
VSS
DQ
DQ
DQ
DQ
ZQ
U17
U33
VSS
DQ
DQ
DQ
DQ
ZQ
U8
DQ
DQ
DQ
DQ
ZQ
VSS
DQ48
DQ49
DQ50
DQ51
VSS
DQS7_t
DQS7_c
DQ56
DQ57
DQ58
DQ59
VSS
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
U19
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
VSS
DQ
DQ
DQ
DQ
ZQ
U20
U2
DQ60
DQ61
DQ62
DQ63
VSS
U30
ZQ
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
ZQ
VSS
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
U3
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U4
CS0_n
CS1_n
BA[1:0]
BG[1:0]
ACT_n
A[17, 13:0]
RAS_n/A16
CAS_n/A15
WE_n/A14
CKE0
CKE1
ODT0
ODT1
PAR_IN
ALERT_CONN
&
DDR4 SDRAM
ZQ
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DDR4 SDRAM
VSS
U26
CK1_t
CK1_c
ZQ
U15
Rank 0: U1–U5, U7–U15, U17–U20
Rank 1: U21–38
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
Command, control, address, and clock line terminations:
U34
ZQ
VSS
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
CK[3:0]_t
CK[3:0]_c
RESET_CONN
VSS
DQ
DQ
DQ
DQ
ZQ
P
L
L
CK0_t
CK0_c
ZQ
A/B-CS0_n: Rank 0
A/B-CS1_n: Rank 1
A/B-BA[1:0]: DDR4 SDRAM
A/B-BG[1:0]: DDR4 SDRAM
A/B-ACT_n: DDR4 SDRAM
A/B-A[17,13:0]: DDR4 SDRAM
A/B-RAS_n/A16: DDR4 SDRAM
A/B-CAS_n/A15: DDR4 SDRAM
A/B-WE_n/A14: DDR4 SDRAM
A/B-CKE0: Rank 0
A/B-CKE1: Rank 1
A/B-ODT0: Rank 0
A/B-ODT1: Rank 1
A/B-PAR: DDR4 SDRAM
ALERT_DRAM: DDR4 SDRAM
R
E
G
I
S
T
E
R
U27
VSS
CS_n DQS_t DQS_c
U7
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
A/B-CS_n[1:0], A/B-BA[1:0]A/B-BG[1:0],
A/B-ACT_n, A/B-A[17, 13:0], A/B-RAS_n/A16,
A/B-CAS_n/A15, A/B-WE_n/A14,
A/B-CKE[1:0], A/B-ODT[1:0]
U24
DDR4
SDRAM
VTT
DDR4
SDRAM
CK[3:0]_t
CK[3:0]_c
ZQ
VDD
VSS
DQ
DQ
DQ
DQ
ZQ
U18
U6
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U32
SCL
ZQ
DQ
DQ
DQ
DQ
ZQ
U9
U22
ZQ
VSS
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
U10
VDDSPD
SPD EEPROM/
Temp Sensor
VDD
DDR4 SDRAM
VTT
Control, command and
address termination
VREFCA
U21
ZQ
SDA
A1 A2
SA0 SA1 SA2
EVENT#
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
SPD EEPROM/
Temp sensor
EVT A0
VSS
CS_n DQS_t DQS_c
DDR4 SDRAM
VPP
DDR4 SDRAM
VSS
DDR4 SDRAM
VSS
VSS
Note:
U28
DQS16_t
DQS16_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQS15_t
DQS15_c
DQ52
DQ53
DQ54
DQ55
VSS
U31
ZQ
CS_n DQS_t DQS_c
VSS
CS_n DQS_t DQS_c
DQS14_t
DQS14_c
DQ44
DQ45
DQ46
DQ47
VSS
U23
DQS6_t
DQS6_c
ZQ
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
U38
DQS13_t
DQS13_c
DQ36
DQ37
DQ38
DQ39
VSS
ZQ
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U11
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQS17_t
DQS17_c
CB4
CB5
CB6
CB7
VSS
ZQ
CS_n DQS_t DQS_c
DQ20
DQ21
DQ22
DQ23
VSS
DQS12_t
DQS12_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
CS_n DQS_t DQS_c
DQS11_t
DQS11_c
DQ28
DQ29
DQ30
DQ31
VSS
U35
DQS4_t
DQS4_c
DQ32
DQ33
DQ34
DQ35
VSS
DQ12
DQ13
DQ14
DQ15
VSS
U37
DQS2_t
DQS2_c
DQ4
DQ5
DQ6
DQ7
VSS
DQS10_t
DQS10_c
U16
CS_n DQS_t DQS_c
1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
10
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© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
General Description
General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with 2 or 4 internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
have 4 internal bank groups consisting of 4 memory banks each, providing a total of 16
banks. Sixteen-bit-wide DDR4 SDRAM has 2 internal bank groups consisting of 4 memory banks each, providing a total of 8 banks. DDR4 SDRAM modules benefit from DDR4
SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single READ or WRITE operation for the
DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR4.
Registering Clock Driver Operation
Registered DDR4 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 Register Specification.
The register section of the registering clock driver latches command and address input
signals on the rising clock edge. The PLL section of the registering clock driver receives
and redrives the differential clock signals (CK, CK#) to the DDR4 SDRAM devices. The
registering clock driver(s) reduces clock, control, command, and address signal loading
by isolating DRAM from the system controller.
Parity Operations
The registering clock driver includes a parity-checking function that can be enabled or
disabled in control word RC0E. When parity checking is enabled, the registering clock
driver forwards sampled commands to the SDRAM only when no parity error has occurred. If the parity error function has been disabled, the registering clock driver forwards sampled commands to the DRAM regardless of whether a parity error has occurred. Parity is also checked during control word WRITE operations unless parity checking is disabled.
The registering clock driver receives a parity bit at the DPAR input from the memory
controller and compares it with the data received on the qualified CA inputs and indicates on its open-drain ALERT_n pin whether a parity error has occurred. Valid parity is
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
11
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© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Registering Clock Driver Operation
defined as an even number of 1s across the address and command inputs qualified by
at least one of the DCS[n:0] signals being LOW.
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
12
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© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Notes
VDD
VDD supply voltage relative to VSS
–0.4
1.5
V
1
VDDQ
VDDQ supply voltage relative to VSS
–0.4
1.5
V
1
VPP
Voltage on VPP pin relative to Vss
-0.4
3.0
V
3
VIN, VOUT Voltage on any pin relative to VSS
–0.4
1.5
V
Table 9: Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units Notes
VDD
VDD supply voltage
1.14
1.2
1.26
V
2
VPP
DRAM Activating Power Supply
2.375
2.5
2.750
V
3
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
0.49 × VDD 20mV
0.5 × VDD
0.51 × VDD +
20mV
V
4
–
–
–
µA
5
–10
0
10
µA
–36
0
72
µA
0
–
85
°C
7
>85
–
95
°C
6, 7
VREFCA(DC) Input reference voltage command/
address bus
VTT
Termination reference voltage (DC) –
command/address bus
II
Input leakage current; Any input
0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN
≤ 0.75V (All other pins not under
test = 0V)
Address inputs,
RAS_n, CAS_n,
WE_n, CS_n,
CKE, ODT, BA,
BG, CK_t, CK_c
IOZ
Output leakage current; 0V ≤ VOUT
≤ VDD; DQ and ODT are disabled;
ODT is HIGH
DQ, DQS_t,
DQS_c,
ALERT_n
IVREF
VREF supply leakage current; VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V)
TOPER
Normal operating temperature range
Extended temperature operating range (optional)
Notes:
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
1. VDD and VDDQ must be within 300mV of each other at all times; VREFCA must not be
greater than 0.6 x VDDQ or less than 500mV; VREF may be less than or equal to 300mV.
2. VDDQ tracks with VDD; VDDQ and VDD are tied together.
3. VPP must be greater than or equal to VDD at all times.
4. VTT termination voltages in excess of specification limit will adversely affect command
and address signals' voltage margins, and reduce timing margins.
5. Inputs are terminated to VDD/2. Input current is dependent on terminating resistance selected in register.
6. The refresh rate is required to double when 85°C < TOPER ≤ 95°C.
7. For additional information, refer to technical note TN-00-08: "Thermal Applications"
available on Micron's web site.
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR4 component data sheets.
Component specifications are available on Micron’s web site. Module speed grades correlate with component speed grades, as shown below.
Table 10: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G4
-083E
-2G1
-093E
-1G9
-107E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
IDD Specifications
IDD Specifications
Table 11: DDR4 IDD Specifications and Conditions – 16GB (Die Revision A)
Values are for the MT40A1G4 DDR4 SDRAM only and are computed from values specified in the 4Gb (1 Gig x 4) component data sheet
Parameter
Symbol
2400
2133
1866
Units
IDD01
One bank ACTIVATE-PRECHARGE current
One bank ACTIVATE-PRECHARGE, wordline boost, IPP current
One bank ACTIVATE-READ-PRECHARGE current
1152
1116
1080
mA
1
126
126
126
mA
1
IPP0
IDD1
1350
1314
1278
mA
Precharge standby current
IDD2N
2
1224
1152
1080
mA
Precharge standby ODT current
IDD2NT1
1224
1170
1116
mA
2
576
576
576
mA
2
900
900
900
mA
2
Precharge power-down current
IDD2P
Precharge quite standby current
IDD2Q
Active standby current
IDD3N
1404
1332
1260
mA
Active standby IPP current
IPP3N2
108
108
108
mA
2
720
720
720
mA
1
2898
2718
2538
mA
Active power-down current
IDD3P
Burst read current
IDD4R
1
Burst read IDDQ current
IDDQ4R
936
864
792
mA
Burst write current
IDD4W1
3168
2808
2538
mA
1
2178
2178
2178
mA
1
270
270
270
mA
Self refresh current: Normal temperature range (0–85°C)
IDD6N
2
684
684
684
mA
Self refresh current: Extended temperature range (0–95°C)
IDD6E2
828
828
828
mA
Self refresh current: Reduced temperature range (0–45°C)
IDD6R2
324
324
324
mA
2
Burst refresh current (1x REF)
IDD5B
Burst refresh IPP current (1 x REF)
IPP5B
Auto self refresh current (25°C)
IDD6A
216
216
216
mA
Auto self refresh current (45°C)
IDD6A
2
324
324
324
mA
Auto self refresh current (75°C)
IDD6A2
432
432
432
mA
1
4068
3618
3168
mA
1
306
270
234
mA
2
648
648
648
mA
Bank interleave read current
IDD7
Bank interleave read IPP current
IPP7
Maximum power-down current
Notes:
PDF: 09005aef84f8c349
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IDD8
1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Registering Clock Driver Specifications
Registering Clock Driver Specifications
Table 12: Registering Clock Driver Electrical Characteristics
SSTE32882 devices or equivalent
Parameter
Symbol
Pins
Min
Nom
Max
Units
DC supply voltage
VDD
–
1.425
1.5
1.575
V
DC reference voltage
VREF
–
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
DC termination
voltage
VTT
–
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
AC high-level input
voltage
VIH(AC)
Control, command,
address
VREF + 175mV
–
VDD + 400mV
V
AC low-level input
voltage
VIL(AC)
Control, command,
address
–0.4
–
VREF - 175mV
V
DC high-level input
voltage
VIH(DC)
Control, command,
address
VREF + 100mV
–
VDD + 0.4
V
DC low-level input
voltage
VIL(DC)
Control, command,
address
–0.4
–
VREF - 100mV
V
High-level input
voltage
VIH(CMOS)
RESET#, MIRROR
0.65 × VDD
–
VDD
V
Low-level input
voltage
VIL(CMOS)
RESET#, MIRROR
0
–
0.35 × VDD
V
Differential input
crosspoint voltage
range
VIX(AC)
CK, CK#, FBIN, FBIN#
0.5 × VDD - 175mV
0.5 × VDD
0.5 × VDD + 175mV
V
Differential input
voltage
VID(AC)
CK, CK#
350
–
VDD + TBD
mV
High-level output
current
IOH
Err_Out#
–
–
TBD
mA
Low-level output
current
IOL
Err_Out#
TBD
–
TBD
mA
Note:
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
1. Timing and switching specifications for the register listed are critical for proper operation of the DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module.
16
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© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC
JC-42.4 EE1004 and TSE2004 device specification for complete details.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 13: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
2.2
3.6
V
Input low voltage: Logic 0; All inputs
VIL
–0.5
VDDSPD * 0.3
V
Input high voltage: Logic 1; All inputs
VIH
VDDSPD * 0.7
VDDSPD + 0.5
V
Output low voltage: 3 mA sink current VDDSPD >2V
Supply voltage
VOL
–
0.4
V
Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD
ILI
–
±5
µA
Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in Hi-Z
ILO
–
±5
µA
Table 14: Temperature Sensor and EEPROM Serial Interface Timing
Parameter/Condition
Symbol
Min
Max
Units
tSCL
10
1000
kHz
Clock pulse width HIGH time
tHIGH
260
–
ns
Clock pulse width LOW time
tLOW
500
–
ns
tTIMEOUT
25
35
ms
SDA rise time
tR
–
120
ns
SDA fall time
tF
–
120
ns
Data-in setup time
tSU:DAT
50
–
ns
Data-in hold time
tHD:DI
0
–
ns
Data out hold time
tHD:DAT
0
350
ns
Start condition setup time
tSU:STA
260
–
ns
Start condition hold time
tHD:STA
260
–
ns
Stop condition setup time
tSU:STO
260
–
ns
tBUF
500
–
ns
tW
–
5
ms
Clock frequency
Detect Clock Low Timeout
Time the bus must be free before a new transition can start
WRITE time
Warm power cycle time off
Time from power on to first command
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
tPOFF
1
–
ms
tINIT
10
–
ms
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
EVENT# Pin
The temperature sensor also adds the EVENT# pin. This is an open-drain output that
requires a pull-up to VDDSPD. Not used by the SPD EEPROM, EVENT# is a temperature
sensor output used to flag critical events that can be set up in the sensor’s configuration
registers.
EVENT# has three defined modes of operation: interrupt mode, comparator mode, and
TCRIT Only.
In Interrupt Mode the EVENT# pin will remain asserted until it is released by writing a
"1" to the Clear Event bit in the Status Register.
In Comparator Mode the EVENT# pin will clear itself when the error condition is removed. This mode is always used when the temperature is compared against the TCRIT
limit.
In TCRIT Only Mode the EVENT# pin will only be asserted if the measured temperature
exceeds the TCRIT limit. It will remain asserted until the temperature drops below the
TCRIT Limits minus the TCRIT Hysteresis.
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 284-Pin DDR4 RDIMM
Module Dimensions
Module Dimensions
Figure 3: 284-Pin DDR4 RDIMM
Front view
3.9 (0.153)
MAX
133.50 (5.256)
133.20 (5.244)
U1
0.75 (0.03) R
(8X)
U2
U3
U4
U5
U6
U7
U8
U9
U10
31.40 (1.236)
31.10 (1.224)
U16
U11
2.50 (0.098) D
(2X)
U12
U13
U14
U15
U17
U18
U19
U20
16.1 (0.63)
TYP
4.8 (0.189) TYP
9.5 (0.374)
TYP
0.75 (0.030) R
Pin 1
2.20 (0.087) TYP
0.85 (0.033)
TYP
0.60 (0.0236)
TYP
1.41 (0.055)
1.39 (0.054)
Pin 142
72.25 (2.84)
TYP
124.95 (4.92)
TYP
Back view
U21
U22
U23
U24
U25
U33
U34
0.45 (0.02) x 45°, 4X
U26
U27
U28
U29
3.0 (0.118) 4X TYP
U30
U31
U32
U35
U36
U37
U38
0.5 (0.0197)
TYP
3.15 (0.124) TYP
Pin 284
22.1 (0.87)
TYP
10.2 (0.4)
TYP
5.95 (0.234) TYP
22.95 (0.9)
TYP
25.5 (1.0)
TYP
Pin 143
28.05 (1.1)
TYP
63.75 (2.51)
TYP
55.25 (2.175)
TYP
Notes:
10.2 (0.4)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef84f8c349
asf36c2gx72pz.pdf - Rev. C 05/13 EN
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.