4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM RDIMM
MT36HTJ51272Y – 4GB
MT36HTS51272PY – 4GB
MT36HTS1G72PY – 8GB
Features
Figure 1: 240-Pin RDIMM (MO-237 R/C K)
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, or
PC2-5300
• 4GB (512 Meg x 72): 1Gb stacked (HTJ), 2Gb TwinDie™ (HTS); or 8GB (1 Gig x 72): 4Gb TwinDie
• Supports ECC error detection and correction
• VDD = VDDQ = 1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Dual rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Module height: 30mm (1.18in)
Options
• Parity
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)1
• Package
– 240-pin DIMM (lead-free)
• Frequency/CL2
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
– 5.0ns @ CL = 3 (DDR2-400)
Notes:
Marking
P
None
I
Y
-667
-53E
-40E
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
CL = 6
CL = 5
CL = 4
CL = 3
(ns)
tRP
(ns)
tRC
(ns)
-80E
PC2-6400
800
800
533
400
12.5
12.5
55
-800
PC2-6400
800
667
533
400
15
15
55
-667
PC2-5300
–
667
553
400
15
15
55
-53E
PC2-4200
–
–
553
400
15
15
55
-40E
PC2-3200
–
–
400
400
15
15
55
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
1
tRCD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
Table 2: Addressing
Parameter
4GB (HTJ)
4GB (HTS)
8GB
8K
8K
8K
Refresh count
Row address
16K A[13:0]
16K A[13:0]
32K A[14:0]
Device bank address
8 BA[2:0]
8 BA[2:0]
8 BA[2:0]
Device configuration
1Gb (256 Meg x 4)
2Gb TwinDie (512 Meg x 4)
4Gb TwinDie (1 Gig x 4)
2K A[11, 9:0]
2K A[11, 9:0]
2K A[11, 9:0]
2 S#[1:0]
2 S#[1:0]
2 S#[1:0]
Column address
Module rank address
Table 3: Part Numbers and Timing Parameters – 4GB
Base device: MT47H512M4SBT,1 1Gb stacked DDR2 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT36HTJ51272(I)Y-53E__
4GB
512 Meg x 72
4.3 GB/s
3.75ns/533 MT/s
4-4-4
MT36HTJ51272(I)Y-40E__
4GB
512 Meg x 72
3.2 GB/s
5.0ns/400 MT/s
3-3-3
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Table 4: Part Numbers and Timing Parameters – 4GB
Base device: MT47H512M4THN,1 2Gb TwinDie DDR2 SDRAM
Module
Part Number2
Density
Configuration
MT36HTS51272P(I)Y-667__
4GB
512 Meg x 72
5.3 GB/s
3.0ns/667 MT/s
5-5-5
MT36HTS51272P(I)Y-53E__
4GB
512 Meg x 72
4.3 GB/s
3.75ns/533 MT/s
4-4-4
MT36HTS51272P(I)Y-40E__
4GB
512 Meg x 72
3.2 GB/s
5.0ns/400 MT/s
3-3-3
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Table 5: Part Numbers and Timing Parameters – 8GB
Base device: MT47H1GM4THM,1 4Gb TwinDie DDR2 SDRAM
Module
Part Number2
Density
Configuration
MT36HTS1G72P(I)Y-667__
8GB
1 Gig x 72
5.3 GB/s
3.0ns/667 MT/s
5-5-5
MT36HTS1G72P(I)Y-53E__
8GB
1 Gig x 72
4.3 GB/s
3.75ns/533 MT/s
4-4-4
MT36HTS1G72P(I)Y-40E__
8GB
1 Gig x 72
3.2 GB/s
5.0ns/400 MT/s
3-3-3
Notes:
1. Data sheets for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT36HTS51272Y-667A1.
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments
Pin Assignments
Table 6: Pin Assignments
240-Pin RDIMM Front
Pin Symbol Pin
1
VREF
31
2
VSS
3
DQ0
4
5
Symbol
240-Pin RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
DQ19
61
A4
91
VSS
121
VSS
151
VSS
181
VDDQ
32
VSS
62
VDDQ
92
DQS5#
122
DQ4
152
DQ28
182
A3
212 DQS14#
33
DQ24
63
A2
93
DQS5
123
DQ5
153
DQ29
183
A1
213
VSS
DQ1
34
DQ25
64
VDD
94
VSS
124
VSS
154
VSS
184
VDD
214
DQ46
VSS
35
VSS
65
VSS
95
DQ42
125
DQS9
155
DQS12
185
CK0
215
DQ47
6
DQS0#
36
DQS3#
66
VSS
96
DQ43
126
DQS9#
156 DQS12# 186
CK0#
216
VSS
7
DQS0
37
DQS3
67
VDD
97
VSS
127
VSS
157
VSS
187
VDD
217
DQ52
8
VSS
38
VSS
68
Par_In
98
DQ48
128
DQ6
158
DQ30
188
A0
218
DQ53
9
DQ2
39
DQ26
69
VDD
99
DQ49
129
DQ7
159
DQ31
189
VDD
219
VSS
10
DQ3
40
DQ27
70
A10/AP
100
VSS
130
VSS
160
VSS
190
BA1
220
NC
11
VSS
41
VSS
71
BA0
101
SA2
131
DQ12
161
CB4
191
VDDQ
221
NC
12
DQ8
42
CB0
72
VDDQ
102
NC
132
DQ13
162
CB5
192
RAS#
222
VSS
13
DQ9
43
CB1
73
WE#
103
VSS
133
VSS
163
VSS
193
S0#
223
DQS15
14
VSS
44
VSS
74
CAS#
104 DQS6#
134
DQS10
164
DQS17
194
VDDQ
224 DQS15#
15
DQS1#
45
DQS8#
75
VDDQ
105
135 DQS10# 165 DQS17# 195
ODT0
225
VSS
16
DQS1
46
DQS8
76
S1#
106
VSS
136
VSS
166
VSS
196
A13
226
DQ54
17
VSS
47
VSS
77
ODT1
107
DQ50
137
NC
167
CB6
197
VDD
227
DQ55
18
RESET#
48
CB2
78
VDDQ
108
DQ51
138
NC
168
CB7
198
VSS
228
VSS
19
NC
49
CB3
79
VSS
109
VSS
139
VSS
169
VSS
199
DQ36
229
DQ60
20
VSS
50
VSS
80
DQ32
110
DQ56
140
DQ14
170
VDDQ
200
DQ37
230
DQ61
21
DQ10
51
VDDQ
81
DQ33
111
DQ57
141
DQ15
171
CKE1
201
VSS
231
VSS
22
DQ11
52
CKE0
82
VSS
112
VSS
142
VSS
172
VDD
202
DQS13
232
DQS16
23
VSS
53
VDD
83
DQS4#
113 DQS7#
143
DQ20
173
A15
203 DQS13# 233 DQS16#
24
DQ16
54
BA2
84
DQS4
114
DQS7
144
DQ21
174
A14
204
VSS
234
VSS
25
DQ17
55
Err_Out#
85
VSS
115
VSS
145
VSS
175
VDDQ
205
DQ38
235
DQ62
26
VSS
56
VDDQ
86
DQ34
116
DQ58
146
DQS11
176
A12
206
DQ39
236
DQ63
27
DQS2#
57
A11
87
DQ35
117
DQ59
147 DQS11# 177
A9
207
VSS
237
VSS
28
DQS2
58
A7
88
VSS
118
VSS
148
VSS
178
VDD
208
DQ44
238
VDDSPD
29
VSS
59
VDD
89
DQ40
119
SDA
149
DQ22
179
A8
209
DQ45
239
SA0
30
DQ18
60
A5
90
DQ41
120
SCL
150
DQ23
180
A6
210
VSS
240
SA1
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DQS6
3
211
DM5/
DQS14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM.
DMx,
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SCL
Input
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx
I/O
Check bits. Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQS#x
I/O
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx,
RDQS#x
Output
Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disabled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out#
Description
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
VDD/VDDQ
Supply
Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the module VDD.
VDDSPD
Supply
SPD EEPROM power supply: 1.7–3.6V.
VREF
Supply
Reference voltage: VDD/2.
VSS
Supply
Ground.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
NU
–
Not used: These pins are not used in specific module configurations/operations.
RFU
–
Reserved for future use.
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
VSS
RS0#
RS1#
DQS0
DQS0#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DQS8
DQS8#
CB0
CB1
CB2
CB3
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7#
DQ56
DQ57
DQ58
DQ59
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1b
U1t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2b
U2t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U3b
U3t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4b
U4t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5b
U5t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U9b
U9t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U10b
U10t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U11b
U11t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U12b
PDF: 09005aef822553c2
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U12t
DQS9
DQS9#
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
DQ28
DQ29
DQ30
DQ31
DQS17
DQS17#
CB4
CB5
CB6
CB7
DQS13
DQS13#
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
DQ60
DQ61
DQ62
DQ63
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U22b
U22t
U6, U17
Par_In
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U21b
U21t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U20b
U20t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U19b
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
R
E
G
I
S
T
E
R
S
RS0#: Rank 0
RS1#: Rank 1
RBA[2:0]: DDR2 SDRAM
RA[14/13:0]: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
RCKE0: Rank 0
RCKE1: Rank 1
RODT0: Rank 0
RODT1: Rank 1
RESET#
Rank 0 = U1b–U5b, U9b–U16b, U18b–U22b
Rank 1 = U1t–U5t, U9t–U16t, U18t–U22t
U18t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U16b
VSS
S0#
S1#
BA[2:0]
A[15:0]
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
U19t
DM CS# DQS DQS#
U18b
Err_Out#
U16t
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
DDR2 SDRAM x 4
Register x 2
U8
CK0
CK0#
PLL
RESET#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U15b
U15t
U7
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14b
U14t
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13b
6
U13t
SCL
SPD EEPROM
WP A0
A1
SDA
A2
VSS SA0 SA1 SA2
VDDSPD
SPD EEPROM
VDD/VDDQ
DDR2 SDRAM
VREF
DDR2 SDRAM
VSS
DDR2 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
General Description
General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to VSS, permanently disabling hardware write protection.
Register and PLL Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2
SDRAM devices on the following rising clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL) on the module receives and redrives the differential
clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize
system and clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock
cycle to CL.
Parity Operations
The registering clock driver can accept a parity bit from the system’s memory controller, providing even parity for the control, command, and address bus. Parity errors are
flagged on the Err_Out# pin. Systems not using parity are expected to function without
issue if Par_In and Err_Out# are left as no connects (NC) to the system.
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htjs36c512_1gx72.pdf - Rev. G 3/10 EN
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD/VDDQ
VDD/VDDQ supply voltage relative to VSS
–0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.5
2.3
V
Input leakage current; Any input 0V ≤ VIN ≤ Command/Address, RAS#,
VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other CAS#, WE# S#, CKE, ODT, BA
pins not under test = 0V)
CK, CK#
–10
10
µA
II
IOZ
IVREF
1
TC
TA
–250
250
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ, DQS, DQS#
DQs and ODT are disabled
–20
20
µA
VREF leakage current; VREF = Valid VREF level
–144
144
µA
0
85
°C
–40
95
0
70
–40
85
DDR2 SDRAM device operating case
temperature2
Commercial
Module ambient operating temperature
Commercial
Industrial
Industrial
Notes:
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
°C
1. The refresh rate is required to double when TC exceeds 85°C < TC ≤ 95°C.
2. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron’s Web site.
8
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1GA
-187E
-80E
-25E
-800
-25
-667
-3
-53E
-37E
-40E
-5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 4GB (HTJ)
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet
Parameter
Symbol
-53E
-40E
Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD01
1386
1386
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid commands; Address
DD
bus inputs are switching; Data pattern is same as IDD4W
IDD11
1836
1746
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
IDD2P2
252
252
mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
IDD2Q2
1440
1260
mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N2
1440
1260
mA
Active power-down current: All device banks open; tCK = Fast PDN exit
tCK (I ); CKE is LOW; Other control and address bus inputs MR[12] = 0
DD
are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
IDD3P2
1080
1080
mA
360
360
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N2
1620
1440
mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching
IDD4W2
2376
2016
mA
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4R2
2376
2016
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD52
7560
7380
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating
IDD62
252
252
mA
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 4GB (HTJ) (Continued)
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet
Parameter
Symbol
-53E
-40E
Units
Operating bank interleave read current: All device banks interleaving
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =
tCK (I ), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S#
DD
DD
DD
DD
is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching
Notes:
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
IDD71
4986
4806
mA
1. Value calculated as one module rank in this operating condition. All other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
11
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 4GB (HTS)
Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg
x 4) component data sheet
Combined
Parameter
Symbol
-667
-53E
-40E
Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (I ), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid
DD
DD
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0
1746
1476
1476
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL
= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W
ICDD1
2016
1926
1836
mA
Precharge power-down current: All device banks idle; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
ICDD2P
252
252
252
mA
Precharge quiet standby current: All device banks idle; tCK = tCK
(IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
ICDD2Q
1206
1224
1242
mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
ICDD2N
936
936
846
mA
Active power-down current: All device banks open;
tCK = tCK (I ); CKE is LOW; Other control and address
DD
bus inputs are stable; Data bus inputs are floating
ICDD3P
540
540
540
mA
180
180
180
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid
DD
DD
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
ICDD3N
1026
1206
936
mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching
ICDD4W
2556
2376
2016
mA
Operating burst read current: All device banks open; Continuous
burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS
= tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD4R
2646
2466
2106
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are switching
ICDD5
4086
3996
3906
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
ICDD6
252
252
252
mA
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12
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 4GB (HTS) (Continued)
Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg
x 4) component data sheet
Combined
Parameter
Symbol
-667
-53E
-40E
Units
Operating bank interleave read current: All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are
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13
ICDD7
5256
5076
4896
mA
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© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
Table 12: DDR2 IDD Specifications and Conditions – 8GB
Values shown for MT47H1GM4 DDR2 SDRAM only and are computed from values specified in the 4Gb (1 Gig x 4) component data sheet
Combined
Parameter
Symbol
-667
-53E
-40E
Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (I ), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid
DD
DD
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0
2034
1854
1854
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL
= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W
ICDD1
2844
2124
2124
mA
Precharge power-down current: All device banks idle; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
ICDD2P
288
288
288
mA
Precharge quiet standby current: All device banks idle; tCK = tCK
(IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
ICDD2Q
1134
1152
1170
mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
ICDD2N
1314
1134
1044
mA
Active power-down current: All device banks open;
tCK = tCK (I ); CKE is LOW; Other control and address
DD
bus inputs are stable; Data bus inputs are floating
ICDD3P
720
630
540
mA
180
180
180
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid
DD
DD
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
ICDD3N
1224
1044
954
mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching
ICDD4W
2844
2484
2394
mA
Operating burst read current: All device banks open; Continuous
burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS
= tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD4R
3294
3312
3330
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are switching
ICDD5
5274
4914
4734
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
ICDD6
288
288
288
mA
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14
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
Table 12: DDR2 IDD Specifications and Conditions – 8GB (Continued)
Values shown for MT47H1GM4 DDR2 SDRAM only and are computed from values specified in the 4Gb (1 Gig x 4) component data sheet
Combined
Parameter
Symbol
-667
-53E
-40E
Units
Operating bank interleave read current: All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
15
ICDD7
6354
5544
5544
mA
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© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
Register and PLL Specifications
Table 13: Register Specifications
SSTU32866 devices or equivalent
Parameter
Symbol
Pins
Condition
Min
Max
Units
DC high-level
input voltage
VIH(DC)
Control, command,
address
SSTL_18
VREF(DC) + 125
VDDQ + 250
mV
DC low-level
input voltage
VIL(DC)
Control, command,
address
SSTL_18
0
VREF(DC) - 125
mV
AC high-level
input voltage
VIH(AC)
Control, command,
address
SSTL_18
VREF(DC) + 250
–
mV
AC low-level
input voltage
VIL(AC)
Control, command,
address
SSTL_18
–
VREF(DC) - 250
mV
Output high
voltage
VOH
Parity output
LVCMOS
1.2
–
V
Output low voltage
VOL
Parity output
LVCMOS
–
0.5
V
Input current
II
All pins
VI = VDD or VSS
–
0.5
µA
Static standby
IDD
All pins
RESET# = VSSQ (Io = 0)
–5
5
mA
Static operating
IDD
All pins
RESET# = VSS; VI = VIH(AC)
or VIL(DC) Io = 0
–
100
mA
Dynamic operating
(clock tree)
IDDD
N/A
RESET# = VDD;
VI = VIH(DC) or VIL(AC),
IO = 0; CK and CK# switching 50% duty cycle
–
Varies by
manufacturer
µA
Dynamic operating
(per each input)
IDDD
N/A
RESET# = VDD;
VI = VIH(AC) or VIL(DC), IO =
0; CK and CK#
switching 50% duty cycle; One data in/out
switching at tCK/2, 50%
duty cycle
–
Varies by
manufacturer
µA
Input capacitance
(per device, per pin)
CIN
All inputs except
RESET#
VI = VREF ±250mV;
VDD = 1.8V
2.5
3.5
pF
Input capacitance
(per device, per pin)
CIN
RESET#
VI = VDD or VSS
Varies by
manufacturer
Varies by
manufacturer
pF
Note:
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
1. Timing and switching specifications for the register listed are critical for proper operation of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available
in JEDEC standard JESD82.
16
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
Table 14: PLL Specifications
CU877 device or equivalent
Parameter
Symbol
Pins
Condition
Min
Max
Units
DC high-level
input voltage
VIH
RESET#
LVCMOS
0.65 × VDD
–
V
DC low-level
input voltage
VIL
RESET#
LVCMOS
–
0.35 × VDD
V
Input voltage (limits)
VIN
RESET#, CK, CK#
–
0.3
VDD + 0.3
V
DC high-level
input voltage
VIH
CK, CK#
Differential input
0.65 × VDD
–
V
DC low-level
input voltage
VIL
CK, CK#
Differential input
–
0.35 × VDD
V
Input differential-pair
cross voltage
VIX
CK, CK#
Differential input
(VDDQ/2) - 0.15
(VDD/2) - 0.15
V
Input differential
voltage
VID(DC)
CK, CK#
Differential input
0.3
VDD - 0.4
V
Input differential
voltage
VID(AC)
CK, CK#
Differential input
0.6
VDD - 0.4
V
RESET#
VI = VDD or VSS
–10
10
µA
CK, CK#
VI = VDD or VSS
–250
250
µA
Input current
II
Output disabled
current
IODL
RESET# = VSS; VI = VIH(AC)
or VIL(DC)
100
–
µA
Static supply current
IDDLD
CK = CK# = LOW
–
500
µA
Dynamic supply
IDD
N/A
CK, CK# = 270 MHz, all
outputs open (not connected to PCB)
–
300
mA
Input capacitance
CIN
Each input
VI = VDD or VSS
2
3
pF
Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter
Symbol
Min
Max
tL
–
15
μs
slr(i)
1.0
4.0
V/ns
SSC modulation frequency
–
30
33
kHz
SSC clock input frequency deviation
–
0.0
–0.5
%
PLL loop bandwidth (–3dB from unity gain)
–
2.0
–
MHz
Stabilization time
Input clock slew rate
Note:
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
Units
1. PLL timing and switching specifications are critical for proper operation of the DDR2
DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information
is available in JEDEC standard JESD82.
17
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4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 16: SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
1.7
3.6
V
Input high voltage: logic 1; All inputs
VIH
VDDSPD × 0.7
VDDSPD + 0.5
V
Input low voltage: logic 0; All inputs
VIL
–0.6
VDDSPD × 0.3
V
Output low voltage: IOUT = 3mA
Supply voltage
VOL
–
0.4
V
Input leakage current: VIN = GND to VDD
ILI
0.1
3
µA
Output leakage current: VOUT = GND to VDD
ILO
0.05
3
µA
Standby current
ISB
1.6
4
µA
Power supply current, READ: SCL clock frequency = 100 kHz
ICCR
0.4
1
mA
Power supply current, WRITE: SCL clock frequency = 100 kHz
ICCW
2
3
mA
Table 17: SPD EEPROM AC Operating Conditions
Symbol
Min
Max
Units
Notes
SCL LOW to SDA data-out valid
Parameter/Condition
tAA
0.2
0.9
µs
1
Time bus must be free before a new transition can start
tBUF
1.3
–
µs
Data-out hold time
tDH
200
–
ns
SDA and SCL fall time
tF
–
300
ns
2
SDA and SCL rise time
tR
–
300
ns
2
Data-in hold time
tHD:DAT
0
–
µs
Start condition hold time
tHD:STA
0.6
–
µs
tHIGH
0.6
–
µs
tI
–
50
µs
tLOW
1.3
–
µs
tSCL
–
400
kHz
Data-in setup time
tSU:DAT
100
–
ns
Start condition setup time
tSU:STA
0.6
–
µs
Stop condition setup time
tSU:STO
0.6
–
µs
tWRC
–
10
ms
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
WRITE cycle time
Notes:
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
3
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pullup resistance, and the EEPROM does not respond to its slave address.
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Module Dimensions
Module Dimensions
Figure 3: 240-Pin DDR2 RDIMM
Front view
‘HTJ’ Module
7.12 (0.2803)
MAX
133.50 (5.256)
133.20 (5.244)
U7
2.00 (0.079) R
(4X)
U6
U1
U2
U3
U5
U4
2.50 (0.098) D
(2X)
U9
U10
U11
U12
30.15 (1.185)
29.85 (1.175)
17.78 (0.700)
TYP
U8
2.30 (0.091) TYP
0.76 (0.030) R
Pin 1
1.0 (0.039)
TYP
2.21 (0.087) TYP
10.00 (0.394)
TYP
0.80 (0.031)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 120
70.66 (2.782)
TYP
‘HTS’ Module
4.0 (0.157)
MAX
123.0 (4.840)
TYP
Back view
U17
U13
3.04 (0.1197)
TYP
U14
U15
Pin 240
U16
U18
U19
U21
U22
Pin 121
5.0 (0.197) TYP
55.0 (2.165)
TYP
Notes:
U20
1.37 (0.054)
1.17 (0.046)
63.0 (2.48)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
complete design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef822553c2
htjs36c512_1gx72.pdf - Rev. G 3/10 EN
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.