1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM

1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT16HTF12864AZ – 1GB
MT16HTF25664AZ – 2GB
MT16HTF51264AZ – 4GB
Features
Figure 1: 240-Pin UDIMM (MO-237 R/C E)
• 240-pin, unbuffered dual in-line memory module
• Fast data transfer rates: PC2-8500, PC2-6400,
PC2-5300, PC2-4200, or PC2-3200
• 1GB (128 Meg x 64), 2GB (256 Meg x 64), 4GB (512
Meg x 64)
• VDD = V DDQ = 1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank
• Halogen-free
Module height: 30mm (1.18in)
Options
Marking
• Operating temperature
– Commercial (0°C ≤ T A ≤ +70°C)
– Industrial (–40°C ≤ T A ≤ +85°C)1
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CL2
– 1.875ns @ CL = 7 (DDR2-1066)3
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3ns @ CL = 5 (DDR2-667)
Notes:
None
I
Z
-1GA
-80E
-800
-667
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Not recommended for new designs.
Table 1: Key Timing Parameters
Data Rate (MT/s)
tRCD
tRP
tRC
CL = 3
(ns)
(ns)
(ns)
533
400
13.125
13.125
58.125
800
533
400
12.5
12.5
57.5
667
533
400
15
15
60
–
667
553
400
15
15
60
PC2-4200
–
–
553
400
15
15
55
PC2-3200
–
–
400
400
15
15
55
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Speed
Grade
Industry
Nomenclature
CL = 7
CL = 6
CL = 5
CL = 4
-1GA
PC2-8500
1066
800
667
-80E
PC2-6400
800
-800
PC2-6400
800
-667
PC2-5300
-53E
-40E
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htf16c128_256_512x64az – Rev. E 4/14 EN
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 2: Addressing
Parameter
1GB
2GB
4GB
8K
8K
8K
16K A[13:0]
16K A[13:0]
32K A[14:0]
Device bank address
4 BA[1:0]
8 BA[2:0]
8 BA[2:0]
Device configuration
Refresh count
Row address
512Mb (64 Meg x 8)
1Gb (128 Meg x 8)
2Gb (256 Meg x 8)
Column address
1K A[9:0]
1K A[9:0]
1K A[9:0]
Module rank address
2 S#[1:0]
2 S#[1:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H64M8,1 512Mb DDR2 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT16HTF12864A(I)Z-80E__
1GB
128 Meg x 64
6.4 GB/s
2.5ns/800 MT/s
5-5-5
MT16HTF12864A(I)Z-800__
1GB
128 Meg x 64
6.4 GB/s
2.5ns/800 MT/s
6-6-6
MT16HTF12864A(I)Z-667__
1GB
128 Meg x 64
5.3 GB/s
3.0ns/667 MT/s
5-5-5
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Table 4: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT47H128M8,1 1Gb DDR2 SDRAM
Module
Part Number2
Density
Configuration
MT16HTF25664A(I)Z-1GA__
2GB
256 Meg x 64
8.5 GB/s
1.875ns/1066 MT/s
7-7-7
MT16HTF25664A(I)Z-80E__
2GB
256 Meg x 64
6.4 GB/s
2.5ns/800 MT/s
5-5-5
MT16HTF25664A(I)Z-800__
2GB
256 Meg x 64
6.4 GB/s
2.5ns/800 MT/s
6-6-6
MT16HTF25664A(I)Z-667__
2GB
256 Meg x 64
5.3 GB/s
3.0ns/667 MT/s
5-5-5
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Table 5: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT47H256M8,1 2Gb DDR2 SDRAM
Module
Part Number2
Density
Configuration
MT16HTF51264A(I)Z-1GA__
4GB
512 Meg x 64
8.5 GB/s
1.875ns/1066 MT/s
7-7-7
MT16HTF51264A(I)Z-80E__
4GB
512 Meg x 64
6.4 GB/s
2.5ns/800 MT/s
5-5-5
MT16HTF51264A(I)Z-800__
4GB
512 Meg x 64
6.4 GB/s
2.5ns/800 MT/s
6-6-6
MT16HTF51264A(I)Z-667__
4GB
512 Meg x 64
5.3 GB/s
3.0ns/667 MT/s
5-5-5
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT16HTF25664AZ-800M1.
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htf16c128_256_512x64az – Rev. E 4/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments
Pin Assignments
Table 6: Pin Assignments
240-Pin UDIMM Front
240-Pin UDIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
VREF
31
DQ19
61
A4
91
VSS
121
VSS
151
VSS
181
VDDQ
211
DM5
2
VSS
32
VSS
62
VDDQ
92
DQS5#
122
DQ4
152
DQ28
182
A3
212
NC
3
DQ0
33
DQ24
63
A2
93
DQS5
123
DQ5
153
DQ29
183
A1
213
VSS
4
DQ1
34
DQ25
64
VDD
94
VSS
124
VSS
154
VSS
184
VDD
214
DQ46
5
VSS
35
VSS
65
VSS
95
DQ42
125
DM0
155
DM3
185
CK0
215
DQ47
6
DQS0#
36
DQS3#
66
VSS
96
DQ43
126
NC
156
NC
186
CK0#
216
VSS
7
DQS0
37
DQS3
67
VDD
97
VSS
127
VSS
157
VSS
187
VDD
217
DQ52
8
VSS
38
VSS
68
NC
98
DQ48
128
DQ6
158
DQ30
188
A0
218
DQ53
9
DQ2
39
DQ26
69
VDD
99
DQ49
129
DQ7
159
DQ31
189
VDD
219
VSS
10
DQ3
40
DQ27
70
A10
100
VSS
130
VSS
160
VSS
190
BA1
220
CK2
11
VSS
41
VSS
71
BA0
101
SA2
131
DQ12
161
NC
191
VDDQ
221
CK2#
12
DQ8
42
NC
72
VDDQ
102
NC
132
DQ13
162
NC
192
RAS#
222
VSS
13
DQ9
43
NC
73
WE#
103
VSS
133
VSS
163
VSS
193
S0#
223
DM6
14
VSS
44
VSS
74
CAS#
104
DQS6#
134
DM1
164
NC
194
VDDQ
224
NC
15
DQS1#
45
NC
75
VDDQ
105
DQS6
135
NC
165
NC
195
ODT0
225
VSS
16
DQS1
46
NC
76
S1#
106
VSS
136
VSS
166
VSS
196
A13
226
DQ54
17
VSS
47
VSS
77
ODT1
107
DQ50
137
CK1
167
NC
197
VDD
227
DQ55
18
NC
48
NC
78
VDDQ
108
DQ51
138
CK1#
168
NC
198
VSS
228
VSS
19
NC
49
NC
79
VSS
109
VSS
139
VSS
169
VSS
199
DQ36
229
DQ60
20
VSS
50
VSS
80
DQ32
110
DQ56
140
DQ14
170
VDDQ
200
DQ37
230
DQ61
21
DQ10
51
VDDQ
81
DQ33
111
DQ57
141
DQ15
171
CKE1
201
VSS
231
VSS
22
DQ11
52
CKE0
82
VSS
112
VSS
142
VSS
172
VDD
202
DM4
232
DM7
23
VSS
53
VDD
83
DQS4#
113
DQS7#
143
DQ20
173
NC
203
NC
233
NC
24
DQ16
54
BA2
84
DQS4
114
DQS7
144
DQ21
174
NF/A141
204
VSS
234
VSS
25
DQ17
55
NC
85
VSS
115
VSS
145
VSS
175
VDDQ
205
DQ38
235
DQ62
26
VSS
56
VDDQ
86
DQ34
116
DQ58
146
DM2
176
A12
206
DQ39
236
DQ63
27
DQS2#
57
A11
87
DQ35
117
DQ59
147
NC
177
A9
207
VSS
237
VSS
28
DQS2
58
A7
88
VSS
118
VSS
148
VSS
178
VDD
208
DQ44
238
VDDSPD
29
VSS
59
VDD
89
DQ40
119
SDA
149
DQ22
179
A8
209
DQ45
239
SA0
30
DQ18
60
A5
90
DQ41
120
SCL
150
DQ23
180
A6
210
VSS
240
SA1
Note:
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htf16c128_256_512x64az – Rev. E 4/14 EN
1. Pin 174 is NF for 1GB, 2GB or A14 for 4GB.
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SCL
Input
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx
I/O
Check bits. Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQS#x
I/O
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx,
RDQS#x
Output
Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disabled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out#
Description
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
VDD/VDDQ
Supply
Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the module VDD.
VDDSPD
Supply
SPD EEPROM power supply: 1.7–3.6V.
VREF
Supply
Reference voltage: VDD/2.
VSS
Supply
Ground.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
NU
–
Not used: These pins are not used in specific module configurations/operations.
RFU
–
Reserved for future use.
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htf16c128_256_512x64az – Rev. E 4/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S1#
VSS
S0#
VSS
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
CS#
DQS
DM
DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U18
DQS1#
DQS1
DM1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
CS# DQS
DQS#
U14
DQS5#
DQS5
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
CS# DQS
DM
DQS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U17
DQS2#
DQS2
DM2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U6
CS# DQS
DQS#
U13
DQS6#
DQS6
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U3
CS# DQS
DM
DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U16
DQS3#
DQS3
DM3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U7
CS# DQS
DQS#
U12
DQS7#
DQS7
DM7
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
U4
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DM
DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U8
CS# DQS
DQS#
U11
U10
BA[2/1:0]: SDRAM
A[14/13:0]: SDRAM
BA[2/1:0]
A[14/13:0]
RAS#
CAS#
WE#
RAS#: SDRAM
CAS#: SDRAM
WE#: SDRAM
CKE0
CKE0: U1–U8
SPD EEPROM
WP A0
A1
SDA
A2
CK0
CK0#
U4, U5,
U13, U14
CK1
CK1#
U1–U3,
U15–U17
CK2
CK2#
U6–U8,
U10–U12
VSS SA0 SA1 SA2
VDDSPD
SPD EEPROM
VDD/VDDQ
DDR2 SDRAM
VREF
DDR2 SDRAM
VSS
VSS
CKE1
SCL
DDR2 SDRAM, EEPROM
CKE1: U10–U17
VSS
ODT0
ODT1
ODT0: U1–U8
VSS
ODT1: U10–U17
VSS
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htf16c128_256_512x64az – Rev. E 4/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
General Description
General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is
transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to V SS, permanently disabling hardware write protection.
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htf16c128_256_512x64az – Rev. E 4/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet are not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD/VDDQ
VDD/VDDQ supply voltage relative to VSS
–0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.5
2.3
V
Input leakage current; Any input 0V ≤ VIN ≤ VDD; Address inputs, RAS#,
VREF input 0V ≤ VIN ≤ 0.95V; (All other pins not
CAS#, WE#, BA
under test = 0V)
S#, CKE, ODT
–80
80
µA
II
IOZ
IVREF
TA
–40
40
CK0, CK0#
–20
20
CK1, CK1#, CK2, CK2#
–30
30
DM
–10
10
Output leakage current; 0V ≤ VOUT; DQ and ODT DQ, DQS, DQS#
are disabled
–10
10
µA
VREF leakage current; VREF = valid VREF level
–32
32
µA
0
70
°C
–40
85
°C
0
85
°C
–40
95
°C
Module ambient operating temperature
Commercial
Industrial
1
TC
DDR2 SDRAM component operating temperature2
Notes:
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
Commercial
Industrial
1. The refresh rate is required to double when TC exceeds 85°C.
2. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron’s Web site.
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1GA
-187E
-80E
-25E
-800
-25
-667
-3
-53E
-37E
-40E
-5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 1GB (Die Revision G)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
-80E/
Parameter
Symbol
-800
-667
Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
inputs are switching; Data bus inputs are switching
IDD01
576
536
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL
(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as IDD4W
IDD11
656
616
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW;
Other control and address bus inputs are stable; Data bus inputs are floating
IDD2P2
112
112
mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
IDD2Q2
384
352
mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
IDD2N2
448
400
mA
Active power-down current: All device banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD3P2
288
240
mA
144
144
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs are switching
IDD3N2
528
480
mA
Operating burst write current: All device banks open; Continuous burst writes; BL
= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
IDD4W1
1056
976
mA
Operating burst read current: All device banks open; Continuous burst read, IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
IDD4R1
1016
936
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
IDD51
816
776
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
IDD62
112
112
mA
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 1GB (Die Revision G) (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
-80E/
Parameter
Symbol
-800
-667
Units
Operating bank interleave read current: All device banks interleaving reads; IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC
(IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
Notes:
IDD71
1256
1176
mA
1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 11: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet
-80E/
Parameter
Symbol -1GA -800
-667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD01
656
576
536
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inDD
puts are switching; Data pattern is same as IDD4W
IDD11
736
656
616
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
IDD2P2
112
112
112
mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2Q2
448
384
384
mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2N2
544
448
384
mA
Active power-down current: All device banks open; tCK =
Fast PDN exit
(IDD); CKE is LOW; Other control and address bus inputs are MR[12] = 0
stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
IDD3P2
368
320
240
mA
160
160
160
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N2
640
528
480
tCK
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
11
mA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H) (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet
-80E/
Parameter
Symbol -1GA -800
-667 Units
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
DD
are switching; Data bus inputs are switching
IDD4W1
1216
1056
976
mA
Operating burst read current: All device banks open; Continuous burst read,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
inputs are switching; Data bus inputs are switching
IDD4R1
1176
1016
936
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD51
1296
1216
1176
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating
IDD62
112
112
112
mA
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
IDD71
1816
1736
1536
mA
Notes:
1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet
-80E/
Parameter
Symbol -1GA -800
-667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD01
680
600
560
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inDD
puts are switching; Data pattern is same as IDD4W
IDD11
760
680
640
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
IDD2P2
160
160
160
mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2Q2
448
384
384
mA
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M) (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet
-80E/
Parameter
Symbol -1GA -800
-667 Units
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2N2
544
448
384
mA
Active power-down current: All device banks open; tCK =
Fast PDN exit
(IDD); CKE is LOW; Other control and address bus inputs are MR[12] = 0
stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
IDD3P2
512
480
448
mA
320
320
320
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N2
640
528
480
mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
DD
are switching; Data bus inputs are switching
IDD4W1
1240
1080
1000
mA
Operating burst read current: All device banks open; Continuous burst read,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
inputs are switching; Data bus inputs are switching
IDD4R1
1200
1040
960
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD51
1400
1320
1280
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating
IDD62
112
112
112
mA
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
IDD71
1840
1760
1560
mA
tCK
Notes:
1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 13: DDR2 IDD Specifications and Conditions – 4GB (Die Revision C)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet
-80E/
Parameter
Symbol -1GA -800
-667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
13
IDD01
776
696
656
mA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 13: DDR2 IDD Specifications and Conditions – 4GB (Die Revision C) (Continued)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet
-80E/
Parameter
Symbol -1GA -800
-667 Units
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inDD
puts are switching; Data pattern is same as IDD4W
IDD11
856
784
736
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
IDD2P2
192
192
192
mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2Q2
560
480
400
mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2N2
640
560
480
mA
Active power-down current: All device banks open; tCK =
Fast PDN exit
tCK (I ); CKE is LOW; Other control and address bus inputs are MR[12] = 0
DD
stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
IDD3P2
400
400
400
mA
224
224
224
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N2
960
800
720
mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
DD
are switching; Data bus inputs are switching
IDD4W1
1376
1136
976
mA
Operating burst read current: All device banks open; Continuous burst read,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
inputs are switching; Data bus inputs are switching
IDD4R1
1376
1136
976
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD51
1496
1456
1416
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating
IDD62
192
192
192
mA
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
IDD71
1936
1856
1696
mA
Notes:
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 14: SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
1.7
3.6
V
Input high voltage: logic 1; All inputs
VIH
VDDSPD × 0.7
VDDSPD + 0.5
V
Input low voltage: logic 0; All inputs
VIL
–0.6
VDDSPD × 0.3
V
Output low voltage: IOUT = 3mA
Supply voltage
VOL
–
0.4
V
Input leakage current: VIN = GND to VDD
ILI
0.1
3
µA
Output leakage current: VOUT = GND to VDD
ILO
0.05
3
µA
Standby current
ISB
1.6
4
µA
Power supply current, READ: SCL clock frequency = 100 kHz
ICCR
0.4
1
mA
Power supply current, WRITE: SCL clock frequency = 100 kHz
ICCW
2
3
mA
Table 15: SPD EEPROM AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
Notes
SCL LOW to SDA data-out valid
tAA
0.2
0.9
µs
1
Time bus must be free before a new transition can start
tBUF
1.3
–
µs
Data-out hold time
tDH
200
–
ns
SDA and SCL fall time
tF
–
300
ns
2
SDA and SCL rise time
tR
–
300
ns
2
Data-in hold time
tHD:DAT
0
–
µs
Start condition hold time
tHD:STA
0.6
–
µs
tHIGH
0.6
–
µs
tI
–
50
ns
tLOW
1.3
–
µs
tSCL
–
400
kHz
Data-in setup time
tSU:DAT
100
–
ns
Start condition setup time
tSU:STA
0.6
–
µs
Stop condition setup time
tSU:STO
0.6
–
µs
tWRC
–
10
ms
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
WRITE cycle time
Notes:
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
3
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Module Dimensions
Module Dimensions
Figure 3: 240-Pin DDR2 UDIMM
Front view
4.0 (0.157)
MAX
133.5 (5.256)
133.2 (5.244)
2.0 (0.079) R
(4X)
U1
U2
U3
U4
U5
U6
U7
U8
30.5 (1.2)
29.85 (1.175)
U10
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.3 (0.091) TYP
0.76 (0.03) R
Pin 1
2.2 (0.087) TYP
1.0 (0.039)
TYP
1.0 (0.039) TYP
10.0 (0.394)
TYP
0.8 (0.031)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 120
70.68 (2.78)
TYP
123.0 (4.84)
TYP
Back view
45° (4X)
U11
U12
U13
U14
U15
U16
U17
U18
3.05 (0.12) TYP
Pin 240
Pin 121
5.0 (0.197) TYP
63.0 (2.48)
TYP
55.0 (2.165)
TYP
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef83b82bc1
htf16c128_256_512x64az – Rev. E 4/14 EN
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