8 6 7 2 3 4 5 1 REVISIONS REV Y1 AND Y2 HAVE A COMMON FOOTPRINT DESCRIPTION APPROVED DATE VDD3.3 DNI 1 VCC ENABLE 0 R114 GND C5 DNI 0.01UF GND 0 100 15PF R20 DNI C8 XOA XOB VDD1.8 1 2 3 4 5 6 7 8 9 10 IRQ SCLK_SCL SDIO_SDA SDO CSB DVDD AVDD XOA XOB AVDD DNI 0.1UF 0.1UF C6 30 29 28 27 26 25 24 23 22 21 VDD3.3 REFA_N REFA_P SYNCB/FSYNCB PINCONTROL RESETB VDD1.8 VDD1.8 VDD1.8 LF_PLL2 0.1UF C36 0.1UF C 5 4 3 2 GND J21 JOHNSON142-0701-201 1 DNI R44 5 4 3 2 TP2 1 WHT GND 0 VDD1.8_P17 VDD1.8_P18 VDD3.3 LDO_VCO2 VDD1.8_P11 OUT1B OUT1 VDD3.3_P14 11 12 13 14 15 16 17 18 19 20 GND 0 R58 DVDD3 REFA_N REFA_P SYNCB PINCONTROL RESETB AVDD AVDD AVDD LF_PLL2 U13 AD9557_PRELIM J22 JOHNSON142-0701-201 1 C35 AVDD OUT1B OUT1 AVDD3 OUT0B OUT0 AVDD AVDD AVDD3 LDO_BYPASS C4 R12 DNI IRQ SCLK/SCL SDIO/SDA SDO CSB VDD1.8_P6 VDD1.8 GND 2 4 100 J1 JOHNSON142-0701-201 CASE 3 15PF 1 Y4 49.152MEGHZ GND 3 R7 1 PAD DVDD3 M3 M2 M1 M0 DVDD DVDD REFB_N REFB_P DVDD3 C7 T1 MABA-007159-000000 5 1 4 PAD 40 39 38 37 36 35 34 33 32 31 0 R11 0.1UF GND VDD3.3 M3 M2 M1 M0 VDD1.8_P35 VDD1.8 DNI C3 GND C2 TBD0402 DNI SEC 0 DNI 100 TBD0402 R56 TBD0402 VDD3.3 100 R116 R50 R10 VDD3.3 GND REFB_N REFB_P GND DNI PRI GND DNI T5 1 2 3 6 7 4 25MHZ 1 CAN USE VECTRON OR CONNOR WINFIELD TCXO VECTRON = YSML276W197H98 R115 TBD0402 5 0 R19 2 3 4 5 5 SEC R2 GND 0.1UF PRI OUT VCON CONWIN TCXO NC GND DNI 2 3 4 5 D 4 3 MABA-007159-000000 8 TRI_STATE 10 0 C 0.1UF C22 VCC R1 GND SEC J10 JOHNSON142-0701-201 1 GND 9 PRI 4 3 MABA-007159-000000 GND 25MHZ DNI Y1 VDD3.3 TCXO_P 2 3 4 5 2 VDD3.3 0 3 GND DNI D OUTPUT C20 100 R113 VDD3.3 1 R35 DNI T3 5 100 J9 JOHNSON142-0701-201 1 4 R31 Y2 VECTRON TCXO C27 0.47UF OUT0B OUT0 C31 6800PF B GND B R25 100 C32 R36 GND 100 C30 C28 R45 0.1UF TBD0402 0.1UF TBD0402 4 PRI 3 SEC T2 MABA-007159-000000 5 1 142-0761-861 J17 1 1 2 3 4 GND 100 GND 2 3 4 0.1UF C18 C17 0.1UF C26 GND 142-0761-861 J18 R32 GND A A GND 1 2 3 4 J13 142-0761-861 1 2 3 4 DNI GND 0 J14 142-0761-861 AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9557 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9557CE02 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 J.SCUTERI 2 SCALE NONE SHEET 1 1 OF 4 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED USB SECTION CY7C68013A-56PVXC U4 IRQ VDD3.3 TP1 1 WHT IRQ_U R87 300 74LVC541APW GND 1 C59 12PF 2 3 4 5 6 7 8 9 U9 GND 18 CSB_BUF O0 17 RESETB O1 16 SYNCB/FSYNCB O2 15 USB_STATUS O3 14 SCLK_BUF O4 13 O5 12 O6 11 10 19 0 ENABLE LED'S GND C SML-LX1206IW-TR (RED) TSW-102-08-G-D C R112 R111 1K 1K R60 300 74LVC541APW A CR3 MANMODE SCLK_U C GND M0 300 SWITHCES OPERATE IN MAN MODE ONLY U9 MUST BE HI-Z GND CR4 R63 GND SML-LX1206IW-TR (RED) 4 7 19 33 35 48 CR13 GND 1 2 3 4 TRI-STATE BUFFER LINE DRIVER VCC I0 I1 I2 I3 I4 I5 I6 I7 O7 EN1_N EN2_N 1 0 A RESETB CSB_U RESETB_U SYNCB/FSYNCB_U USB_STATUS_U SCLK_U GND R84 S2 1A 2A 1B 2B 7914J-1-000E 20 12PF D+ D- P4 R82 CTL2/FLAGC GND 13 17 AGND C58 2 Y3 2.2UF U4 AVCC VCC XTALIN 12 11 XTALOUT SCL 15 DPLUS SDA CY7C68013A-56PVXC 16 USB CHIP RESET* DMINUS 5 CLKOUT/T1OUT WAKEUP 20 RDY0/SLRD IFCLK/T0OUT 36 RDY1/SLWR CTL0/FLAGA 37 RESERVED CTL1/FLAGB 38 SDA SCL GND 19 M0_BUF M1_BUF M2_BUF DNI 6 18 24 34 39 50 10 14 1UF 22 23 49 51 8 9 21 GND VCC I0 I1 I2 I3 I4 I5 I6 I7 O7 EN1_N EN2_N TRI-STATE BUFFER LINE DRIVER C57 0.1UF C56 100K 1MEG C54 SML-LX1206IW-TR (RED) 10UF GND U1 GND 18 O0 17 O1 16 O2 15 O3 14 O4 13 O5 12 O6 11 10 1 VDD3.3 R39 C55 C R43 4700PF 100K CR2 R41 A VDD3.3 GND P16 1 2 3 4 GND GND C53 2 3 4 5 6 7 8 9 M0 M1 M2 4-1734376-8 GND1 VDD3.3 20 USB CHIP R38 750 C DD+ MANMODE 1K S1 1A 2A 1B 2B 7914J-1-000E 2 3 6 R90 SYNCB 1 4 5 VBUS DNI GND P1 SAMTECTSW10608GS4PIN VDD3.3 USB CONNECTOR D TDC HEADER PA0/INT0* 40 USB_STATUS_U CSB_U PA1/INT1* 41 42 RESETB_U PA2/SLOE 43 IRQ_U PA3/WU2 44 SYNCB/FSYNCB_U PA4/FIFOADR0 45 PA5/FIFOADR1 PA6/PKTEND 46 PA7/FLAGD/SLCS* 47 SDIO_U PB0/FD0 25 26 SDO_INT PB1/FD1 27 PB2/FD2 PB3/TXD1/FD3 28 PB4/FD4 29 PB5/FD5 30 PB6/FD6 31 PB7/FD7 32 M0 PD0/FD8 52 53 M1 PD1/FD9 54 M2 PD2/FD10 55 M3 PD3/FD11 56 PD4/FD12 PD5/FD13 1 PD6/FD14 2 PD7/FD15 3 24.000MEGHZ D M1 GND A C SML-LX1206GW-TR (GREEN) CR5 R64 A C SML-LX1206IW-TR (RED) 300 SDIO/SDA_INT VDD3.3 GND 20 10 VCC GND I0 O0 I1 O1 I2 O2 I3 O3 I4 O4 I5 O5 I6 O6 I7 O7 EN1_N EN2_N 1 1K GND 1K R22 VDD3.3 GND 1K R16 VDD3.3 GND 1K R14 VDD3.3 R9 GND 1K R6 VDD3.3 SAMTECTSW10608GS3PIN CR6 R65 300 A C SML-LX1206GW-TR (GREEN) B 18 17 16 15 14 13 12 11 M3 CR7 R66 A C SML-LX1206IW-TR (RED) 300 P15 GND 19 1 2 3 4 5 SAMTECTSW10608GS5PIN TRI-STATE BUFFER LINE DRIVER GND TSW-102-08-G-S SELECTS I2C OR SPI SAMTECTSW10608GS3PIN SELECTS I2C OR SPI 2 3 4 5 6 7 8 9 M0 M1 M2 M3 M3 M2 M1 M0 1 2 3 P3 1 2 P2 1K R23 1K R21 1K R15 1K R13 1K R8 GND M0 M1 M2 M3 VDD3.3 P7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK/SCL SERIAL_CLK R83 R85 0 0 GND ENABLE LED'S TSW-105-08-G-T A 0 R80 10K R79 SDIO/SDA SDIO/SDA_INT VDD3.3 R81 MANMODE 0 A 0 R3 PINCONTROL SDO SDO_INT CSB CSB_BUF SAMTECTSW10608GS3PIN IRQ DNI R78 PINCONTROL SCLK_BUF P10 EEPROM ENA P8 1 2 3 VDD3.3 U5 74LVC541APW SERIAL_CLK SCL 24LC00-I/P 39K INTERNAL PULLDOWN SDIO_U VDD3.3 2.2K R42 R40 8 VDD3.3 7 6 5 VCC NC4 SCL SDA 1 2 3 GND NC1 NC2 NC3 VSS SDA 0 B 1 2 3 4 M2 U3 2.2K EEPROM GND P14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AN A LO G DE V CES TSW-105-08-G-T THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9557 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9557CE02 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 J.SCUTERI 2 SCALE NONE SHEET 1 2 OF 4 8 6 7 2 3 4 5 1 REVISIONS 0.1UF PIN 7 PIN 10 GND GND 0.1UF 0.1UF PIN 19 TP12 1 WHT TP13 1 WHT TP14 1 WHT TP15 1 WHT TP16 1 WHT TP17 1 WHT VDD3.3 PIN 40 C135 C119 VDD1.8 0.1UF PIN 34 GND C117 VDD1.8 PIN 31 APPROVED VDD3.3 0.1UF GND C71 VDD1.8 0.1UF GND GND C47 DATE D D C45 DESCRIPTION VDD1.8 VDD3.3 VDD1.8 VDD3.3 VDD1.8 REV 0.1UF 0.1UF C PIN 23 PIN 22 C110 C112 0.1UF GND C43 GND C49 GND SCATTER TEST POINTS AROUND BOARD GND GND 0.1UF PIN 24 C PIN 30 E1 1 VDD1.8 C162 0.1UF 2 600OHM VDD1.8_P6 DNI GND C163 0.1UF GND BYPASS CAPS & FERRITE BEADS E2 1 VDD1.8_P11 600OHM VDD3.3 C166 0.1UF B VDD3.3_P14 C19 GND TBD7343 N C12 P TBD0402 C78 TBD0402 C74 C70 C66 TBD0402 2 TBD0402 1 TBD0402 C64 E3 P VDD3.3 GND VDD3.3 VDD1.8 N C164 0.1UF 2 TBD7343 VDD1.8 GND 600OHM B CAPS ON BOT OF EVB CAPS ON TOP OF EVB GND TBD0402 C83 TBD0402 C77 TBD0402 C72 TBD0402 C67 C65 C63 TBD0402 VDD1.8_P17 TBD0402 2 TBD0402 1 VDD1.8 C52 E4 TBD0402 C48 VDD1.8 GND C168 0.1UF 600OHM GND CAPS FOR USB SECTION E5 0.1UF C23 0.1UF 0.1UF C21 0.1UF C16 C15 0.1UF 0.1UF C14 C13 0.1UF 0.1UF C11 C10 0.1UF 600OHM C9 VDD1.8_P18 0.1UF C170 0.1UF VDD3.3 2 C1 1 VDD1.8 GND GND A E6 1 VDD1.8 C172 0.1UF GND 2 600OHM A VDD1.8_P35 DNI C173 0.1UF AN A LO G DE V CES GND THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9557 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9557CE02 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 J.SCUTERI 2 SCALE NONE SHEET 1 3 OF 4 8 6 7 2 3 4 5 1 REVISIONS REV 1.8V REGULATOR U501 ADP7104 P504 GND 1 4VDC 2 Z5.530.3225.0 P5 8 VIN 7 PG 6 GND 5 EN 1 2 GND 3 SAMTECTSW10608GS3PIN VOUT SENSE GND NC PAD TP500 1 WHT 1 2 3 4 VDD1.8 C524 10UF DNI DNI U502 ADP7104 TP501 1 WHT GND 8 VIN 7 PG 6 GND 5 4VDC R527 100K P6 EN 1 2 GND 3 SAMTECTSW10608GS3PIN GND PAD GND VOUT SENSE GND NC PAD TP502 1 WHT APPROVED 1 2 3 4 VDD3.3 C525 10UF D DNI TP503 1 WHT GND R530 100K GND PAD DNI J500 R124.427.000 1 GND DNI J501 R124.427.000 1 VDD3.3 2 3 4 5 5 4 3 2 GND GND DNI DNI J502 R124.427.000 1 DC TO DC STEP DOWN C DATE 3.3V REGULATOR DNI D DESCRIPTION J503 R124.427.000 1 VDD1.8 2 3 4 5 C 5 4 3 2 GND GND 6V WALL WART (AC ADAPTER) P500 L500 6V_FILT 6VDC 1 2 3 N C500 470UF 4.7UF P PJ-102A C501 1UH P N DC TO DC STEP DOWN C502 470UF CR501 1 3 C509 GND GND 1UF BAT54 8.5V OVER PROTECTION CIRCUIT C511 P503 DNI 1 2 1 1 0 R531 2.0K R523 10K R514 IN PV EN 19 FREQ 20 C526 VREG C514 3 15 1UF R503 11 0 SYNC 2 MMBT3904 10 7 TRK 16 BST 14 SW 13 100NF R512 DH DL PGOOD CSL 2.21K C512 8 SS 6 FB 17 GND COMP CLKSET CLKOUT 18 33UH C513 ADP1828ACPZ R508 4.99K 4VDC R502 1K 3 R516 1000PF 2 22PF 100 GND 1 L501 C515 R506 4VDC 12 PAD SI2316BDS-T1-E3 5 GND PGND PAD 4 B Q500 9 0.01UF C508 3 GND C505 4.7UF Q501 C504 1UF 22UF 3 Q504 6V_FILT U500 10 C503 2 1 2 B 10 P9 A CR502 MMSZ4693T1G R532 1UF 1000PF C R510 28K R521 10K 0 R513 GND C506 1UF SI2316BDS-T1-E3 1 DNI 2 R507 28K GND A A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9557 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9557CE02 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 J.SCUTERI 2 SCALE NONE SHEET 1 4 OF 4