Sample & Buy Product Folder Support & Community Tools & Software Technical Documents PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface 1 Features • • 1 • • • • • • • • • • • Ultra Low Out-of-Band Noise Integrated High-Performance Audio PLL with BCK Reference to Generate SCK Internally Direct Line Level 2.1-VRMS Output No DC Blocking Capacitors Required Line Level Output Down to 1KΩ Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR Accepts 16-, 24-, and 32-Bit Audio Data PCM Data Formats: I2S, Left-Justified Automatic Power-Save Mode When LRCK And BCK Are Deactivated 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs Simple Configuration Using Hardware Pins Single-Supply Operation: 14 – 3.3 V Analog, 1.8 V or 3.3 V Digital Qualified in Accordance with AEC-Q100 2 Applications • • • • Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with singlesupply line drivers. The integrated line driver surpasses all other chargepump based line drivers by supporting loads down to 1 kΩ per pin. The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for popfree performance. Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz). Table 1. Device Information(1) A/V Receivers, DVD, BD Players Automotive Infotainment and Telematics HDTV Receivers Aftermarket Automotive Amplifiers PART NUMBER PACKAGE BODY SIZE (NOM) PCM5102A PCM5101A TSSOP (20) 5.50 mm × 4.40 mm PCM5100A 3 Description The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digitalto-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segmentDAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified System Diagram 2 I S PCM1863/5 BCK LRCK IN AUX PCM510xA PLL 2ch Single Ended Charge Pump IN MIC 2ch Single Ended Analog Sensor - Light Intensity - Ultrasonic - Battery Level BT Module MSP430 OUT LINE WiLAN chip 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified System Diagram .................................. Revision History..................................................... Device Comparison ............................................... Pin Configuration and Functions ......................... Specifications......................................................... 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 1 1 1 1 2 4 5 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings ............................................................ 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 11 Timing Requirements, XSMT .................................. 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 14 9.1 Overview ................................................................. 14 9.2 Functional Block Diagram ....................................... 14 9.3 Feature Description................................................. 14 9.4 Device Functional Modes........................................ 25 10 Applications and Implementation...................... 26 10.1 Application Information.......................................... 26 11 Power Supply Recommendations ..................... 28 11.1 Power Supply Distribution and Requirements ...... 11.2 Recommended Powerdown Sequence................. 11.3 External Power Sense Undervoltage Protection Mode ........................................................................ 11.4 Power-On Reset Function..................................... 11.5 PCM510xA Power Modes ..................................... 28 28 30 32 33 12 Layout................................................................... 34 12.1 Layout Guidelines ................................................. 34 13 Device and Documentation Support ................. 35 13.1 13.2 13.3 13.4 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ 35 35 35 35 14 Mechanical, Packaging, and Orderable Information ........................................................... 35 14.1 Mechanical Data ................................................... 35 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2015) to Revision C Page • Changed the device number from "PCM510x" to "PCM510xA" in the Simplified System Diagram ..................................... 1 • Changed typical performance table to reflect part differences accurately ............................................................................ 4 • Changed "Storage temperatures, Tstg" to "Operating junction temperature range at –40°C to 130°C" ................................. 6 • Changed "Storage temperature (Q1 devices) –40°C to 125°C" to "Storage temperatures, Tstg –65°C to 150°C" ................ 6 • Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ" to "1 kΩ".................................................................................................................................................................................. 6 • Changed the operating junction temperature range in the Recommended Operating Conditions from "MIN = –25°C MAX = 85°C" to "MIN = –40°C MAX = 130°C"....................................................................................................................... 6 • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Electrical Characteristics .................................................................................................................................................. 7 • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Typical Characteristics graphs section. .......................................................................................................................... 12 • Changed "MCK" to "SCK" at the PLL Clock in the Functional Block Diagram..................................................................... 14 • Added label "Mute Circuit" and ground symbols to pins DEMP and FMT in Figure 33 ...................................................... 26 Changes from Revision A (September 2012) to Revision B Page • Added ESD Rating table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information.............................................................................................................................................................................. 1 • Added items to show 1.8 V DVDD capability ......................................................................................................................... 1 • Changed the Features list. ..................................................................................................................................................... 1 • Changed "Operating temperature range " to "Operating junction temperature range" .......................................................... 6 • Deleted redundant PLL specification in the Recommended Operating Conditions .............................................................. 6 • Deleted "Intelligent clock error..." and "...for pop-free performance."................................................................................... 14 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 • Clarified clock generation explanation.................................................................................................................................. 24 • Clarified external SCK discussion. ....................................................................................................................................... 25 • Deleted "The PCM510xA disables the internal PLL when an external SCK is supplied." ................................................... 25 Changes from Original (May 2012) to Revision A Page • Changed layout of first two pages .......................................................................................................................................... 1 • Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical Characteristics ........................................................................................................................................................................ 8 • Changed reference to correct footnote................................................................................................................................. 10 • Changed tSCKH and tSCKL values to 9ns................................................................................................................................. 11 • Removed 48kHz sample rate with PLL-generated clock...................................................................................................... 25 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 3 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 6 Device Comparison Differences Between PCM510xA Devices PART NUMBER DYNAMIC RANGE SNR THD PCM5102A 112dB 112dB –93 dB PCM5101A 106 dB 106 dB –92 dB PCM5100A 100 dB 100 dB –90 dB Typical Performance (3.3 V Power Supply) PARAMETER SNR 112 / 106 / 100 dB Dynamic range 112 /106 / 100 dB THD+N at –1 dBFS –93/ –92 / –90 dB Full-scale single-ended output 2.1 VRMS (GND center) Normal 8× oversampling digital filter latency 20tS Low latency 8× oversampling digital filter latency 3.5tS Sampling frequency System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 4 PCM5102 / PCM5101 / PCM5100 Submit Documentation Feedback 8 kHz to 384 kHz Up to 50 MHz Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 7 Pin Configuration and Functions PW 20-Pin Package (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 9 — Analog ground AVDD 8 P Analog power supply, 3.3 V BCK 13 I Audio data bit clock input (1) CAPM 4 O Charge pump flying capacitor terminal for negative rail CAPP 2 O Charge pump flying capacitor terminal for positive rail CPGND 3 — Charge pump ground CPVDD 1 P Charge pump power supply, 3.3 V DEMP 10 I De-emphasis control for 44.1-kHz sampling rate (1): Off (Low) / On (High) DGND 19 — DIN 14 I Audio data input (1) DVDD 20 P Digital power supply, 1.8 V or 3.3 V FLT 11 I Filter select : Normal latency (Low) / Low latency (High) FMT 16 I Audio format selection : I2S (Low) / Left-justified (High) LDOO 18 P Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal LRCK 15 I Audio data word clock input (1) OUTL 6 O Analog output from DAC left channel OUTR 7 O Analog output from DAC right channel SCK 12 I System clock input (1) VNEG 5 O Negative charge pump rail terminal for decoupling, –3.3 V XSMT 17 I Soft mute control (1): Soft mute (Low) / soft un-mute (High) (1) Digital ground Failsafe LVCMOS Schmitt trigger input Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 5 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply voltage Digital input voltage MIN MAX AVDD, CPVDD, DVDD –0.3 3.9 LDO with DVDD at 1.8 V –0.3 2.25 DVDD at 1.8 V –0.3 2.25 DVDD at 3.3 V –0.3 3.9 UNIT V Analog input voltage –0.3 3.9 Operating junction temperature range –40 130 °C Storage temperature, Tstg –65 150 °C 8.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions MIN NOM MAX AVDD Analog power supply voltage range Referenced to AGND (1) VCOM mode 3 3.3 3.46 VREF mode 3.2 3.3 3.46 DVDD Digital power supply voltage range Referenced to DGND (1) 1.8 V DVDD 1.65 1.8 1.95 3.3 V DVDD 3.1 3.3 3.46 CPVDD Charge pump supply voltage range Referenced to CPGND (1) 3.1 3.3 3.46 MCLK Master clock frequency LOL, LOR Stereo line output load resistance CLOUT Digital output load capacitance TJ Operating junction temperature range (1) 50 1 10 V V V MHz kΩ 10 –40 UNIT pF 130 °C All grounds on board are tied together; they must not differ in voltage by more than 0.2 V max, for any combination of ground signals. 8.4 Thermal Information THERMAL METRIC (1) PW 20 PINS RθJA Junction-to-ambient thermal resistance 91.2 RθJC(top) Junction-to-case (top) thermal resistance 25.3 RθJB Junction-to-board thermal resistance 42 ψJT Junction-to-top characterization parameter 1 ψJB Junction-to-board characterization parameter 41.5 RθJC(bot) Junction-to-case (bottom) thermal resistance — (1) 6 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 8.5 Electrical Characteristics Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 16 24 32 24 UNIT Bits Data Format (PCM Mode) Audio data bit length 16 fS (1) Sampling frequency 8 fSCK System clock frequency Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 32 Bits 384 kHz 50 MHz Digital Input/Output for non-Q1 Consumer Grade Devices Logic family: 3.3 V LVCMOS compatible VIH VIL IIH IIL VOH VOL 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –4 mA 0.8×DVDD IOL = 4 mA 0.22×DVDD V µA V Logic family 1.8 V LVCMOS compatible VIH VIL IIH IIL VOH VOL 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –2 mA 0.8×DVDD IOL = 2 mA 0.22×DVDD V µA V Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible VIH VIL IIH IIL VOH VOL 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –4 mA 0.8×DVDD IOL = 4 mA 0.22×DVDD V µA V Logic family 1.8 V LVCMOS compatible VIH VIL IIH IIL VOH VOL (1) 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –2 mA IOL = 2 mA 0.8×DVDD 0.3×DVDD V µA V One sample time is defined as the reciprocal of the sampling frequency. 1tS = 1/fS Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 7 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCM5102A –93 –83 dB PCM5101A –92 –82 PCM5100A –90 –80 PCM5102A –93 PCM5101A –92 Dynamic Performance (PCM Mode) (2) (3) fS = 48 kHz THD+N at –1 dBFS (3) fS = 96 kHz and 192 kHz PCM5100A PCM5102A Dynamic range (3) EIAJ, A-weighted, fS = 48 PCM5101A kHz PCM5100A –90 106 112 100 106 95 100 PCM5102A 112 EIAJ, A-weighted, fS = 96 PCM5101A kHz and 192 kHz PCM5100A 106 100 PCM5102A Signal-to-noise ratio (3) 112 EIAJ, A-weighted, fS = 48 PCM5101A kHz PCM5100A 106 100 PCM5102A 112 EIAJ, A-weighted, fS = 96 PCM5101A kHz and 192 kHz PCM5100A Signal to noise ratio with analog mute (3) (4) EIAJ, A-weighted, fS = 48 kHz fS = 96 kHz fS = 192 kHz (2) (3) (4) 8 100 113 EIAJ, A-weighted, fS = 96 kHz and 192 kHz fS = 48 kHz Channel separation 106 123 123 PCM5102A 100 109 PCM5101A 95 103 PCM5100A 90 97 PCM5102A 109 PCM5101A 103 PCM5100A 97 PCM5102A 109 PCM5101A 103 PCM5100A 97 Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF; Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted channel separation: 20-Hz HPF, 20-kHz AES17 LPF. Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode. Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see recommended output filter). Assert XSMT or both L-ch and R-ch PCM data are Bipolar Zero. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Output voltage 2.1 VRMS Gain error –6 ±2 6 % of FSR Gain error on Q1 Automotive Grade Devices –7 ±2 7 % of FSR Gain mismatch, channel-to-channel –6 ±2 6 % of FSR Gain mismatch, channel-to-channel on Q1 Devices –6 ±2 6 % of FSR PCM5100/1 bipolar zero error At bipolar zero –5 ±1 5 mV PCM5102 Bipolar zero error At bipolar zero –2 ±1 2 mV Load impedance 1 kΩ Filter Characteristics–1: Normal Pass band 0.45fS Stop band 0.55fS Stop band attenuation –60 Pass-band ripple ±0.02 Delay time 20tS dB s Filter Characteristics–2: Low Latency Pass band 0.47fS Stop band 0.55fS Stop band attenuation –52 Pass-band ripple ±0.0001 Delay time 3.5tS dB s Power Supply Requirements DVDD Digital supply voltage Target DVDD = 1.8 V 1.65 1.8 1.95 DVDD Digital supply voltage Target DVDD = 3.3 V 3 3.3 3.6 AVDD Analog supply voltage 3 3.3 3.6 CPVDD Charge-pump supply voltage 3 3.3 3.6 IDD DVDD supply current at 1.8 V (5) IDD IDD IDD DVDD supply current at 1.8 V (6) DVDD supply current at 1.8 V (7) DVDD supply current at 3.3 V (5) IDD DVDD supply current at 3.3 V (6) IDD DVDD supply current at 3.3 V (7) IDD (5) (6) (7) AVDD / CPVDD supply current (5) fS = 48 kHz 7 fS = 96 kHz 8 fS = 192 kHz 9 fS = 48 kHz 7 fS = 96 kHz 8 fS = 192 kHz 9 Standby 7 fS = 96 kHz 8 fS = 192 kHz 9 fS = 48 kHz 8 fS = 96 kHz 9 VDC mA mA 0.3 fS = 48 kHz VDC mA 12 mA 13 mA fS = 192 kHz 10 Standby 0.5 0.8 fS = 48 kHz 11 16 fS = 96 kHz 11 fS = 192 kHz 11 mA mA Input is Bipolar Zero data. Input is 1 kHz –1 dBFS data. Power Down Mode Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 9 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER IDD IDD AVDD / CPVDD supply current (6) AVDD / CPVDD supply current (7) Power dissipation, DVDD = 1.8 V (5) Power dissipation, DVDD = 1.8 V (6) Power dissipation, DVDD = 1.8 V (7) Power dissipation, DVDD = 3.3 V (5) Power dissipation, DVDD = 3.3 V (6) Power dissipation, DVDD = 3.3 V (7) 10 Submit Documentation Feedback TYP MAX fS = 48 kHz TEST CONDITIONS 22 32 fS = 96 kHz 22 fS = 192 kHz 22 fS = n/a 0.2 0.4 fS = 48 kHz 49 185 fS = 96 kHz 51 fS = 192 kHz 53 fS = 48 kHz 85 fS = 96 kHz 87 fS = 192 kHz 89 fS = n/a (Power Down Mode) MIN 60 fS = 96 kHz 63 fS = 192 kHz 66 fS = 48 kHz 99 fS = 96 kHz 102 fS = 192 kHz 106 fS = n/a (Power Down Mode) mA mA mW 187 mW 1 fS = 48 kHz UNIT mW 92.4 mW 148.5 2 mW 4 mW Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 8.6 Timing Requirements Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise. MIN tSCY System clock pulse cycle time tSCKH System clock pulse width, High tSCKL System clock pulse width, Low TYP 20 DVDD = 1.8 V 8 DVDD = 3.3 V 9 DVDD = 1.8 V 8 DVDD = 3.3 V 9 MAX UNIT 1000 ns ns ns tSCKH "H" 0.7*DVDD System Clock (SCK) 0.3*DVDD "L" tS CK L tSCY Figure 1. Timing Requirements for SCK Input 8.7 Timing Requirements, XSMT MIN TYP MAX UNIT tr Rise time 20 ns tf Fall time 20 ns 0.9 * DVDD XSMT 0.1 * DVDD tr <20ns tf <20ns Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 11 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 8.8 Typical Characteristics 10 10 -10 -10 -30 -30 THD+N (dB) THD+N (dB) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. -50 -50 -70 -70 -90 -90 -110 -100 -80 -60 -40 Input Level (dBFS) -20 -110 -100 0 -20 -40 -40 -60 -60 Amplitude (dB) Amplitude (dB) -40 -20 0 Figure 4. PCM5102 THD+N versus Input Level -20 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 5 10 Frequency (kHz) 15 0 20 Figure 5. PCM5101 FFT Plot using a 1-kHz tone (–60dBFS) from DC to 20 kHz -20 -20 -40 -40 -60 -60 -80 -100 -120 5 10 Frequency (kHz) 15 20 Figure 6. PCM5102 FFT Plot using a 1-kHz tone (–60dBFS) from DC to 20 kHz Amplitude (dB) Amplitude (dB) -60 Input Level (dBFS) Figure 3. PCM5101 THD+N versus Input Level -80 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 Frequency (kHz) 15 20 Figure 7. PCM5101 FFT Plot At Bipolar Zero Data (BPZ) 12 -80 Submit Documentation Feedback 0 5 10 Frequency (kHz) 15 20 Figure 8. PCM5102 FFT Plot at BPZ Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Typical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. -20 -40 Amplitude (dB) Amplitude (dB) -60 -80 -100 -120 -140 -160 -180 0 5 Frequency (kHz) 0 0 -20 -20 -40 -40 -60 -80 -100 15 20 Figure 10. PCM5102 FFT Plot at BPZ With Analog Mute (AMUTE) Amplitude (dB) Amplitude (dB) Figure 9. PCM5101 FFT Plot at BPZ With Analog Mute (AMUTE) 10 Frequency (kHz) -60 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 200 Frequency (kHz) 250 300 Figure 11. PCM5101 FFT Plot using a 1-kHz tone (–60dBFS) from DC to 300 kHz Copyright © 2012–2015, Texas Instruments Incorporated 0 50 100 150 200 Frequency (kHz) 250 300 Figure 12. PCM5102 FFT Plot using a 1-kHz tone (–60dBFS) from DC to 300 kHz Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 13 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 9 Detailed Description 9.1 Overview The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure, the device digitally attenuates the data (or last known good data) and then mutes the analog circuit. Compared with existing DAC technology, the PCM510xA devices offer up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements to 3 MHz). The PCM510xA devices accept industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384 kHz are supported. Analog Mute Analog Mute 32bit ûModulator Audio Interface Current Segment DAC I/V Zero Data Detector Current Segment DAC I/V DIN (i2s) 8x Interpolation Filter 9.2 Functional Block Diagram LINE OUT Advanced Mute Control Clock Halt Detection PCM510xA LRCK BCK Power Supply PLL Clock SCK UVP/Reset POR Ch. Pump CPVDD (3.3V) AVDD (3.3V) DVDD (1.8V or 3.3V) GND CAPP CAPM VNEG 9.3 Feature Description 9.3.1 Terminology Sampling frequency is symbolized by fS. Full scale is symbolized by FS. Sample time as a unit is symbolized by tS. 9.3.2 Audio Data Interface 9.3.2.1 Audio Serial Interface The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM510xA on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for left/right is given by the format selected. 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Feature Description (continued) Table 2. PCM510xA Audio Data Formats, Bit Depths and Clock Rates CONTROL MODE FORMAT DATA BITS Hardware Control I2S/LJ 32, 24, 20, 16 MAX LRCK FREQUENCY [fS] SCK RATE [x fS] BCK RATE [x fS] Up to 192 kHz 128 – 3072 (≤50MHz) 64, 48, 32 384 kHz 64, 128 64, 48, 32 The PCM510xA requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock. If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed. If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed. 9.3.2.2 PCM Audio Data Formats The PCM510xA supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified. All formats require binary twos-complement, MSB-first audio data; up to 32-bit audio data is accepted. 1tS R-channel L-channel LRCK BCK Audio data word = 16-bit, BCK = 32, 48, 64fS 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB 2 23 Audio data word = 24-bit, BCK = 48, 64fS - , 1 2 2 24 1 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64fS 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB Figure 13. Left Justified Audio Data Format Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 15 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 1tS LRCK L- channel R- channel BCK Audio data word = 16-bit, BCK = 32, 48, 64fS 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB Audio data word = 24-bit, BCK = 48, 64fS 1 2 23 1 24 2 23 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64fS 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB I2S Data Format; L-channel = LOW, R-channel = HIGH Figure 14. I2S Audio Data Format 9.3.2.3 Zero Data Detect The PCM510xA has a zero-data detect function. When the device detects continuous zero data, it enters a full analog mute condition. The PCM510xA counts zero data over 1024 LRCKs (21ms @ 48kHz) before setting analog mute. In Hardware mode, the device uses default values. By default, Both L-ch and R-ch have to be zero data for zero data detection to begin the muting process etc. 9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute) An external digital host controls the PCM510xA soft mute function by driving the XSMT pin with a specific minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM510xA requires tr and tf times of less than 20ns. In the majority of applications, this is no problem, however, traces with high capacitance may have issues. When the XSMT pin is shifted from high to low (3.3 V to 0 V), a soft digital attenuation ramp begins. –1-dB attenuation is then applied every sample time from 0 dBFS to –∞. The soft attenuation ramp takes 104 samples. When the XSMT pin is shifted from low to high (0 V to 3.3 V), a soft digital “un-mute” is started. 1-dB gain steps are applied every sample time from –∞ to 0 dBFS. The un-mute takes 104 samples. In systems where XSMT is not required, it can be directly connected to AVDD. 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 9.3.4 Audio Processing 9.3.4.1 Interpolation Filter The PCM510xA provides two types of interpolation filter. Users can select which filter to use by using the FLT pin (pin 11). Table 3. Digital Interpolation Filter Options FLT Pin Description 0 FIR normal x8/x4/x2/x1 interpolation filters 1 IIR low-latency x8/x4/x2/x1 interpolation filters The normal x8 / x4 / x2 / x1(bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table 4. Normal x8 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Value (Typ) Filter gain stop band 0.55fS ….. 7.455fS Filter group delay Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 4 −0.4 0 50 100 150 200 250 Samples 300 350 G023 G012 Figure 15. Normal x8 Interpolation Filter Frequency Response Copyright © 2012–2015, Texas Instruments Incorporated 400 Figure 16. Normal x8 Interpolation Filter Impulse Response Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 17 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.1 0.2 0.3 Frequency (x fS) 0.4 0.5 G034 Figure 17. Normal x8 Interpolation Filter Passband Ripple 18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 The normal x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table 5. Normal x4 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Value (Typ) Filter gain stop band 0.55fS ….. 7.455fS Filter group delay Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 20 40 60 80 100 Samples 120 140 G020 G009 Figure 18. Normal x4 Interpolation Filter Frequency Response 160 Figure 19. Normal x4 Interpolation Filter Impulse Response 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.5 Frequency (x fS) 1.0 G031 Figure 20. Normal x4 Interpolation Filter Passband Ripple Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 19 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table 6. Normal x2 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Value (Typ) Filter gain stop band 0.55fS ….. 7.455fS Filter group delay Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 10 20 30 40 50 60 Samples 70 80 100 G017 G006 Figure 21. Normal x2 Interpolation Filter Frequency Response 90 Figure 22. Normal x2 Interpolation Filter Impulse Response 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.5 1.0 Frequency (x fS) 1.5 2.0 G028 Figure 23. Normal x2 Interpolation Filter Passband Ripple 20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 The low-latency x8 / x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table 7. Low Latency x8 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Filter gain stop band 0.55fS ….. 7.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter group delay 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 −0.6 4 0 50 100 150 200 250 Samples 300 350 400 G022 G011 Figure 24. Low Latency x8 Interpolation Filter Frequency Response Figure 25. Low Latency x8 Interpolation Filter Impulse Response 0.00010 0.00008 0.00006 Amplitude (dB) 0.00004 0.00002 0.00000 −0.00002 −0.00004 −0.00006 −0.00008 −0.00010 0.0 0.1 0.2 0.3 Frequency (x fS) 0.4 0.5 G033 Figure 26. Low Latency x8 Interpolation Filter Passband Ripple Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 21 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table 8. Low Latency x4 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Filter gain stop band 0.55fS ….. 3.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter group delay 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 −0.6 4 0 20 40 60 80 100 Samples 120 140 160 180 G019 G008 Figure 27. Low Latency x4 Interpolation Filter Frequency Response Figure 28. Low Latency x4 Interpolation Filter Impulse Response 0.0001 0.00008 0.00006 Amplitude (dB) 0.00004 0.00002 0 −0.00002 −0.00004 −0.00006 −0.00008 −0.0001 0.0 0.5 Frequency (x fS) 1.0 G030 Figure 29. Low Latency x4 Interpolation Filter Passband Ripple 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Table 9. Low Latency x2 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Filter gain stop band 0.55fS ….. 1.455fS Filter group delay Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s space 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 10 20 30 40 50 60 Samples 70 80 90 100 G016 G005 Figure 30. Low Latency x2 Interpolation Filter Frequency Response Figure 31. Low Latency x2 Interpolation Filter Impulse Response 0.0001 0.00008 0.00006 Amplitude (dB) 0.00004 0.00002 0 −0.00002 −0.00004 −0.00006 −0.00008 −0.0001 0.0 0.5 Frequency (x fS) 1.0 G030 Figure 32. Low Latency x2 Interpolation Filter Passband Ripple Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 23 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 9.3.5 Reset and System Clock Functions 9.3.5.1 Clocking Overview The PCM510xA devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio interface in one form or another. The data flows at the sample rate (fS). Once the data is brought into the serial audio interface, it gets processed, interpolated and modulated all the way to 128 × fS before arriving at the current segments for the final digital to analog conversion. The serial audio interface typically has 4 connections SCK (system master clock), BCK (bit clock), LRCK (left right word clock) and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to operate with or without an external SCK. 9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S) The PCM510xA requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM510xA systemclock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, e.g. 88.2kHZ and 96kHz are detected as "double rate," 32kHz, 44.1kHz and 48kHz will be detected as "single rate". The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 10 shows examples of system clock frequencies for common audio sampling rates. SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode, available only in the PCM512x, PCM514x, and PCM5242 devices, by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz [LRCK] and 2.8224 MHz [BCK]). Table 10. System Master Clock Inputs for Audio Related Clocks System Clock Frequency (fSCK) (MHz) Sampling Frequency 64 fS 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1024 fS 1152 fS 1536 fS 2048 fS 3072 fS 8 kHz – (1) 1.024 (2) 1.536 (2) 2.048 3.072 4.096 6.144 8.192 9.216 12.288 16.384 24.576 16 kHz – (1) 2.048 (2) 3.072 (2) 4.096 6.144 8.192 12.288 16.384 18.432 24.576 36.864 49.152 32 kHz – (1) 4.096 (2) 6.144 (2) 8.192 12.288 16.384 24.576 32.768 36.864 49.152 – (1) – (1) 44.1 kHz – (1) 5.6488 (2) 8.4672 (2) 11.2896 16.9344 22.5792 33.8688 45.1584 – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) 48 kHz 88.2 kHz 96 kHz 176.4 kHz 192 kHz 384 kHz (1) (2) 24 – (1) – (1) – (1) – (1) – (1) 24.576 6.144 (2) 11.2896 12.288 (2) (2) 22.579 24.576 49.152 9.216 (2) 16.9344 18.432 33.8688 36.864 – (1) 12.288 22.5792 24.576 45.1584 49.152 – (1) 18.432 33.8688 36.864 – (1) – (1) – (1) 24.576 45.1584 49.152 – (1) – (1) – (1) 36.864 – (1) – (1) – (1) – (1) – (1) 49.152 – (1) – (1) – (1) – (1) – (1) This system clock rate is not supported for the given sampling frequency. This system clock rate is supported by PLL mode. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM) The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference. The internal PLL is disabled as soon as an external SCK is supplied. The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 11 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK. Table 11. BCK Rates (MHz) by LRCK Sample Rate for PCM510xA PLL Operation BCK (fS) Sample f (kHz) 32 64 8 – – 16 – 1.024 32 1.024 2.048 44.1 1.4112 2.8224 48 1.536 3.072 96 3.072 6.144 192 6.144 12.288 384 12.288 24.576 9.4 Device Functional Modes 9.4.1 External SCK and PLL Activation As discussed in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM), the internal PLL of a PCM510xA device supplies a SCK if an external SCK is not present at powerup. 9.4.1.1 Interpolation Filter Modes Interpolation-filter options are controlled by the FLT pin. See Table 3. 9.4.1.2 44.1kHz De-emphasis De-emphasis control for 44.1-kHz fS is controlled by the DEMP pin. See Pin Configuration and Functions. 9.4.1.3 Audio Format Audio format is selected by the FMT pin. See Pin Configuration and Functions. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 25 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information PCM Audio Source 10.1.1 Typical Applications FLT DEMP SCK AGND BCK AVDD AGND DIN PCM510x 0.1mF 10mF + Right Channel Line Output 3.3VA 470W OUTR LRCK OUTL FMT VNEG AGND Mute Circuit XSMT CAPM LDOO CPGND DGND CAPP 2.2mF Left Channel Line Output 2.2mF 470W 0.1mF DVDD 3.3V 10mF + 2.2nF AGND + 10mF 2.2nF 0.1mF + 10mF 3.3VA AGND CPVDD 0.1mF Figure 33. Simplified Schematic, Hardware-Controlled Subsystem 10.1.1.1 Example Design Requirements • Device control method: hardware control – Normal filter latency – I2S digital audio interface – Power rail monitoring from the system 12-V rail to mute early on system power loss • Single-ended 2.1-VRMS analog outputs • 3-wire I2S interface (BCK PLL) • Single 3.3-V supply 10.1.1.2 Detailed Design Procedure • Device control method: See Pin Configuration and Functions and Audio Processing. – Normal filter latency: FLT pin tied low – Audio format selection: FMT pin tied low • Clock and PLL setup (See Reset and System Clock Functions). Ensure incoming BCK meets minimum requirements. • XSMT pin setup for 12-V monitoring (See External Power Sense Undervoltage Protection Mode). • Single-supply 3.3-V operation (See Setting Digital Power Supplies and I/O Voltage Rails) 26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Application Information (continued) 10.1.1.3 Application Curve -20 -40 Amplitude (dB) -60 -80 -100 -120 -140 -160 0 5 10 Frequency (kHz) 15 20 Figure 34. PCM5101A FFT Plot, DC to 20 kHz with a 1 kHz, –60dBFS Input Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 27 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 11 Power Supply Recommendations 11.1 Power Supply Distribution and Requirements The PCM510xA devices are powered through the following pins: AVDD 3.3V CPVDD 3.3V DAC Charge Pump Reference Oscillator DVDD (1.8V or 3.3v) LDOO 1.8V Digital Core (^W[, Logic etc) Digital IO Analog Circuits 1.8V LDO PLL Clock Halt Detect Digital Circuits Power Circuits Line Driver PCM186x Figure 35. Power Distribution Tree within PCM510xA Table 12. Power Supply Pin Descriptions NAME USAGE / DESCRIPTION AVDD Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on. DVDD Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO. CPVDD Charge Pump Voltage Supply - must be 3.3 V LDOO Output from the onchip LDO. Should be used with a 0.1-µF decoupling cap. Can be driven (used as power input) with a 1.8-V supply to bypass the onchip LDO for lower power consumption. AGND Analog ground DGND Digital ground 11.2 Recommended Powerdown Sequence Under certain conditions, the PCM510xA devices can exhibit some pop on power down. Pops are caused by a device not having enough time to detect power loss and start the muting process. The PCM510xA devices have two auto-mute functions to mute the device upon power loss (intentional or unintentional). XSMT = 0 When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute. This process takes 150 sample times (ts) + 0.2 ms. Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute much faster than a 48-kHz system. Clock Error Detect When clock error is detected on the incoming data clock, the PCM510xA devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete, the PCM510xA outputs are hard muted to ground. 11.2.1 Planned Shutdown These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways: 1. Assert XSMT low 150 tS + 0.2 ms before power is removed. 28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Recommended Powerdown Sequence (continued) 3.3V VDD 0V 150tS + 0.2ms High XSMT Low High I2 S Clocks SCK, BCK, LRCK Low Time Figure 36. Assert XSMT 2. Stop I2S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 37. 3.3V VDD 0V High XSMT Low 3 ms High I2S Clocks SCK, BCK, LRCK Low Time Figure 37. Stop I2C Clocks 11.2.2 Unplanned Shutdown Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 38 shows how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 29 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Recommended Powerdown Sequence (continued) MCU GPIO “mute” signal GND XSMT Linear Regulator 110V / 220V SMPS 6V PCM5xxx Audio DAC 3.3V 10 F GND GND Figure 38. Using the XSMT Pin 11.3 External Power Sense Undervoltage Protection Mode NOTE External Power Sense Undervoltage Protection Mode is supported only when DVDD = 3.3 V. The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC system supply using a voltage divider created with two resistors. (See Figure 39 ) • If the XSMT pin makes a transition from “1” to “0” over 6 ms or more, the device switches into external undervoltage protection mode. This mode uses two trigger levels: – When the XSMT pin level reaches 2 V, soft mute process begins. – When the XSMT pin level reaches 1.2 V, analog mute engages, regardless of digital audio level, and analog shutdown begins. (DAC and related circuitry powers down). If XSMT is moved from "1" to "0" in 20 ns or less, then the device will interpret it as a digital controlled request to mute. It will perform a soft mute, then move to standby. A timing diagram to show this is shown in Figure 40. NOTE The XSMT input pin voltage range is from –0.3 V to DVDD+0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD+0.3 V. For example, if the PCM510xA is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMT during ideal power supply conditions is 3.3 V. A voltage spike higher than 14.4 V causes a voltage greater than 3.6 V (DVDD+0.3) on the XSMT pin, potentially damaging the device. Providing the divider is set appropriately, any DC voltage can be monitored. 30 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 External Power Sense Undervoltage Protection Mode (continued) System VDD 12V supply 7.25kW XSMT 2.75kW Figure 39. XSMT in External UVP Mode Digital Attenuation Followed by Analog Mute 0.9 * DVDD 2.0 V Analog Mute XSMT 1.2 V 0.1 * DVDD tf Figure 40. XSMT Timing for Undervoltage Protection The trigger voltage values for the soft mute and hard mute are shown in Table 13. The range of values will vary from device to device, but typical thresholds are shown. XSMT should be set up to nominally be 3.3 V along with DVDD, but derived from a higher system power supply rail. Table 13. Distribution of Voltage Thresholds MIN TYP MAX Soft Mute Threshold Voltage 2.0 V 2.2 V 0.9×DVDD Hard Mute Threshold Voltage 0.1×DVDD 0.9 V 1.2 V Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 31 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 11.4 Power-On Reset Function Power-On Reset, DVDD 3.3-V Supply The PCM510xA includes a power-on reset function shown in Figure 41. With VDD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digital interpolation filter selected. 3.3V 2.8V AVDD, DVDD, CPVDD Internal Reset Reset Removal Internal Reset 4 ms I2S Clocks SCK, BCK, LRCK Figure 41. Power-On Reset Timing, DVDD = 3.3 V Power-On Reset, DVDD 1.8-V Supply The PCM510xA includes a power-on reset function shown in Figure 42 operating at DVDD = 1.8 V. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state. 3.3V 2.8V AVDD, CPVDD 1.8V 1.5V DVDD, LDOO Internal Reset Reset Removal Internal Reset 4 ms I2S Clocks SCK, BCK, LRCK Figure 42. Power-On Reset Timing, DVDD = 1.8 V 32 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 11.5 PCM510xA Power Modes 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails The internal digital core of the PCM510xA devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply. DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core. For systems that require 3.3 V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO. When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply. 11.5.2 Power Save Modes The PCM510xA devices offer two power-save modes: standby and power-down. When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA device automatically enters standby mode. The DAC and line driver are also powered down. When BCK and LRCK remain at a low level for more than 1 second, the PCM510xA device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode. When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 33 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 12 Layout 12.1 Layout Guidelines • • • • The PCM510xA family of devices are simple to layout. Most engineers use a shared common ground for an entire device. GND can be consider AGND and DGND connected. Good system partitioning should keep digital clock and interface traces away from the analog outputs for highest analog performance. This reduces any high speed clock return currents influencing the analog outputs. Power supply and charge pump decoupling capacitors should be placed as close as possible to the device. The top layer should be used for routing signals, whilst the bottom layer can be used for GND. Bottom Layer Copper Fill (GND) Top Layer Copper Fill (GND) 1 CPVDD 2 CAPP 3 CPGND 4 CAPM 5 VNEG 6 OUTL 7 OUTR 8 AVDD 9 AGND 3.3V 10 DEMP 3.3V DVDD 20 DGND 19 LDOO 18 XSMT 17 FMT 16 LRCK 15 DIN 14 BCK 13 SCK 12 FLT 11 12V Direct to Processor or full high/low for control pins Figure 43. PCM510x Layout Example 34 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 14. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY PCM5100A Click here Click here Click here Click here Click here PCM5101A Click here Click here Click here Click here Click here PCM5102A Click here Click here Click here Click here Click here PCM5100A-Q1 Click here Click here Click here Click here Click here PCM5101A-Q1 Click here Click here Click here Click here Click here PCM5102A-Q1 Click here Click here Click here Click here Click here 13.2 Community Resources E2E™ Audio Converters Forum TI E2E Community 13.3 Trademarks Directpath is a trademark of Texas Instruments, Inc. System Two Cascade, Audio Precision are trademarks of Audio Precision. 13.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, see the left-hand navigation. 14.1 Mechanical Data Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 35 PACKAGE OPTION ADDENDUM www.ti.com 7-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) PCM5100APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100AQPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 P5100AQ1 PCM5101APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A PCM5101APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A PCM5101AQPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 P5101AQ1 PCM5102APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102AQPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 P5102AQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-May-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PCM5100A, PCM5100A-Q1, PCM5101A, PCM5101A-Q1, PCM5102A, PCM5102A-Q1 : • Catalog: PCM5100A, PCM5101A, PCM5102A • Automotive: PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM5100APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5100AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5101APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5101AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5102APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5102AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM5100APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCM5100AQPWRQ1 TSSOP PW 20 2000 367.0 367.0 38.0 PCM5101APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCM5101AQPWRQ1 TSSOP PW 20 2000 367.0 367.0 38.0 PCM5102APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCM5102AQPWRQ1 TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated