Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 SN74LVC1G08 Single 2-Input Positive-AND Gate 1 Features • 1 • • • • • • • • • 3 Description 2 Available in the Ultra Small 0.64-mm Package (DPW) With 0.5-mm Pitch Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Provides Down Translation to VCC Max tpd of 3.6 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • • • • • • • • • • • • • • • • • • • ATCA Solutions Active Noise Cancellation (ANC) Barcode Scanner Blood Pressure Monitor CPAP Machine Cable Solutions DLP 3D Machine Vision, Hyperspectral Imaging, Optical Networking, and Spectroscopy E-Book Embedded PC Field Transmitter: Temperature or Pressure Sensor Fingerprint Biometrics HVAC: Heating, Ventilating, and Air Conditioning Network-Attached Storage (NAS) Server Motherboard and PSU Software Defined Radio (SDR) TV: High-Definition (HDTV), LCD, and Digital Video Communications System Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card X-ray: Baggage Scanner, Medical, and Dental This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G08 device performs the Boolean function or Y = A • B or Y = A + B in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm. white space white space Device Information(1) DEVICE NAME SN74LVC1G08 PACKAGE BODY SIZE SOT-23 (5) 2.9mm × 1.6mm SC70 (5) 2.0mm × 1.25mm X2SON (4) 0.8mm × 0.8mm SON (6) 1.45mm × 1.0mm SON (6) 1.0mm × 1.0mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 4 4 5 5 6 6 6 7 7 7 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, CL = 15 pF ...................... Switching Characteristics, 1.8 V and 2.5 V .............. Switching Characteristics, 3.3 V and 5 V ................. Operating Characteristics.......................................... Typical Characteristics ............................................ Parameter Measurement Information .................. 8 8 Detailed Description ............................................ 10 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 Application and Implementation ........................ 11 9.1 Application Information............................................ 11 9.2 Typical Application ................................................. 11 10 Power Supply Recommendations ..................... 12 11 Layout................................................................... 12 11.1 Layout Guidelines ................................................. 12 11.2 Layout Example .................................................... 12 12 Device and Documentation Support ................. 13 12.1 Trademarks ........................................................... 13 12.2 Electrostatic Discharge Caution ............................ 13 12.3 Glossary ................................................................ 13 13 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History Changes from Revision X (March 2014) to Revision Y Page • Updated Handling Ratings table. ........................................................................................................................................... 4 • Added Thermal Information table. ......................................................................................................................................... 5 • Added Typical Characteristics. .............................................................................................................................................. 7 • Added Detailed Description section. .................................................................................................................................... 10 • Added Application and Implementation section. ................................................................................................................. 11 • Added Power Supply Recommendations section. .............................................................................................................. 12 • Added Layout section. ......................................................................................................................................................... 12 Changes from Revision W (July 2013) to Revision X Page • Added Applications. ................................................................................................................................................................ 1 • Added Device Information table. ............................................................................................................................................ 1 • Moved Tstg to Handling Ratings table. .................................................................................................................................... 4 Changes from Revision V (November 2012) to Revision W • 2 Page Added parameter values for –40 to 125°C temperature ratings............................................................................................. 6 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 SN74LVC1G08 www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014 5 Pin Configuration and Functions DBV PACKAGE (TOP VIEW) A 1 B 2 GND 3 DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A VCC 5 5 1 B 2 GND 3 VCC A B Y 4 B A 1 5 3 2 4 3 4 Y A 1 6 VCC B GND 2 5 3 4 NC Y Y DPW PACKAGE (TOP VIEW) GND VCC 2 GND 4 5 1 DSF PACKAGE (TOP VIEW) VCC Y YZP PACKAGE (BOTTOM VIEW) GND 3 4 B 2 A 1 5 Y VCC DRY PACKAGE (TOP VIEW) A 1 6 VCC B 2 5 NC GND 3 4 Y NC – No internal connection See mechanical drawings for dimensions. Pin Functions PIN DESCRIPTION NAME DBV, DCK, DRL, YZP DRY, DSF DPW A 1 1 2 Input B 2 2 1 Input GND 3 3 3 Ground Y 4 4 4 Output VCC 5 6 5 Power pin NC 5 Not connected Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 3 SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) VI Input voltage range –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 6.2 Handling Ratings MIN Tstg Storage temperature range V(ESD) (1) (2) 4 Electrostatic discharge MAX –65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 UNIT °C V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 SN74LVC1G08 www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014 6.3 Recommended Operating Conditions (1) VCC Operating Supply voltage MAX 5.5 Data retention only V 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage UNIT 1.5 VCC = 1.65 V to 1.95 V VIH MIN 1.65 1.7 VCC = 3 V to 3.6 V V 2 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 4.5 V to 5.5 V 0.3 × VCC VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V Low-level output current Δt/Δv –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V Input transition rise or fall rate (1) mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA mA –24 VCC = 4.5 V IOL V ns/V 5 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.4 Thermal Information SN74LVC1G08 THERMAL METRIC (1) DBV DCK DRL DRY YZP DPW 5 PINS 5 PINS 5 PINS 6 PINS 5 PINS 4 PINS RθJA Junction-to-ambient thermal resistance 207.6 283.1 242.9 438.8 130 340 RθJCtop Junction-to-case (top) thermal resistance 145.2 92.3 77.5 276.8 54 215 RθJB Junction-to-board thermal resistance 53.5 60.9 77.5 271.7 51 294 ψJT Junction-to-top characterization parameter 37.5 1.7 9.6 83.8 1 41 ψJB Junction-to-board characterization parameter 53.1 60.1 77.3 271.4 50 294 RθJCbot Junction-to-case (bottom) thermal resistance – – – – – 250 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 5 SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MIN IOH = –100 μA VOH 1.65 V to 5.5 V VCC – 0.1 VCC – 0.15 1.2 1.2 IOH = –8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3V MAX V 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 3.8 0.4 0.4 0.55 0.55 0.55 0.55 0 to 5.5 V ±5 ±5 μA 3V IOL = 24 mA IOL = 32 mA 4.5 V VI = 5.5 V or GND Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, ΔICC One input at VCC – 0.6 V, Other inputs at VC C or GND Ci VI = VCC or GND (1) 3.8 UNIT TYP IOH = –32 mA IOL = 16 mA II MIN 1.65 V IOH = –24 mA A or B inputs MAX IOH = –4 mA IOH = –16 mA VOL –40°C to 125°C RECOMMENDED –40°C to 85°C VCC IO = 0 V 0 ±10 ±10 μA 1.65 V to 5.5 V 10 10 μA 3 V to 5.5 V 500 500 μA 3.3 V 4 4 pF All typical values are at VCC = 3.3 V, TA = 25°C. 6.6 Switching Characteristics, CL = 15 pF over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 1.5 7.2 0.7 4.4 0.8 3.6 0.8 3.4 UNIT ns 6.7 Switching Characteristics, 1.8 V and 2.5 V (1) over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 4) –40°C to 125°C –40°C to 85°C (1) 6 PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y RECOMMENDED VCC = 1.8 V ± 0.15 V VCC = 1.8 V ± 0.15 V –40°C to 125°C –40°C to 85°C RECOMMENDED VCC = 2.5 V ± 0.2 V UNIT VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX MIN MAX MIN MAX 2.4 8 2.4 10 1.1 5.5 1.1 7 ns On products compliant to MIL-PRF-38535, this parameter is not production tested. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 SN74LVC1G08 www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014 6.8 Switching Characteristics, 3.3 V and 5 V (1) over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4) –40°C to 125°C –40°C to 85°C (1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y VCC = 3.3 V ± 0.3 V –40°C to 125°C –40°C to 85°C RECOMMENDED VCC = 3.3 V ± 0.3 V RECOMMENDED VCC = 5 V ± 0.5 V UNIT VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 1 4.5 1 6 1 4 1 5 ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 6.9 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 21 24 26 31 Power dissipation capacitance UNIT pF 6.10 Typical Characteristics 8 6 TPD 7 5 6 TPD - ns TPD - ns 4 3 5 4 3 2 2 1 1 TPD 0 -100 0 -50 0 50 Temperature - °C 100 150 0 1 D001 Figure 1. TPD Across Temperature at 3.3V Vcc 2 3 Vcc - V 4 5 Product Folder Links: SN74LVC1G08 D002 Figure 2. TPD Across Vcc at 25°C Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated 6 7 SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 SN74LVC1G08 www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014 Parameter Measurement Information (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 9 SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC1G08 device contains one 2-input positive AND gate device and performs the Boolean function Y = A • B or Y = A + B . This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. 8.2 Functional Block Diagram 8.3 Feature Description • • • • Wide operating voltage range. – Operates from 1.65 V to 5.5 V. Allows down voltage translation. Inputs and outputs accept voltages to 5.5 V. Ioff feature allows voltages on the inputs and outputs when VCC is 0 V. 8.4 Device Functional Modes Function Table INPUTS 10 A B OUTPUT Y H H H L X L X L L Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 SN74LVC1G08 www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014 9 Application and Implementation 9.1 Application Information The SN74LVC1G08 is a high drive CMOS device that can be used for implementing AND logic with a high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translate down to VCC. 9.2 Typical Application AND Logic Function Basic LED Driver VCC VCC A- uC or Logic A- uC or Logic Y- uC or Logic B- uC or Logic LVC1G08 B- uC or Logic LVC1G08 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed (IO max) per output and should not exceed total current (continuous current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings table. – Outputs should not be pulled above VCC. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 11 SN74LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com Typical Application (continued) 9.2.3 Application Curves 10 8 Icc Icc Icc Icc 1.8V 2.5V 3.3V 5V Icc - mA 6 4 2 0 -2 -20 0 20 40 Frequency - MHz 60 80 D003 Figure 5. Icc vs Frequency 10 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in the Recommended Operating Conditions table. Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or is more convenient. 11.2 Layout Example VCC Unused Input Input Output Unused Input Output Input 12 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 SN74LVC1G08 www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC1G08 13 PACKAGE OUTLINE SN74LVC1GXX and SN74AUP1GXX DPW0005A-C01 X2SON - 0.4 mm max height SCALE 12.000 PLASTIC SMALL OUTLINE - NO LEAD 0.85 0.75 B A 0.85 0.75 PIN 1 INDEX AREA 0.4 MAX C SEATING PLANE NOTE 4 (0.1) 0.05 0.00 0.25 0.1 THERMAL PAD 2 4 2X 0.48 NOTE 4 3 5 1 4X 0.27 0.17 (0.06) 3X 0.32 0.23 0.27 0.17 0.1 C A 0.05 C B 4221849/A 12/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. The size and shape of this feature may vary. www.ti.com EXAMPLE BOARD LAYOUT SN74LVC1GXX and SN74AUP1GXX DPW0005A-C01 X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.78) SYMM 4X (0.42) ( 0.1) VIA 0.05 MIN ALL AROUND TYP 1 5 4X (0.22) SYMM 4X (0.26) (0.48) 3 2 4 (R0.05) TYP 4X (0.06) ( 0.25) LAND PATTERN EXAMPLE SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP SOLDER MASK DEFINED SCALE:60X 4221849/A 12/2014 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN SN74LVC1GXX and SN74AUP1GXX DPW0005A-C01 X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42) 4X (0.22) 4X (0.06) 5 1 ( 0.24) 4X (0.26) SYMM (0.21) TYP SOLDER MASK EDGE 3 2 (R0.05) TYP (0.48) 4 SYMM (0.78) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X 4221849/A 12/2014 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LVC1G08DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C085 ~ C08F ~ C08K ~ C08R ~ C08T) (C08P ~ C08S) SN74LVC1G08DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C085 ~ C08F ~ C08K ~ C08R ~ C08T) (C08P ~ C08S) SN74LVC1G08DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C085 ~ C08F ~ C08K ~ C08R ~ C08T) (C08P ~ C08S) SN74LVC1G08DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C085 ~ C08F ~ C08K ~ C08R) (C08H ~ C08P ~ C08S) SN74LVC1G08DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C085 ~ C08F ~ C08K ~ C08R) (C08H ~ C08P ~ C08S) SN74LVC1G08DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C085 ~ C08F ~ C08K ~ C08R) (C08H ~ C08P ~ C08S) SN74LVC1G08DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) SN74LVC1G08DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) SN74LVC1G08DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) SN74LVC1G08DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Sep-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LVC1G08DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) SN74LVC1G08DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) SN74LVC1G08DPWR ACTIVE X2SON DPW 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 M4 SN74LVC1G08DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE7 ~ CER) SN74LVC1G08DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CE7 ~ CER) SN74LVC1G08DRY2 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CE SN74LVC1G08DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CE SN74LVC1G08DSF2 ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CE SN74LVC1G08DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 CE SN74LVC1G08YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (CE ~ CE2 ~ CE7) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G08 : • Automotive: SN74LVC1G08-Q1 • Enhanced Product: SN74LVC1G08-EP NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 13-Aug-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G08DBVR SOT-23 DBV 5 3000 178.0 9.0 SN74LVC1G08DBVR SOT-23 DBV 5 3000 178.0 SN74LVC1G08DBVT SOT-23 DBV 5 250 178.0 SN74LVC1G08DBVT SOT-23 DBV 5 250 SN74LVC1G08DCKR SC70 DCK 5 SN74LVC1G08DCKT SC70 DCK SN74LVC1G08DCKT SC70 DCK SN74LVC1G08DCKT SC70 W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 9.2 3.3 3.2 1.55 4.0 8.0 Q3 9.2 3.3 3.2 1.55 4.0 8.0 Q3 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 DCK 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 SN74LVC1G08DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74LVC1G08DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3 SN74LVC1G08DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3 SN74LVC1G08DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC1G08DSF2 SON DSF 6 5000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3 SN74LVC1G08DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 SN74LVC1G08DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1G08YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Aug-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G08DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G08DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G08DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G08DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G08DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G08DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G08DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G08DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74LVC1G08DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1G08DRY2 SON DRY 6 5000 202.0 201.0 28.0 SN74LVC1G08DRY2 SON DRY 6 5000 184.0 184.0 19.0 SN74LVC1G08DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74LVC1G08DSF2 SON DSF 6 5000 202.0 201.0 28.0 SN74LVC1G08DSF2 SON DSF 6 5000 184.0 184.0 19.0 SN74LVC1G08DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74LVC1G08YZPR DSBGA YZP 5 3000 182.0 182.0 20.0 Pack Materials-Page 2 MECHANICAL DATA PLASTIC SMALL OUTLINE NO-LEAD DSF (S-PX2SON-N6) 1.05 0.95 A B PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 2X 0.7 4 SYMM 4X 0.35 6 1 (0.1) PIN 1 ID 6X 6X 0.45 0.35 0.22 0.12 0.07 0.05 C A C B 4208186/F 10/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.858 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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