3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3

SN54LVTH16244A, SN74LVTH16244A
www.ti.com
SCBS142U – MAY 1992 – REVISED OCTOBER 2013
3.3-V ABT 16-Bit Buffers/Drivers With 3-State Outputs
Check for Samples: SN54LVTH16244A, SN74LVTH16244A
FEATURES
DESCRIPTION
•
The 'LVTH16244A devices are 16-bit buffers and line
drivers designed for low-voltage (3.3-V) VCC
operation, but with the capability to provide a TTL
interface to a 5-V system environment. These devices
can be used as four 4-bit buffers, two 8-bit buffers, or
one 16-bit buffer. These devices provide true outputs
and symmetrical active-low output-enable (OE)
inputs.
1
2
•
•
•
•
•
•
•
•
Members of the Texas Instruments Widebus™
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not
recommended.
When VCC is between 0 and 1.5 V, the devices are in
the high-impedance state during power up or power
down. However, to ensure the high-impedance state
above 1.5 V, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
These devices are fully specified for hot-insertion
applications using Ioff and power-up 3-state. The Ioff
circuitry disables the outputs, preventing damaging
current backflow through the devices when they are
powered down. The power-up 3-state circuitry places
the outputs in the high-impedance state during power
up and power down, which prevents driver conflict.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1992–2013, Texas Instruments Incorporated
SN54LVTH16244A, SN74LVTH16244A
SCBS142U – MAY 1992 – REVISED OCTOBER 2013
www.ti.com
SN54LVTH16244A . . . WD PACKAGE
SN74LVTH16244A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2
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1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
Copyright © 1992–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVTH16244A SN74LVTH16244A
SN54LVTH16244A, SN74LVTH16244A
www.ti.com
SCBS142U – MAY 1992 – REVISED OCTOBER 2013
TERMINAL ASSIGNMENTS (1)
(56-Ball GQL/ZQL Package)
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
blk
blk
blk
(1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
2OE
B
1Y2
1Y1
GND
GND
1A1
1A2
C
1Y4
1Y3
VCC
VCC
1A3
1A4
D
2Y2
2Y1
GND
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
VCC
VCC
4A2
4A1
J
4Y3
4Y4
GND
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
NC – No internal connection
xxxxx
xxxxx
xxxxx
TERMINAL ASSIGNMENTS (1)
(54-Ball GRD/ZRD Package)
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
1Y1
NC
1OE
2OE
NC
1A1
A
B
1Y3
1Y2
NC
NC
1A2
1A3
B
C
2Y1
1Y4
VCC
VCC
1A4
2A1
D
2Y3
2Y2
GND
GND
2A2
2A3
E
3Y1
2Y4
GND
GND
2A4
3A1
F
3Y3
3Y2
GND
GND
3A2
3A3
E
G
4Y1
3Y4
VCC
VCC
3A4
4A1
F
H
4Y3
4Y2
NC
NC
4A2
4A3
J
4Y4
NC
4OE
3OE
NC
4A4
C
D
G
H
J
(1)
Copyright © 1992–2013, Texas Instruments Incorporated
NC – No internal connection
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Product Folder Links: SN54LVTH16244A SN74LVTH16244A
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SN54LVTH16244A, SN74LVTH16244A
SCBS142U – MAY 1992 – REVISED OCTOBER 2013
www.ti.com
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
4
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Product Folder Links: SN54LVTH16244A SN74LVTH16244A
SN54LVTH16244A, SN74LVTH16244A
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SCBS142U – MAY 1992 – REVISED OCTOBER 2013
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
VO
Voltage range applied to any output in the high state (2)
–0.5
VCC + 0.5
IO
Current into any output in the low state
IO
Current into any output in the high state (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
Package thermal impedance (4)
θJA
SN54LVTH16244A
96
SN74LVTH16244A
128
SN54LVTH16244A
48
SN74LVTH16244A
64
DGG package
70
DGV package
58
DL package
63
GQL/ZQL package
42
GRD/ZRD package
Tstg
(1)
(2)
(3)
(4)
V
V
V
°C/W
36
Storage temperature range
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
SN54LVTH16244A
SN74LVTH16244A
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
–25
–32
mA
IOL
Low-level output current
48
64
mA
Δt/Δv
Input transition rise or fall rate
10
10
ns/V
Δt/ΔVCC
Power-up ramp rate
200
TA
Operating free-air temperature
–55
(1)
2
V
2
Outputs enabled
V
μs/V
200
125
–40
V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1992–2013, Texas Instruments Incorporated
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SN54LVTH16244A, SN74LVTH16244A
SCBS142U – MAY 1992 – REVISED OCTOBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN TYP
VIK
VOH
VCC = 2.7 V,
II = –18 mA
VCC = 2.7 V to 3.6
V,
IOL = –100 μA
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
VCC = 3 V
MAX
MIN TYP
–1.2
VCC – 0.2
VOL
VCC = 3 V
Data
inputs
VCC – 0.2
Ioff
II(hold)
Data
inputs
2.4
V
2.4
V
2
2
0.2
0.2
0.2
IOL = 24 mA
0.5
0.5
0.5
IOL = 16 mA
0.4
0.4
0.4
IOL = 32 mA
0.5
0.5
0.5
IOL = 48 mA
0.55
0.55
0.55
10
10
VCC = 3.6 V,
VI = VCC or GND
±1
VI = VCC
VI = 2 V
±1
1
–5
±100
–5
μA
±100
75
75
75
–75
–75
–75
500
–750
500
–750
VCC = 3.6 V ,
VI = 0 to 3.6 V
IOZH
VCC = 3.6 V,
VO = 3 V
IOZL
VCC = 3.6 V,
VO = 0.5 V
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
±100 (
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
±100 (
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
5
5
5
μA
–5
–5
μA
3)
Outputs low
Outputs disabled
μA
–5
3)
Outputs high
V
μA
1
–5
VI or VO = 0 to 4.5 V
VI = 0.8 V
±1
1
VI = 0
(2)
–1.2
IOL = 100 μA
50
VCC = 3 V
MAX
2
VI = 5.5 V
VCC = 0,
UNIT
VCC – 0.2
2.4
VCC = 0 or 3.6 V,
VCC = 3.6 V
MIN TYP
–1.2
IOL = 64 mA
II
MAX
IOH = –32 mA
VCC = 2.7 V
Control
inputs
Recommended
–40°C to 125C
SN74LVTH16244A
–40°C to 85°C
SN74LVTH16244A
SN54LVTH16244A
±100
±100
μA
±100
±100
μA
0.19
0.19
5
5
0.19
5
0.19
0.19
0.19
0.2
0.2
0.2
mA
ΔICC (4)
VCC = 3 V to 3.6 V, One input at VCC – 0.6
V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0 V
4
4
4
pF
Co
VO = 3 V or 0 V
9
9
9
pF
(1)
(2)
(3)
(4)
6
mA
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
On products compliant to MIL-PRF-38535, this parameter does not apply.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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Product Folder Links: SN54LVTH16244A SN74LVTH16244A
SN54LVTH16244A, SN74LVTH16244A
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SCBS142U – MAY 1992 – REVISED OCTOBER 2013
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) (1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
Y
OE
Y
OE
Y
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
Recommended
–40°C to 125C
SN74LVTH16244A
–40°C to 85°C
SN74LVTH16244A
SN54LVTH16244A
MAX
VCC = 3.3 V
± 0.3 V
MIN TYP
VCC = 2.7 V
MAX
MIN
MAX
UNIT
VCC = 3.3 V
± 0.3 V
MIN TYP
VCC = 2.7 V
MIN
MAX
1.1
4.4
4.6
1.2
2.3
3.2
3.7
1.2
2.3
MAX
4.4
4.6
1.1
3.6
3.9
1.2
2
3.2
3.7
1.2
2
3.6
3.9
1.1
4.6
5.4
1.2
2.6
4
5
1.2
2.6
4.6
5.4
1.1
5.4
6.2
1.2
2.7
4
5
1.2
2.7
5.4
6.2
1.6
5.7
6.2
2.2
3.3
4.5
5
2.2
3.3
5.7
6.2
1.2
5
4.7
2
3.1
4.2
4.4
2
3.1
5
4.7
tsk(LH)
0.5
0.5
tsk(HL)
0.5
0.5
MIN
MAX
ns
ns
ns
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
Copyright © 1992–2013, Texas Instruments Incorporated
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SN54LVTH16244A, SN74LVTH16244A
SCBS142U – MAY 1992 – REVISED OCTOBER 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPLZ
tPZL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
2.7 V
Output
Control
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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SCBS142U – MAY 1992 – REVISED OCTOBER 2013
REVISION HISTORY
Changes from Revision T (November 2006) to Revision U
Page
•
Updated document to new TI data sheet format - no specification changes. ...................................................................... 1
•
Removed ordering information. ............................................................................................................................................ 1
•
Updated operating temperature range. ................................................................................................................................. 5
Copyright © 1992–2013, Texas Instruments Incorporated
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9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9668501QXA
ACTIVE
CFP
WD
48
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9668501QX
A
SNJ54LVTH16244
AWD
5962-9668501VXA
ACTIVE
CFP
WD
48
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9668501VX
A
SNV54LVTH16244
AWD
74LVTH16244ADGGRE4
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
74LVTH16244ADGGRG4
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
74LVTH16244ADLRG4
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
SN74LVTH16244ADGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
SN74LVTH16244ADGVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LL244A
SN74LVTH16244ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
SN74LVTH16244ADLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
SN74LVTH16244ADLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVTH16244A
SN74LVTH16244AGQLR
OBSOLETE
BGA
MICROSTAR
JUNIOR
GQL
56
TBD
Call TI
Call TI
-40 to 85
SN74LVTH16244AGRDR
OBSOLETE
BGA
MICROSTAR
JUNIOR
GRD
54
TBD
Call TI
Call TI
-40 to 85
SN74LVTH16244AZQLR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQL
56
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
1000
Addendum-Page 1
LL244A
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVTH16244AZRDR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZRD
54
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LL244A
SNJ54LVTH16244AWD
ACTIVE
CFP
WD
48
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9668501QX
A
SNJ54LVTH16244
AWD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVTH16244A, SN54LVTH16244A-SP, SN74LVTH16244A :
• Catalog: SN74LVTH16244A, SN54LVTH16244A
• Enhanced Product: SN74LVTH16244A-EP, SN74LVTH16244A-EP
• Military: SN54LVTH16244A
• Space: SN54LVTH16244A-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
15.8
1.8
12.0
24.0
Q1
SN74LVTH16244ADGGR TSSOP
DGG
48
2000
330.0
24.4
SN74LVTH16244ADGVR TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
SN74LVTH16244AZQLR BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
SN74LVTH16244AZRDR BGA MI
CROSTA
R JUNI
OR
ZRD
54
1000
330.0
16.4
5.8
8.3
1.55
8.0
16.0
Q1
SN74LVTH16244ADLR
SSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVTH16244ADGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74LVTH16244ADGVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
SN74LVTH16244ADLR
SSOP
DL
48
1000
367.0
367.0
55.0
SN74LVTH16244AZQLR BGA MICROSTAR
JUNIOR
ZQL
56
1000
336.6
336.6
28.6
SN74LVTH16244AZRDR BGA MICROSTAR
JUNIOR
ZRD
54
1000
336.6
336.6
28.6
Pack Materials-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
48
1
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
25
24
NO. OF
LEADS**
48
56
A MAX
0.640
(16,26)
0.740
(18,80)
A MIN
0.610
(15,49)
0.710
(18,03)
4040176 / D 10/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only
Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA
GDFP1-F56 and JEDEC MO -146AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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