Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 SN65LVDS93A FlatLink™ Transmitter 1 Features 2 Applications • • • • • 1 • • • • • • • • • • • Industrial Temperature Range –40°C to 85°C LVDS Display Serdes Interfaces Directly to LCD Display Panels With Integrated LVDS Package Options: 4.5-mm × 7-mm BGA, and 8.1mm × 14-mm TSSOP 1.8 V up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic Processors Transfer Rate up to 135 Mpps (Mega Pixels Per Second); Pixel Clock Frequency Range 10 MHz to 135 MHz Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI Operates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz 28 Data Channels Plus Clock In Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage Differential Consumes Less Than 1 mW When Disabled Selectable Rising or Falling Clock Edge Triggered Inputs ESD: 5-kV HBM Supports Spread Spectrum Clocking (SSC) Compatible With all OMAP™2x, OMAP3x, and DaVinci™ Application Processors LCD Display Panel Drivers UMPC and Netbook PCs Digital Picture Frames 3 Description The SN65LVDS93A LVDS SerDes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928). When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. Device Information(1) PART NUMBER SN65LVDS93A PACKAGE BODY SIZE (NOM) TSSOP (56) 14.00 mm × 6.10 mm BGA MICROSTAR JUNIOR (56) 7.00 mm × 4.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. RGB Video System Using Discrete LVDS TX 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 9 1 1 1 2 3 3 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 7 Timing Requirements ................................................ 8 Switching Characteristics .......................................... 9 Typical Characteristics ............................................ 11 Parameter Measurement Information ................ 12 Detailed Description ............................................ 16 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 18 10 Application and Implementation........................ 19 10.1 Application Information.......................................... 19 10.2 Typical Application ................................................ 20 11 Power Supply Recommendations ..................... 27 12 Layout................................................................... 27 12.1 Layout Guidelines ................................................. 27 12.2 Layout Example .................................................... 29 13 Device and Documentation Support ................. 31 13.1 13.2 13.3 13.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 14 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2011) to Revision B • Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Original (August 2009) to Revision A Page • Deleted all maximum values from ICC - Supply current (average).......................................................................................... 8 • Changed ten - Enable Time, unit value From: 6 ns To: 6 µs................................................................................................... 9 2 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 5 Description (continued) The SN65LVDS93A device requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level. The SN65LVDS93A is characterized for operation over ambient air temperatures of –40°C to 85°C. 6 Pin Configuration and Functions DGG Package 56-Pin TSSOP (Top View) ZQL Package 56-Ball BGA MICROSTAR (Top View) IOVCC 1 56 D5 2 3 55 54 D7 GND D8 4 53 5 52 GND D1 6 51 D0 D9 D10 7 50 8 49 D27 GND VCC D11 9 10 48 47 D12 11 46 Y0P Y1M D13 12 45 Y1P GND D14 13 44 14 15 43 42 LVDSVCC GND Y2M 16 41 17 18 40 39 19 38 D19 GND 20 21 D20 D6 D15 D16 D2 4 3 2 1 D8 D7 D5 D4 D2 D1 D9 GND D6 D3 D0 D27 D11 VCC D10 GND Y0P Y0M D13 D12 IOVCC GND Y1P Y1M D14 GND GND D16 D15 Y2P Y2M D17 D18 CLKSEL GND CLKP CLKM D19 GND IOVCC GND Y3P Y3M D20 D21 D25 SHTDN PLLVCC GND D22 D23 D24 D26 CLKIN GND J H Y0M G F LVDSVCC E D C 37 CLKOUTP Y3M Y3P 36 GND 35 34 GND D21 22 23 D22 24 33 D23 25 32 IOVCC D24 D25 26 31 27 30 28 29 D17 D18 5 K Y2P CLKOUTM CLKSEL 6 D4 D3 B A PLLVCC GND SHTDN CLKIN D26 GND Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 3 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Pin Functions - TSSOP PIN NAME NO. I/O DESCRIPTION I Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger (CLKSEL = VIL). 31 I Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. 40 O CLKOUTP 39 O Differential LVDS pixel clock output. Output is high-impedance when SHTDN is pulled low (de-asserted). D0 51 D1 52 D2 54 D3 55 D4 56 D5 2 D6 3 D7 4 D8 6 D9 7 CLKSEL 17 CLKIN CLKOUTM D10 8 D11 10 D12 11 D13 12 D14 14 D15 15 D16 16 D17 18 D18 19 D19 20 D20 22 D21 23 D22 24 D23 25 D24 27 D25 28 D26 30 D27 50 GND 5, 13, 21, 29, 33, 35, 36, 43, 49, 53 IOVCC 1, 26 I Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC. Power Supply (1) I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing) LVDSVCC 44 3.3-V LVDS output analog supply PLLVCC 34 3.3-V PLL analog supply SHTDN 32 I VCC 9 Power Supply (1) (1) 4 Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation. 3.3-V digital supply voltage For a multilayer pcb, TI recommends keeping one common GND layer underneath the device and connecting all ground terminals directly to this plane. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 Pin Functions - TSSOP (continued) PIN NAME NO. Y0M 48 Y1M 46 Y2M 42 Y0P 47 Y1P 45 Y2P 41 Y3M 38 Y3P 37 I/O DESCRIPTION O Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted) O Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. Pin Functions - BGA MICROSTAR BALL NAME NO. CLKIN A2 CLKM D1 CLKP D2 CLKSEL D4 D0 J2 D1 K1 D2 K2 D3 J3 D4 K3 D5 K4 D6 J4 D7 K5 D8 K6 D9 J6 D10 H4 D11 H6 D12 G5 D13 G6 D14 F6 D15 E5 D16 E6 D17 D6 D18 D5 D19 C6 D20 B6 D21 B5 D22 A6 D23 A5 D24 A4 D25 B4 D26 A3 D27 J1 I/O CMOS IN with pulldn LVDS Out DESCRIPTION Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. Differential LVDS pixel clock output. Output is high-impedance when SHTDN is pulled low (de-asserted). CMOS IN with pulldn Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger (CLKSEL = VIL). CMOS IN with pulldn Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 5 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Pin Functions - BGA MICROSTAR (continued) BALL NAME NO. I/O A1, B1, C3, C5, F2, F5, J5, D3, G3, H3 GND IOVCC C4, G4 DESCRIPTION Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC. Power Supply (1) I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing) LVDSVCC F1 3.3-V LVDS output analog supply PLLVCC B2 3.3-V PLL analog supply SHTDN B3 VCC H5 Y0M H1 Y1M G1 Y2M E1 Y0P H2 Y1P G2 Y2P E2 Y3M C1 Y3P -(1) C2 CMOS IN with pulldn Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation. Power Supply (1) 3.3-V digital supply voltage LVDS Out Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted) LVDS Out Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. E3, E4, F3, F4 – Not connected For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. 7 Specifications 7.1 Absolute Maximum Ratings (1) MIN MAX UNIT Supply voltage, VCC, IOVCC, LVDSVCC, PLLVCC (2) –0.5 4 V Voltage at any output terminal –0.5 VCC + 0.5 V Voltage at any input terminal –0.5 IOVCC + 0.5 V Continuous power dissipation See Thermal Information Storage temperature, Tstg (1) (2) –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the GND terminals. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±5000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 LVDS output supply voltage, LVDSVCC 3 3.3 3.6 PLL analog supply voltage, PLLVCC 3 3.3 3.6 1.62 1.8 / 2.5 / 3.3 3.6 IO input reference supply voltage, IOVCC Power supply noise on any VCC terminal UNIT V 0.1 High-level input voltage, VIH Low-level input voltage, VIL IOVCC = 1.8 V IOVCC/2 + 0.3 V IOVCC = 2.5 V IOVCC/2 + 0.4 V IOVCC = 3.3 V IOVCC/2 + 0.5 V V IOVCC = 1.8 V IOVCC/2 – 0.3 V IOVCC = 2.5 V IOVCC/2 – 0.4 V IOVCC = 3.3 V Differential load impedance, ZL Operating free-air temperature, TA V IOVCC/2 – 0.5 V 90 132 Ω –45 85 °C 7.4 Thermal Information SN65LVDS93A THERMAL METRIC (1) ZQL (BGA MICROSTAR) DGG (TSSOP) 56 PINS 56 PINS RθJA Junction-to-ambient thermal resistance 67.1 62.1 RθJC(top) Junction-to-case (top) thermal resistance 25.2 18.4 RθJB Junction-to-board thermal resistance 31.0 31.1 ψJT Junction-to-top characterization parameter 0.8 0.8 ψJB Junction-to-board characterization parameter 30.3 30.8 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VT Input voltage threshold |VOD| Differential steady-state output voltage magnitude TEST CONDITIONS MIN TYP (1) MAX IOVCC/2 250 UNIT V 450 mV RL = 100 Ω, See Figure 7 Δ|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) Steady-state common-mode output voltage VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current VIH = IOVCC IIL Low-level input current VIL = 0 V ±10 μA VOY = 0 V ±24 mA 1 See Figure 7 tR/F (Dx, CLKin) = 1 ns 1.125 35 1.375 mV V 35 mV 25 μA IOS Short-circuit output current VOD = 0 V ±12 mA IOZ High-impedance state output current VO = 0 V to VCC ±20 μA Rpdn Input pulldown integrated resistor on all inputs (Dx, CLKSEL, SHTDN, CLKIN) IOVCC = 1.8 V 200 IOVCC = 3.3 V 100 IQ Quiescent current (1) Disabled, all inputs at GND; SHTDN = VIL 2 kΩ 100 μA All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 7 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT SHTDN = VIH, RL = 100 Ω (5 places), grayscale pattern (Figure 8) VCC = 3.3 V, fCLK = 75 MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 51.9 I(IOVCC) with IOVCC = 3.3 V 0.4 I(IOVCC) with IOVCC = 1.8 V 0.1 mA SHTDN = VIH, RL = 100 Ω (5 places), 50% transition density pattern (Figure 8), VCC = 3. 3 V, fCLK = 75 MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 53.3 I(IOVCC) with IOVCC = 3.3 V 0.6 I(IOVCC) with IOVCC = 1.8 V 0.2 mA SHTDN = VIH, RL = 100 Ω (5 places), worstcase pattern (Figure 9), VCC = 3.6 V, fCLK = 75 MHz ICC Supply current (average) I(VCC) + I(PLLVCC) + I(LVDSVCC) 63.7 I(IOVCC) with IOVCC = 3.3 V 1.3 I(IOVCC) with IOVCC = 1.8 V 0.5 mA SHTDN = VIH, RL = 100 Ω (5 places), worstcase pattern (Figure 9), fCLK = 100 MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 81.6 I(IOVCC) with IOVCC = 3.6 V 1.6 I(IOVCC) with IOVCC = 1.8 V 0.6 mA SHTDN = VIH, RL = 100 Ω (5 places), worstcase pattern (Figure 9), fCLK = 135 MHz CI I(VCC) + I(PLLVCC) + I(LVDSVCC) 102.2 I(IOVCC) with IOVCC = 3.6 V 2.1 I(IOVCC) with IOVCC = 1.8 V 0.8 Input capacitance mA 2 pF 7.6 Timing Requirements Input clock period, tc Input clock modulation MIN MAX UNIT 7.4 100 ns w/ modulation frequency 30 kHz 8% w/ modulation frequency 50 kHz High-level input clock pulse width duration, tw 6% 0.4 tc Input signal transition time, tt Data set up time, D0 through D27 before CLKIN (See Figure 6) Data hold time, D0 through D27 after CLKIN 8 Submit Documentation Feedback 0.6 tc ns 3 ns 2 ns 0.8 ns Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 7.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN TYP (1) MAX –0.1 0 0.1 ns UNIT t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1 /7 tc – 0.1 1 /7 tc + 0.1 ns t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) 2 /7 tc – 0.1 2 /7 tc + 0.1 ns t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) 3 /7 tc – 0.1 3 /7 tc + 0.1 ns t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) 4 /7 tc – 0.1 4 /7 tc + 0.1 ns t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) 5 /7 tc – 0.1 5 /7 tc + 0.1 ns t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) 6 /7 tc – 0.1 6 /7 tc + 0.1 ns tc(o) Output clock period Δtc(o) Output clock cycle-to-cycle jitter See Figure 10, tC = 10 ns, |Input clock jitter| < 25 ps (2) tc (3) tC = 10 ns; clean reference clock, see Figure 11 ±26 tC = 10 ns with 0.05UI added noise modulated at 3 MHz, see Figure 11 ±44 tC = 7.4 ns; clean reference clock, see Figure 11 ±35 tC = 7.4 ns with 0.05UI added noise modulated at 3 MHz, see Figure 11 ±42 ns ps tw High-level output clock pulse duration tr/f Differential output voltage transition time (tr or tf) See Figure 7 ten Enable time, SHTDN↑ to phase lock (Yn valid) f(clk) = 135 MHz, See Figure 12 6 µs tdis Disable time, SHTDN↓ to off-state (CLKOUT high-impedance) f(clk) = 135 MHz, See Figure 13 7 ns (1) (2) (3) 4 /7 tc 225 ns 500 ps All typical values are at VCC = 3.3 V, TA = 25°C. |Input clock jitter| is the magnitude of the change in the input clock period. The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 9 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Dn CLKIN or CLKIN CLKOUT Previous cycle Next Current cycle Y0 D0-1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8-1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19-1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27-1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. Typical SN65LVDS93A Load and Shift Sequences 10 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 7.8 Typical Characteristics 100 800 90 700 80 600 Period Clock Jitter - ps-pp ICC - Average Supply Current - mA Output Jitter VCC = 3.6V 70 60 50 VCC = 3.3V 40 VCC = 3V Input Jitter 500 400 300 200 100 30 0 0.01 20 10 30 50 70 90 110 130 0.10 1 10 f(mod) - Input Modular Frequency - MHz fclk - Clock Frequency - MHz Total device current (using grayscale pattern) over pixel clock frequency CLK frequency during text = 100 MHz Figure 2. Average Grayscale ICC vs Clock Frequency PRBS Data Signal V - Voltage - 80mV/div CLKL Signal Figure 3. Output Clock Jitter vs Input Clock Jitter tk - Time - 1 ns/div Clock signal = 135 MHz Figure 4. Typical PRBS Output Signal Over One Clock Period Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 11 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com 8 Parameter Measurement Information LVDSVCC IOVCC 5W D or SHTDN 50W 7V YnP or YnM 10kW 7V 300kW Figure 5. Equivalent Input and Output Schematic Diagrams tsu thold Dn CLKIN All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0V. Figure 6. Setup and Hold Time Definition 12 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 Parameter Measurement Information (continued) 49.9W ± 1% (2 PLCS) YP VOD VOC YM 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V Figure 7. Test Load and Voltage Definitions for LVDS Outputs CLKIN D0,8,16 D1,9,17 D2,10,18 D3,11,19 D4-7,12-15,20-23 D24-27 The 16 grayscale test pattern test device power consumption for a typical display pattern. Figure 8. 16 Grayscale Test Pattern Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 13 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Parameter Measurement Information (continued) T CLKIN EVEN Dn ODD Dn The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Figure 9. Worst-Case Power Test Pattern t7 CLKIN CLKOUT t6 t5 t4 t3 t2 t0 Yn t1 VOD(H) ~2.5V CLKOUT or Yn 1.40V CLKIN 0.00V ~0.5V VOD(L) t7 t0-6 CLKOUT is shown with CLKSEL at high-level. CLKIN polarity depends on CLKSEL input level. Figure 10. SN65LVDS93A Timing Definitions 14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 Parameter Measurement Information (continued) + Reference Device Under Test VCO + Modulation v(t) = A sin(2 pfmodt) HP8656B Signal Generator, 0.1 MHz-990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz-4200 MHz Device Under Test RF Output Modulation Input CLKIN DTS2070C Digital TimeScope CLKOUT Input Figure 11. Output Clock Jitter Test Set Up CLKIN Dn ten SHTDN Invalid Yn Valid Figure 12. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 13. Disable Time Waveforms Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 15 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com 9 Detailed Description 9.1 Overview FlatLink™ is an LVDS SerDes data transmission system. The SN65LVDS93A takes in three (or four) data words each containing seven single-ended data bits, and converts this to an LVDS serial output. Each serial output runs at seven times that of the parallel data rate. The deserializer (receiver) device operates in the reverse manner. The three (or four) LVDS serial inputs are transformed back to the original 7-bit parallel single-ended data. FlatLink devices are available in 21:3 or 28:4 SerDes ratios. • The 21-bit devices are designed for 6-bit RGB video for a total of 18 bits in addition to 3 extra bits for horizontal synchronization, vertical synchronization, and data enable. • The 28-bit devices are intended for 8-bit RGB video applications. Again, the extra 4 bits are for horizontal synchronization, vertical synchronization, data enable, and the remaining is the reserved bit. These 28-bit devices can also be used in 6-bit and 4-bit RGB applications as shown in the subsequent system diagrams. 9.2 Functional Block Diagram Parallel-Load 7-bit Shift Register D0, D1, D2, D3, D4, D6, D7 7 A,B,...G SHIFT/LOAD >CLK Y0P Y0M Parallel-Load 7-bit Shift Register D8, D9, D12, D13, D14, D15, D18 7 A,B,...G SHIFT/LOAD >CLK Y1P Y1M Parallel-Load 7-bit Shift Register D19, D20, D21, D22, D24, D25, D26 7 A,B,...G SHIFT/LOAD >CLK Y2P Y2M Parallel-Load 7-bit Shift Register D27, D5, D10, D11, D16, D17, D23 7 A,B,...G SHIFT/LOAD >CLK Y3P Y3M Control Logic SHTDN 7X Clock/PLL 7XCLK CLKIN >CLK CLKINH CLKSEL 16 CLKOUTP CLKOUTM RISING/FALLING EDGE Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 9.3 Feature Description 9.3.1 TTL Input Data The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN65LVDS93A and can connect directly to lowpower, low-voltage application and graphic processors. The bit mapping is listed in Table 1. Table 1. Pixel Bit Ordering RED GREEN BLUE R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 LSB 4-bit MSB 6-bit MSB 8-bit MSB 9.3.2 LVDS Output Data The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts. Table 2. Pixel Data Assignment SERIAL CHANNEL Y0 Y1 Y2 8-BIT DATA BITS 6-BIT 4-BIT NON-LINEAR STEP LINEAR STEP SIZE SIZE FORMAT-1 FORMAT-2 FORMAT-3 D0 R0 R2 R2 R0 R2 VCC D1 R1 R3 R3 R1 R3 GND D2 R2 R4 R4 R2 R0 R0 D3 R3 R5 R5 R3 R1 R1 D4 R4 R6 R6 R4 R2 R2 D6 R5 R7 R7 R5 R3 R3 D7 G0 G2 G2 G0 G2 VCC D8 G1 G3 G3 G1 G3 GND D9 G2 G4 G4 G2 G0 G0 D12 G3 G5 G5 G3 G1 G1 D13 G4 G6 G6 G4 G2 G2 D14 G5 G7 G7 G5 G3 G3 D15 B0 B2 B2 B0 B2 VCC D18 B1 B3 B3 B1 B3 GND D19 B2 B4 B4 B2 B0 B0 D20 B3 B5 B5 B3 B1 B1 D21 B4 B6 B6 B4 B2 B2 D22 B5 B7 B7 B5 B3 B3 D24 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC D25 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC D26 ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 17 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Table 2. Pixel Data Assignment (continued) SERIAL CHANNEL Y3 CLKOUT 8-BIT DATA BITS 6-BIT 4-BIT NON-LINEAR STEP LINEAR STEP SIZE SIZE FORMAT-1 FORMAT-2 FORMAT-3 D27 R6 R0 GND GND GND GND D5 R7 R1 GND GND GND GND D10 G6 G0 GND GND GND GND D11 G7 G1 GND GND GND GND D16 B6 B0 GND GND GND GND D17 B7 B1 GND GND GND GND D23 RSVD RSVD GND GND GND GND CLKIN CLK CLK CLK CLK CLK CLK 9.4 Device Functional Modes 9.4.1 Input Clock Edge The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the CLKIN signal, where the rising or falling edge of the clock may be selected through CLKSEL. The selection of a clock rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pullup resistor to pull CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to GND. 9.4.2 Low Power Mode The SN65LVDS93A can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A lowlevel on this signal clears all internal registers to a low-level. Populate a pullup to VCC on SHTDN# to enable the device for normal operation. 18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information This section describes the power up sequence, provides information on device connectivity to various GPU and LCD display panels, and offers a PCB routing example. 10.1.1 Power The SN65LVDS93A does not require a specific power-up sequence. The device is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while all other device blocks are still powered down. The device is also permitted to power up all 3.3-V power domains while IOVCC is still powered down to GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still lower than normal mode. The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended: Power-up sequence (SN65LVDS93A SHTDN input initially low): 1. Ramp up LCD power (maybe 0.5 ms to 10 ms) but keep backlight turned off. 2. Wait for additional 0-200ms to ensure display noise won’t occur. 3. Enable video source output; start sending black video data. 4. Toggle LVDS83B shutdown to SHTDN = VIH. 5. Send >1 ms of black video data; this allows the LVDS83B to be phase locked, and the display to show black data first. 6. Start sending true image data. 7. Enable backlight. Power-down sequence (SN65LVDS93A SHTDN input initially high): 1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low. 2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for >2 frame times. 3. Set SN65LVDS93A input SHTDN = GND; wait for 250 ns. 4. Disable the video output of the video source. 5. Remove power from the LCD panel for lowest system power. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 19 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com 10.2 Typical Application J1 U1H GND1 GND2 GND3 GND4 GND5 GND6 GND7 PLLGND LVDSGND1 LVDSGND2 J3 CLKM CLKP Y0P Y0M Y1P Y1M Y2P Y2M IOVCC R4 4.7k R5 4.7k R6 4.7k R7 4.7k R8 4.7k R9 4.7k Y3P Y3M R10 4.7k JMP1 U1B D0 D1 D2 D3 D4 D6 D7 D0 D1 D2 D3 D4 D6 D7 D1 D2 G2 G1 J5 E1 E2 sma_surface J6 sma_surface C2 C1 J7 sma_surface SN65LVDS93A-Q1ZQL J8 sma_surface J9 sma_surface 14 Header 7x2 J10 sma_surface IOVCC R11 4.7k R12 4.7k R13 4.7k R14 4.7k R15 4.7k R16 4.7k R17 4.7k sma_surface JMP2 U1C K6 J6 G5 G6 F6 E5 D5 J4 sma_surface H2 H1 1 2 SN65LVDS93A-Q1ZQL D8 D9 D12 D13 D14 D15 D18 sma_surface U1A SN65LVDS93A-Q1ZQL J2 K1 K2 J3 K3 J4 K5 J2 sma_surface C3 C5 D3 F5 G3 H3 J5 A1 B1 F2 D8 D9 D12 D13 D14 D15 D18 1 2 IOVCC IOVCC 14 R1 4.7k Header 7x2 SN65LVDS93A-Q1ZQL R2 IOVCC R18 4.7k R19 4.7k R20 4.7k R21 4.7k R22 4.7k R23 4.7k R24 4.7k JMP6 U1G JMP3 U1D D19 D20 D21 D22 D24 D25 D 26 C6 B6 B5 A6 A4 B4 A3 D19 D20 D21 D22 D24 D25 D26 SHTDN CLKSEL 1 2 B3 D4 SHTDN CLKSEL 1 2 3 4 Header 2x2 SN65LVDS93A-Q1ZQL 14 U1J NC1 NC2 NC3 NC4 Header 7x2 SN65LVDS93A-Q1ZQL IOVCC R25 4.7k R26 4.7k R27 4.7k R28 4.7k R29 4.7k R30 4.7k E3 E4 F3 F4 SN65LVDS93A-Q1ZQL R31 4.7k JMP4 U1E D5 D10 D11 D16 D17 D23 D27 K4 H4 H6 E6 D6 A5 J1 D5 D10 D11 D16 D17 D23 D27 VCC 1 2 IOVCC U1I VCC PLLVCC LVDSVCC 14 IOVCC1 IOVCC2 Header 7x2 SN65LVDS93A-Q1ZQL G4 B2 F1 H5 C4 SN65LVDS93A-Q1ZQL VCC VCC C31 1uF C32 0.1uF C33 0.01uF VCC C34 1uF C35 0.1uF C36 0.01uF IOVCC C40 1uF C41 0.1uF C42 0.01uF C37 1uF C38 0.1uF C39 0.01uF PLACE UNDER LVDS93A-Q1 (bottom pcb side) Figure 14. Schematic Example (SN65LVDS93A Evaluation Board) 20 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 Typical Application (continued) 10.2.1 Design Requirements For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VCC 3.3 V VCCIO 1.8 V CLKIN Falling edge SHTDN# High Format 18-bit GPU to 24-bit LCD 10.2.2 Detailed Design Procedure 10.2.2.1 Signal Connectivity While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the industry has aligned over the years on a certain data format (bit order). Figure 15 through Figure 18 show how each signal should be connected from the graphic source through the SN65LVDS93A input, output and LVDS LCD panel input. Detailed notes are provided with each figure. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 21 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com SN65LVDS93A 4.8k 1.8V or 2.5V or 3.3V C1 Rpullup Rpulldown Y0M Y0P Y2M Y2P Y3M Y3P 100 to column driver 100 FPC Cable Panel connector Y1M Y1P LVDS timing Controller (8bpc, 24bpp) 100 100 to row driver CLKOUTM CLKOUTP 100 VCC PLLVCC LVDSVCC 24-bpp LCD Display GND SHTDN D27 D5 D0 D1 D2 D3 D4 D6 D10 D11 D7 D8 D9 D12 D13 D14 D16 D17 D15 D18 D19 D20 D21 D22 D24 D25 D26 D23 CLKIN CLKSEL FORMAT2 (See Note A) D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN IOVCC VDDGPUIO GND R0(LSB) R1 R2 R3 R4 R5 R6 R7(MSB) G0(LSB) G1 G2 G3 G4 G5 G6 G7(MSB) B0(LSB) B1 B2 B3 B4 B5 B6 B7(MSB) HSYNC VSYNC ENABLE RSVD (Note C) CLK FORMAT1 Main board connector 24-bpc GPU 3.3V C2 3.3V C3 (See Note B) Main Board Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by checking the LCD display data sheet. • Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the dominate data format for LCD panels. • Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel. Note B. Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF. • C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF. • C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF. Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended. Note D. RSVD must be driven to a valid logic level. All unused SN65LVDS93A inputs must be tied to a valid logic level. Figure 15. 24-Bit Color Host to 24-Bit LCD Panel Application 22 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 SN65LVDS93A D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN B0(LSB) B1 B2 B3 B4 B5(MSB) C1 CLKOUTM CLKOUTP FPC Cable Panel connector Main board connector 100 Y2M Y2P LVDS timing Controller (6-bpc, 18-bpp) 100 100 to row driver 18-bpp LCD Display Y3M Y3P 4.8k 1.8V or 2.5V or 3.3V to column driver Y1M Y1P IOVCC VDDGPUIO GND HSYNC VSYNC ENABLE RSVD CLK 100 Rpullup (See Note A) VCC PLLVCC LVDSVCC G0(LSB) G1 G2 G3 G4 G5(MSB) Y0M Y0P GND R0(LSB) R1 R2 R3 R4 R5(MSB) SHTDN CLKSEL 18-bpp GPU 3.3V C2 3.3V C3 Rpulldown (See Note B) Main Board Note A. Leave output Y3 NC. Note B.Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF. • C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF. • C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF. Figure 16. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 23 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 12-bpp GPU www.ti.com SN65LVDS93A (See Note B) (See Note B) B2 or VCC B3 or GND B0 B1 B2 B3(MSB) C1 100 FPC Cable t Panell connector to column driver CLKOUTM CLKOUTP LVDS timing Controller (6-bpc, 18-bpp) 100 100 to row driver 18-bpp LCD Display Y3M Y3P 4.8k 1.8V or 2.5V or 3.3V Y1M Y1P Y2M Y2P IOVCC VDDGPUIO GND HSYNC VSYNC ENABLE RSVD CLK 100 Rpullup (See Note A) VCC PLLVCC LVDSVCC G2 or VCC G3 or GND G0 G1 G2 G3(MSB) SHTDN CLKSEL (See Note B) Y0M Y0P Main board connector D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN GND R2 or VCC R3 or GND R0 R1 R2 R3(MSB) 3.3V C2 3.3V C3 Rpulldown (See Note C) Main Board Note A. Leave output Y3 N.C. Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of the entire color space at the expense of nonlinear step sizes between each step. For linear steps with less dynamic range, connect D1, D8, and D18 to GND. R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color space at the expense of nonlinear step sizes between each step. For linear steps with less dynamic range, connect D0, D7, and D15 to VCC. Note C.Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF. • C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF. • C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF. Figure 17. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application 24 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 SN65LVDS93A G2 G3 G4 G5 G6 G7(MSB) B0 and B1: NC (See Note B) B2 B3 B4 B5 B6 B7(MSB) B0 and B1: NC (See Note B) C1 Y1M Y1P 100 to column driver CLKOUTM CLKOUTP FPC Cable LVDS timing Controller (6-bpc, 18-bpp) 100 100 to row driver 18-bpp LCD Display Y3M Y3P 4.8k 1.8V or 2.5V or 3.3V 100 Y2M Y2P IOVCC VDDGPUIO GND HSYNC VSYNC ENABLE RSVD CLK Y0M Y0P t Panell connector G0 and G1: NC (See Note B) SHTDN CLKSEL R7(MSB) Main board connector D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN Rpullup (See Note A) VCC PLLVCC LVDSVCC R2 R3 R4 R5 R6 GND 24-bpp GPU R0 and R1: NC (See Note B) 3.3V C2 3.3V C3 Rpulldown (See Note C) Main Board Note A. Leave output Y3 NC. Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down to18-bit per pixel. NoteC.Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF. • C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF. • C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF. Figure 18. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 25 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com 10.2.2.2 PCB Routing Figure 19 shows a possible breakout of the data input and output signals on two layers of a printed-circuit-board. D27 D5 D10 D11 D16 D17 D23 Y0M Y0P D19 D20 D21 D22 D24 D25 D26 Y1M Y1P Y2M Y2P D8 D9 D12 D13 D14 D15 D18 CLKINM CLKINP Y3M Y3P D0 D1 D2 D3 D4 D6 D7 CLKIN Figure 19. Printed-Circuit-Board Routing Example (See Figure 14 for the Schematic) 10.2.3 Application Curve 250 Pixel Value (dec) 200 150 100 50 0 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 Pixel Samples Figure 20. 18b GPU to 24b LCD 26 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 11 Power Supply Recommendations Power supply PLL, IO, and LVDS pins must be uncoupled from each. 12 Layout 12.1 Layout Guidelines 12.1.1 Board Stackup There is no fundamental information about how many layers should be used and how the board stackup should look. Again, the easiest way the get good results is to use the design from the EVMs of TI. The magazine Elektronik Praxis has published an article with an analysis of different board stackups. These are listed in Table 4. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a GND plane. Better is the use of a 4-layer PCB, with a GND and a VCC plane and two signal layers. If the circuit is complex and signals must be routed as stripline, because of propagation delay and/or characteristic impedance, a 6-layer stackup should be used. Table 4. Possible Board Stackup on a Four-Layer PCB MODEL 1 MODEL 2 MODEL 3 MODEL 4 Layer 1 SIG SIG SIG GND Layer 2 SIG GND GND SIG Layer 3 VCC VCC SIG VCC Layer 4 GND SIG VCC SIG Decoupling Good Good Bad Bad Bad EMC Bad Bad Bad Signal Integrity Bad Bad Good Bad Self Disturbance Satisfaction Satisfaction Satisfaction High 12.1.2 Power and Ground Planes A complete ground plane in high-speed design is essential. Additionally, a complete power plane is recommended as well. In a complex system, several regulated voltages can be present. The best solution is for every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In a mixed-signal design, for example, using data converters, the manufacturer often recommends splitting the analog ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part. Take care when using split ground planes because: • Split ground planes act as slot antennas and radiate. • A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal, and the signal can induce noise into the nonrelated reference plane (Figure 21). • With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the ground plane. Always take care of the return current (Figure 22). For Figure 22, do not route a signal referenced to digital ground over analog ground and vice versa. The return current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal induces noise, due to crosstalk (dotted red line) into the analog ground plane. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 27 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Figure 21. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting Figure 22. Crosstalk Induced by the Return Current Path 12.1.3 Traces, Vias, and Other PCB Components A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the characteristic impedance changes. This impedance change causes reflections. • Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any impedance change, the best routing would be a round bend (see Figure 23). • Separate high-speed signals (for example, clock signals) from low-speed signals and digital from analog signals; again, placement is important. • To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route them with 90° to each other. 28 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 Figure 23. Poor and Good Right-Angle Bends 12.2 Layout Example SN65LVDS93A-Q1 EVM REV 6507548 Figure 24. SN65LVDS93A EVM Top Layer – TSSOP Package Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 29 SN65LVDS93A SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com Layout Example (continued) Figure 25. SN65LVDS93A EVM VCC Layer – TSSOP Package 30 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A SN65LVDS93A www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: LVDS SerDes Receiver, SLLS928 13.2 Trademarks OMAP, DaVinci, FlatLink are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65LVDS93A 31 PACKAGE OPTION ADDENDUM www.ti.com 19-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN65LVDS93ADGG ACTIVE TSSOP DGG 56 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS93A SN65LVDS93ADGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS93A SN65LVDS93AZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 LVDS93A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Mar-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN65LVDS93A : • Automotive: SN65LVDS93A-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS93AZQLR Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR ZQL 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 4.8 B0 (mm) K0 (mm) P1 (mm) 7.3 1.5 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS93AZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 336.6 336.6 28.6 Pack Materials-Page 2 PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 TYP 7.9 SEATING PLANE PIN 1 ID AREA A 0.1 C 54X 0.5 56 1 14.1 13.9 NOTE 3 2X 13.5 28 B 6.2 6.0 29 56X 0.27 0.17 0.08 1.2 MAX C A B (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 29 28 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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