TL431, TL432 Adjustable Precision Shunt

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TL431, TL431A, TL431B
TL432, TL432A, TL432B
SLVS543O – AUGUST 2004 – REVISED JANUARY 2015
TL43xx Precision Programmable Reference
1 Features
3 Description
•
The TL431 and TL432 devices are three-terminal
adjustable shunt regulators, with specified thermal
stability over applicable automotive, commercial, and
military temperature ranges. The output voltage can
be set to any value between Vref (approximately
2.5 V) and 36 V, with two external resistors. These
devices have a typical output impedance of 0.2 Ω.
Active output circuitry provides a very sharp turn-on
characteristic, making these devices excellent
replacements for Zener diodes in many applications,
such as onboard regulation, adjustable power
supplies, and switching power supplies. The TL432
device has exactly the same functionality and
electrical specifications as the TL431 device, but has
different pinouts for the DBV, DBZ, and PK packages.
1
•
•
•
•
•
•
•
Reference Voltage Tolerance at 25°C
– 0.5% (B Grade)
– 1% (A Grade)
– 2% (Standard Grade)
Adjustable Output Voltage: Vref to 36 V
Operation From −40°C to 125°C
Typical Temperature Drift (TL431B)
– 6 mV (C Temp)
– 14 mV (I Temp, Q Temp)
Low Output Noise
0.2-Ω Typical Output Impedance
Sink-Current Capability: 1 mA to 100 mA
Both the TL431 and TL432 devices are offered in
three grades, with initial tolerances (at 25°C) of 0.5%,
1%, and 2%, for the B, A, and standard grade,
respectively. In addition, low output drift versus
temperature ensures good stability over the entire
temperature range.
2 Applications
•
•
•
•
•
Adjustable Voltage and Current Referencing
Secondary Side Regulation in Flyback SMPSs
Zener Replacement
Voltage Monitoring
Comparator with Integrated Reference
The TL43xxC devices are characterized for operation
from 0°C to 70°C, the TL43xxI devices are
characterized for operation from –40°C to 85°C, and
the TL43xxQ devices are characterized for operation
from –40°C to 125°C.
Device Information(1)
PART NUMBER
TL43xx
PACKAGE (PIN)
BODY SIZE (NOM)
SOT-23-3 (3)
2.90 mm x 1.30 mm
SOT-23-5 (5)
2.90 mm x 1.60 mm
SOIC (8)
4.90 mm x 3.90 mm
PDIP (8)
9.50 mm x 6.35 mm
SOP (8)
6.20 mm x 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
VKA
Input
IKA
Vref
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL431, TL431A, TL431B
TL432, TL432A, TL432B
SLVS543O – AUGUST 2004 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Thermal Information .................................................. 4
Recommended Operating Conditions....................... 4
Electrical Characteristics, TL431C, TL432C ............. 5
Electrical Characteristics, TL431I, TL432I ................ 6
Electrical Characteristics, TL431Q, TL432Q............. 7
Electrical Characteristics, TL431AC, TL432AC ........ 8
Electrical Characteristics, TL431AI, TL432AI ........... 9
Electrical Characteristics, TL431AQ, TL432AQ.... 10
Electrical Characteristics, TL431BC, TL432BC .... 11
Electrical Characteristics, TL431BI, TL432BI ....... 12
Electrical Characteristics, TL431BQ, TL432BQ.... 13
Typical Characteristics .......................................... 14
8
9
Parameter Measurement Information ................ 18
Detailed Description ............................................ 19
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
20
10 Applications and Implementation...................... 21
10.1 Application Information.......................................... 21
10.2 Typical Applications .............................................. 21
10.3 System Examples ................................................. 26
11 Power Supply Recommendations ..................... 29
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
14 Mechanical, Packaging, and Orderable
Information ........................................................... 30
5 Revision History
Changes from Revision N (January 2014) to Revision O
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, ,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Moved Typical Characteristics into Specifications section. ................................................................................................. 14
Changes from Revision M (July 2012) to Revision N
Page
•
Updated document formatting ................................................................................................................................................ 1
•
Removed Ordering Information table. .................................................................................................................................... 3
•
Added Application Note links................................................................................................................................................ 21
Changes from Revision K (June 2010) to Revision L
•
2
Page
Deleted TA values under TEST CONDITIONS for VI(dev) and II(dev) PARAMETERS in the Electrical Characteristics table. .. 5
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SLVS543O – AUGUST 2004 – REVISED JANUARY 2015
6 Pin Configuration and Functions
TL431, TL431A, TL431B . . . LP (TO-92/TO-226) PACKAGE
(TOP VIEW)
TL431A, TL431B . . . DCK (SC-70) PACKAGE
(TOP VIEW)
TL431 . . . KTP (PowerFLEX /TO-252) PACKAGE
(TOP VIEW)
CATHODE
ANODE
CATHODE
ANODE
CATHODE
NC
REF
ANODE
REF
REF
1
8
2
7
3
6
4
5
REF
ANODE
ANODE
NC
CATHODE
NC
NC
NC
3
4
ANODE
NC
NC
1
8
2
7
3
6
4
5
REF
NC
ANODE
NC
NC − No internal connection
TL431, TL431A, TL431B . . . PK (SOT-89) PACKAGE
(TOP VIEW)
TL432, TL432A, TL432B . . . PK (SOT-89) PACKAGE
(TOP VIEW)
REF
ANODE
ANODE
CATHODE
ANODE
ANODE
REF
CATHODE
TL432, TL432A, TL432B . . . DBV (SOT-23-5) PACKAGE
(TOP VIEW)
TL431, TL431A, TL431B . . . DBV (SOT-23-5) PACKAGE
(TOP VIEW)
NC
1
†
2
CATHODE
3
5
ANODE
4
REF
NC
1
ANODE
2
NC
3
REF
4
CATHODE
TL432, TL432A, TL432B . . . DBZ (SOT-23-3) PACKAGE
(TOP VIEW)
TL431, TL431A, TL431B . . . DBZ (SOT-23-3) PACKAGE
(TOP VIEW)
REF
1
CATHODE
2
1
3
5
NC − No internal connection
NC − No internal connection
† Pin 2 is attached to Substrate and must be
connected to ANODE or left open.
REF
5
TL431, TL431A, TL431B . . . P (PDIP), PS (SOP),
OR PW (TSSOP) PACKAGE
(TOP VIEW)
NC − No internal connection
CATHODE
6
2
NC − No internal connection
TL431, TL431A, TL431B . . . D (SOIC) PACKAGE
(TOP VIEW)
CATHODE
ANODE
ANODE
NC
1
ANODE
3
2
ANODE
Pin Functions
PIN
TLV431x
NAME
TLV432x
TYPE
DESCRIPTION
DBZ
DBV
PK
D
P, PS
PW
CATHODE
1
3
3
1
1
1
1
1
2
4
1
I/O
REF
2
4
1
8
8
3
3
3
1
5
3
I
Threshold relative to common anode
2
2, 3,
6, 7
6
2
2
6
3
2
2
O
Common pin, normally connected to ground
ANODE
3
5
LP
KTP
DCK
DBZ
DBV
PK
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Shunt Current/Voltage input
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VKA
Cathode voltage (2)
IKA
Continuous cathode current range
II(ref)
Reference input current range
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
(1)
(2)
MAX
UNIT
37
V
–100
150
mA
–0.05
10
mA
150
°C
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ANODE, unless otherwise noted.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Thermal Information
TL43xx
THERMAL METRIC (1)
P
PW
D
PS
8 PINS
DCK
DBV
6 PINS
5 PINS
DBZ
LP
PK
RθJA
Junction-to-ambient thermal
resistance
85
149
97
95
259
206
206
140
52
RθJC(top)
Junction-to-case (top) thermal
resistance
57
65
39
46
87
131
76
55
9
(1)
UNIT
3 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.4 Recommended Operating Conditions
See (1)
VKA
Cathode voltage
IKA
Cathode current
MIN
MAX
Vref
36
V
1
100
mA
0
70
TL43xxI
–40
85
TL43xxQ
–40
125
TL43xxC
TA
(1)
4
Operating free-air temperature
UNIT
°C
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
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7.5 Electrical Characteristics, TL431C, TL432C
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
Vref
TEST CIRCUIT
Reference voltage
See Figure 20
TL431C, TL432C
TEST CONDITIONS
VKA = Vref, IKA = 10 mA
MIN
TYP
MAX
2440
2495
2550
SOT23-3 and TL432
devices
6
16
All other devices
4
25
–1.4
–2.7
–1
–2
UNIT
mV
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.4
1.2
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
1
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
1
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
VI(dev)
|zKA|
(1)
(2)
Dynamic impedance
(2)
VKA = Vref,
IKA = 10 mA,
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
(
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7.6 Electrical Characteristics, TL431I, TL432I
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
Vref
TEST CIRCUIT
Reference voltage
See Figure 20
TEST CONDITIONS
VKA = Vref, IKA = 10 mA
SOT23-3 and TL432
devices
TL431I, TL432I
MIN
TYP
MAX
2440
2495
2550
14
34
5
50
–1.4
–2.7
–1
–2
UNIT
mV
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
2.5
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
1
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
1
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
VI(dev)
|zKA|
(1)
(2)
Dynamic impedance
(2)
All other devices
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
6
VKA = Vref,
IKA = 10 mA
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7.7 Electrical Characteristics, TL431Q, TL432Q
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CIRCUIT
TL431Q, TL432Q
TEST CONDITIONS
UNIT
MIN
TYP
MAX
2440
2495
2550
mV
14
34
mV
–1.4
–2.7
–1
–2
Vref
Reference voltage
See Figure 20
VKA = Vref, IKA = 10 mA
VI(dev)
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
VKA = Vref, IKA = 10 mA
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
2.5
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
1
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
1
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
|zKA|
(1)
(2)
Dynamic impedance
(2)
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
(
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7.8 Electrical Characteristics, TL431AC, TL432AC
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
Vref
TEST CIRCUIT
Reference voltage
See Figure 20
TEST CONDITIONS
VKA = Vref, IKA = 10 mA
TL431AC, TL432AC
MIN
TYP
MAX
2470
2495
2520
SOT23-3 and TL432
devices
6
16
All other devices
4
25
–1.4
–2.7
–1
–2
UNIT
mV
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
1.2
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
0.6
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
0.5
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
VI(dev)
|zKA|
(1)
(2)
Dynamic impedance
(2)
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
8
VKA = Vref,
IKA = 10 mA
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7.9 Electrical Characteristics, TL431AI, TL432AI
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
Vref
TEST CIRCUIT
Reference voltage
See Figure 20
TL431AI, TL432AI
TEST CONDITIONS
VKA = Vref, IKA = 10 mA
SOT23-3 and TL432
devices
MIN
TYP
MAX
2470
2495
2520
14
34
5
50
–1.4
–2.7
–1
–2
UNIT
mV
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
2.5
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
0.7
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
0.5
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
VI(dev)
|zKA|
(1)
(2)
Dynamic impedance
(2)
VKA = Vref,
IKA = 10 mA
All other devices
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
(
Copyright © 2004–2015, Texas Instruments Incorporated
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7.10 Electrical Characteristics, TL431AQ, TL432AQ
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CIRCUIT
TEST CONDITIONS
TL431AQ, TL432AQ
UNIT
MIN
TYP
MAX
2470
2495
2520
mV
14
34
mV
–1.4
–2.7
–1
–2
Vref
Reference voltage
See Figure 20
VKA = Vref, IKA = 10 mA
VI(dev)
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
VKA = Vref, IKA = 10 mA
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
2.5
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
0.7
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
0.5
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
|zKA|
(1)
(2)
Dynamic impedance
(2)
ΔVKA = 36 V – 10 V
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
10
ΔVKA = 10 V – Vref
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7.11 Electrical Characteristics, TL431BC, TL432BC
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CIRCUIT
TL431BC, TL432BC
TEST CONDITIONS
UNIT
MIN
TYP
MAX
2483
2495
2507
mV
6
16
mV
–1.4
–2.7
–
–2
Vref
Reference voltage
See Figure 20
VKA = Vref, IKA = 10 mA
VI(dev)
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
VKA = Vref, IKA = 10 mA
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
1.2
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
0.6
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
0.5
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
|zKA|
(1)
(2)
Dynamic impedance
(2)
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
(
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7.12 Electrical Characteristics, TL431BI, TL432BI
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CIRCUIT
TEST CONDITIONS
TL431BI, TL432BI
UNIT
MIN
TYP
MAX
2483
2495
2507
mV
14
34
mV
–1.4
–2.7
–1
–2
Vref
Reference voltage
See Figure 20
VKA = Vref, IKA = 10 mA
VI(dev)
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
VKA = Vref, IKA = 10 mA
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
2.5
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
0.7
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
0.5
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
|zKA|
(1)
(2)
Dynamic impedance
(2)
ΔVKA = 36 V – 10 V
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
12
ΔVKA = 10 V – Vref
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7.13 Electrical Characteristics, TL431BQ, TL432BQ
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CIRCUIT
TL431BQ, TL432BQ
TEST CONDITIONS
UNIT
MIN
TYP
MAX
2483
2495
2507
mV
14
34
mV
–1.4
–2.7
–1
–2
Vref
Reference voltage
See Figure 20
VKA = Vref, IKA = 10 mA
VI(dev)
Deviation of reference input
voltage over full temperature
range (1)
See Figure 20
VKA = Vref, IKA = 10 mA
ΔVref /
ΔVKA
Ratio of change in reference
voltage to the change in
cathode voltage
See Figure 21
IKA = 10 mA
Iref
Reference input current
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
2
4
µA
II(dev)
Deviation of reference input
current over full temperature
range (1)
See Figure 21
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞
0.8
2.5
µA
Imin
Minimum cathode current for
regulation
See Figure 20
VKA = Vref
0.4
0.7
mA
Ioff
Off-state cathode current
See Figure 22
VKA = 36 V, Vref = 0
0.1
0.5
µA
See Figure 20
VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA
0.2
0.5
Ω
|zKA|
(1)
(2)
Dynamic impedance
(2)
ΔVKA = 10 V – Vref
ΔVKA = 36 V – 10 V
mV/V
The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
∆IKA
The dynamic impedance is defined as:
|z'| = ∆V
∆I
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by:
|zKA| 1 + R1
R2 .
which is approximately equal to
(
(
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7.14 Typical Characteristics
Data at high and low temperatures are applicable only within the recommended operating free-air temperature
ranges of the various devices.
2600
5
2580
Vref = 2550 mV
2560
4
I ref − Reference Current − µA
V ref − Reference Voltage − mV
R1 = 10 kΩ
R2 =∞
IKA = 10 mA
VKA = Vref
IKA = 10 mA
2540
2520
Vref = 2495 mV
2500
2480
2460
Vref = 2440 mV
2440
3
2
1
2420
2400
−75
−50
−25
0
25
50
75
100
0
−75
125
−50
Figure 1. Reference Voltage vs Free-Air Temperature
25
0
50
75
100
125
Figure 2. Reference Current vs Free-Air Temperature
800
150
VKA = Vref
TA = 25°C
125
VKA = Vref
TA = 25°C
600
I KA − Cathode Current − µ A
100
I KA − Cathode Current − mA
−25
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
75
50
25
0
−25
−50
Imin
400
200
0
−75
−100
−2
−1
0
2
1
−200
−1
3
0
VKA − Cathode Voltage − V
Figure 3. Cathode Current vs Cathode Voltage
Figure 4. Cathode Current vs Cathode Voltage
VKA = 36 V
Vref = 0
VKA = 3 V to 36 V
− 0.95
2
∆V ref / ∆V KA − mV/V
I off − Off-State Cathode Current − µA
3
− 0.85
2.5
1.5
1
0.5
−1.05
−1.15
−1.25
−1.35
16
0
−75
14
2
1
VKA − Cathode Voltage − V
16
−50
−25
0
25
50
75
100
125
−1.45
−75
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 5. Off-State Cathode Current
vs Free-Air Temperature
Figure 6. Ratio of Delta Reference Voltage to Delta Cathode
Voltage vs Free-Air Temperature
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Typical Characteristics (continued)
6
IO = 10 mA
TA = 25°C
240
V n − Equivalent Input Noise V oltage − µV
Vn − Equivalent Input Noise V oltage − nV/
Hz
260
220
200
180
160
140
120
16
5
4
3
2
1
0
−1
−2
−3
f = 0.1 to 10 Hz
IKA = 10 mA
TA = 25°C
−4
−5
−6
100
10
100
1k
10 k
0
100 k
1
2
3
4
5
6
7
8
9
10
t − Time − s
f − Frequency − Hz
Figure 8. Equivalent Input Noise Voltage Over a 10-S Period
Figure 7. Equivalent Input Noise Voltage vs Frequency
19.1 V
1 kΩ
500 µF
910 Ω
2000 µF
VCC
TL431
(DUT)
VCC
1 µF
TLE2027
AV = 10 V/mV
+
820 Ω
+
−
16 kΩ
16 kΩ
1 µF
22 µF
To
Oscilloscope
−
16 Ω
160 kΩ
TLE2027
33 kΩ
AV = 2 V/V
0.1 µF
33 kΩ
VEE
VEE
Figure 9. Test Circuit for Equivalent Input Noise Voltage Over a 10-S Period
IKA = 10 mA
TA = 25°C
A V − Small-Signal V oltage Amplification − dB
60
IKA = 10 mA
TA = 25°C
50
Output
40
15 kΩ
30
232 Ω
9 µF
20
+
10
8.25 kΩ
0
1k
IKA
10 k
100 k
1M
10 M
GND
f − Frequency − Hz
Figure 10. Small-Signal Voltage Amplification
vs Frequency
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Figure 11. Test Circuit for Voltage Amplification
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Typical Characteristics (continued)
|z KA| − Reference Impedance − Ω
100
1 kΩ
Output
IKA = 10 mA
TA = 25°C
IKA
10
50 Ω
−
+
GND
1
Figure 13. Test Circuit for Reference Impedance
0.1
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 12. Reference Impedance vs Frequency
6
220 Ω
TA = 25°C
Output
Input
Input and Output V oltage − V
5
Pulse
Generator
f = 100 kHz
4
3
50 Ω
Output
GND
2
1
Figure 15. Test Circuit for Pulse Response
0
−1
0
1
2
3
4
5
6
7
t − Time − µs
Figure 14. Pulse Response
100
90
I KA − Cathode Current − mA
80
A V KA
B V KA
C VKA
D VKA
150 Ω
= Vref
=5V
= 10 V
= 15 Vf
TA = 25°C
IKA
+
B
VBATT
CL
70
−
Stable
60
C
Stable
50
A
40
TEST CIRCUIT FOR CURVE A
30
D
20
IKA
R1 = 10 kΩ
10
0
0.001
0.01
0.1
1
10
CL − Load Capacitance − µF
The areas under the curves represent conditions that may cause the
device to oscillate. For curves B, C, and D, R2 and V+ are adjusted
to establish the initial VKA and IKA conditions, with CL = 0. VBATT and
CL then are adjusted to determine the ranges of stability.
Figure 16. Stability Boundary Conditions for All TL431 and
TL431A Devices
(Except for SOT23-3, SC-70, and Q-Temp Devices)
16
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150 Ω
CL
+
R2
VBATT
−
TEST CIRCUIT FOR CURVES B, C, AND D
Figure 17. Test Circuits for Stability Boundary Conditions
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Typical Characteristics (continued)
100
90
I KA − Cathode Current − mA
80
A VKA
B V KA
C VKA
D VKA
150 Ω
= Vref
=5V
= 10 V
= 15 Vf
IKA
+
70
VBATT
CL
B
−
TA = 25°C
60
C
Stable
Stable
50
A
40
TEST CIRCUIT FOR CURVE A
A
30
D
IKA
20
R1 = 10 kΩ
B
150 Ω
10
0
0.001
CL
0.01
0.1
1
CL − Load Capacitance − µF
The areas under the curves represent conditions that may cause the
device to oscillate. For curves B, C, and D, R2 and V+ are adjusted
to establish the initial VKA and IKA conditions, with CL = 0. VBATT and
CL then are adjusted to determine the ranges of stability.
Figure 18. Stability Boundary Conditions for All TL431B,
TL432, SOT-23, SC-70, and Q-Temp Devices
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+
10
R2
VBATT
−
TEST CIRCUIT FOR CURVES B, C, AND D
Figure 19. Test Circuit for Stability Boundary Conditions
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8 Parameter Measurement Information
VKA
Input
IKA
Vref
Figure 20. Test Circuit for VKA = Vref
Input
VKA
IKA
R1
Iref
R2
Vref
R1 ö
æ
VKA = Vref ç 1 +
÷ + Iref × R1
R2
è
ø
Figure 21. Test Circuit for VKA > Vref
Input
VKA
Ioff
Figure 22. Test Circuit for Ioff
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9 Detailed Description
9.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications, ranging from power
to signal path. This is due to it's key components containing an accurate voltage reference & opamp, which are
very fundamental analog building blocks. TL43xx is used in conjunction with it's key components to behave as a
single voltage reference, error amplifier, voltage clamp or comparator with integrated reference.
TL43xx can be operated and adjusted to cathode voltages from 2.5V to 36V, making this part optimum for a wide
range of end equipments in industrial, auto, telecom & computing. In order for this device to behave as a shunt
regulator or error amplifier, >1mA (Imin(max)) must be supplied in to the cathode pin. Under this condition,
feedback can be applied from the Cathode and Ref pins to create a replica of the internal reference voltage.
Various reference voltage options can be purchased with initial tolerances (at 25°C) of 0.5%, 1%, and 2%. These
reference options are denoted by B (0.5%), A (1.0%) and blank (2.0%) after the TL431 or TL432. TL431 & TL432
are both functionaly, but have separate pinout options.
The TL43xxC devices are characterized for operation from 0°C to 70°C, the TL43xxI devices are characterized
for operation from –40°C to 85°C, and the TL43xxQ devices are characterized for operation from –40°C to
125°C.
9.2 Functional Block Diagram
CATHODE
+
REF
_
Vref
ANODE
Figure 23. Equivalent Schematic
CATHODE
800 Ω
800 Ω
20 pF
REF
150 Ω
3.28 kΩ
2.4 kΩ
7.2 kΩ
4 kΩ
10 kΩ
20 pF
1 kΩ
800 Ω
ANODE
Figure 24. Detailed Schematic
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9.3 Feature Description
TL43xx consists of an internal reference and amplifier that outputs a sink current base on the difference between
the reference pin and the virtual internal pin. The sink current is produced by the internal Darlington pair, shown
in the above schematic (Figure 24). A Darlington pair is used in order for this device to be able to sink a
maximum current of 100 mA.
When operated with enough voltage headroom (≥ 2.5 V) and cathode current (IKA), TL431 forces the reference
pin to 2.5 V. However, the reference pin can not be left floating, as it needs IREF ≥ 4 µA (please see Electrical
Characteristics, TL431C, TL432C). This is because the reference pin is driven into an npn, which needs base
current in order operate properly.
When feedback is applied from the Cathode and Reference pins, TL43xx behaves as a Zener diode, regulating
to a constant voltage dependent on current being supplied into the cathode. This is due to the internal amplifier
and reference entering the proper operating regions. The same amount of current needed in the above feedback
situation must be applied to this device in open loop, servo or error amplifying implementations in order for it to
be in the proper linear region giving TL43xx enough gain.
Unlike many linear regulators, TL43xx is internally compensated to be stable without an output capacitor
between the cathode and anode. However, if it is desired to use an output capacitor Figure 24 can be used as a
guide to assist in choosing the correct capacitor to maintain stability.
9.4 Device Functional Modes
9.4.1 Open Loop (Comparator)
When the cathode/output voltage or current of TL43xx is not being fed back to the reference/input pin in any
form, this device is operating in open loop. With proper cathode current (Ika) applied to this device, TL43xx will
have the characteristics shown in Figure 23. With such high gain in this configuration, TL43xx is typically used as
a comparator. With the reference integrated makes TL43xx the prefered choice when users are trying to monitor
a certain level of a single signal.
9.4.2 Closed Loop
When the cathode/output voltage or current of TL43xx is being fed back to the reference/input pin in any form,
this device is operating in closed loop. The majority of applications involving TL43xx use it in this manner to
regulate a fixed voltage or current. The feedback enables this device to behave as an error amplifier, computing
a portion of the output voltage and adjusting it to maintain the desired regulation. This is done by relating the
output voltage back to the reference pin in a manner to make it equal to the internal reference voltage, which can
be accomplished via resistive or direct feedback.
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
As this device has many applications and setups, there are many situations that this datasheet can not
characterize in detail. The linked application notes will help the designer make the best choices when using this
part.
Application note SLVA482 will provide a deeper understanding of this devices stability characteristics and aid the
user in making the right choices when choosing a load capacitor. Application note SLVA445 assists designers in
setting the shunt voltage to achieve optimum accuracy for this device.
10.2 Typical Applications
10.2.1 Comparator With Integrated Reference
Vsup
Rsup
Vout
CATHODE
R1
VIN
RIN
REF
VL
+
R2
2.5V
ANODE
Figure 25. Comparator Application Schematic
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Typical Applications (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input Voltage Range
0 V to 5 V
Input Resistance
10 kΩ
Supply Voltage
24 V
Cathode Current (Ik)
5 mA
Output Voltage Level
~2 V – VSUP
Logic Input Thresholds VIH/VIL
VL
10.2.1.2 Detailed Design Procedure
When using TL431 as a comparator with reference, determine the following:
• Input Voltage Range
• Reference Voltage Accuracy
• Output logic input high and low level thresholds
• Current Source resistance
10.2.1.2.1 Basic Operation
In the configuration shown in Figure 25 TL431 will behave as a comparator, comparing the VREF pin voltage to
the internal virtual reference voltage. When provided a proper cathode current (IK), TL43xx will have enough
open loop gain to provide a quick response. This can be seen in Figure 26, where the RSUP=10 kΩ (IKA=500 µA)
situation responds much slower than RSUP=1 kΩ (IKA=5 mA). With the TL43xx's max Operating Current (IMIN)
being 1 mA, operation below that could result in low gain, leading to a slow response.
10.2.1.2.1.1 Overdrive
Slow or inaccurate responses can also occur when the reference pin is not provided enough overdrive voltage.
This is the amount of voltage that is higher than the internal virtual reference. The internal virtual reference
voltage will be within the range of 2.5 V ±(0.5%, 1.0% or 1.5%) depending on which version is being used. The
more overdrive voltage provided, the faster the TL431 will respond.
For applications where TL431 is being used as a comparator, it is best to set the trip point to greater than the
positive expected error (i.e. +1.0% for the A version). For fast response, setting the trip point to >10% of the
internal VREF should suffice.
For minimal voltage drop or difference from Vin to the ref pin, it is recommended to use an input resistor <10kΩ
to provide Iref.
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10.2.1.2.2 Output Voltage and Logic Input Level
In order for TL431 to properly be used as a comparator, the logic output must be readable by the receiving logic
device. This is accomplished by knowing the input high and low level threshold voltage levels, typically denoted
by VIH & VIL.
As seen in Figure 26, TL431's output low level voltage in open-loop/comparator mode is ~2 V, which is typically
sufficient for 5V supplied logic. However, would not work for 3.3 V & 1.8 V supplied logic. In order to accomodate
this a resistive divider can be tied to the output to attenuate the output voltage to a voltage legible to the
receiving low voltage logic device.
TL431's output high voltage is equal to VSUP due to TL431 being open-collector. If VSUP is much higher than the
receiving logic's maximum input voltage tolerance, the output must be attenuated to accomadate the outgoing
logic's reliability.
When using a resistive divider on the output, be sure to make the sum of the resistive divider (R1 & R2 in
Figure 25) is much greater than RSUP in order to not interfere with TL431's ability to pull close to VSUP when
turning off.
10.2.1.2.2.1 Input Resistance
TL431 requires an input resistance in this application in order to source the reference current (IREF) needed from
this device to be in the proper operating regions while turing on. The actual voltage seen at the ref pin will be
VREF=VIN-IREF*RIN. Since IREF can be as high as 4 µA it is recommended to use a resistance small enough that
will mitigate the error that IREF creates from VIN.
10.2.1.3 Application Curves
5.5
5
4.5
4
Voltage (V)
3.5
3
2.5
2
1.5
1
Vin
Vka(Rsup=10k:)
Vka(Rsup=1k:)
0.5
0
-0.5
-0.001
-0.0006
-0.0002
0.0002
Time (s)
0.0006
0.001
D001
Figure 26. Output Response With Various Cathode Currents
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10.2.2 Shunt Regulator/Reference
RSUP
VSUP
VO = ( 1 +
R1
0.1%
CATHODE
REF
Vr ef
R1
) Vref
R2
R2
0.1%
TL431
ANODE
CL
Figure 27. Shunt Regulator Schematic
10.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Reference Initial Accuracy
1.0 %
Supply Voltage
24 V
Cathode Current (Ik)
5 mA
Output Voltage Level
2.5 V - 36 V
Load Capacitance
100 nF
Feedback Resistor Values and Accuracy (R1 & R2)
10 kΩ
10.2.2.2 Detailed Design Procedure
When using TL431 as a Shunt Regulator, determine the following:
• Input Voltage Range
• Temperature Range
• Total Accuracy
• Cathode Current
• Reference Initial Accuracy
• Output Capacitance
10.2.2.2.1
Programming Output/Cathode Voltage
In order to program the cathode voltage to a regulated voltage a resistive bridge must be shunted between the
cathode and anode pins with the mid point tied to the reference pin. This can be seen in Figure 27, with R1 & R2
being the resistive bridge. The cathode/output voltage in the shunt regulator configuration can be approximated
by the equation shown in Figure 27. The cathode voltage can be more accuratel determined by taking in to
account the cathode current:
Vo=(1+R1/R2)*VREF-IREF*R1
In order for this equation to be valid, TL43xx must be fully biased so that it has enough open loop gain to mitigate
any gain error. This can be done by meeting the Imin spec denoted in Electrical Characteristics, TL431C,
TL432C.
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10.2.2.2.2 Total Accuracy
When programming the output above unity gain (VKA=VREF), TL43xx is susceptible to other errors that may effect
the overall accuracy beyond VREF. These errors include:
•
•
•
•
R1 and R2 accuracies
VI(dev) - Change in reference voltage over temperature
ΔVREF / ΔVKA - Change in reference voltage to the change in cathode voltage
|zKA| - Dynamic impedance, causing a change in cathode voltage with cathode current
Worst case cathode voltage can be determined taking all of the variables in to account. Application note
SLVA445 assists designers in setting the shunt voltage to achieve optimum accuracy for this device.
10.2.2.2.3 Stability
Though TL43xx is stable with no capacitive load, the device that receives the shunt regulator's output voltage
could present a capacitive load that is within the TL43xx region of stability, shown inFigure 16 and Figure 18.
Also, designers may use capacitive loads to improve the transient response or for power supply decoupling.
When using additional capacitance between Cathode and Anode, refer to Figure 16 and Figure 18. Also,
application note SLVA482 will provide a deeper understanding of this devices stability characteristics and aid the
user in making the right choices when choosing a load capacitor.
10.2.2.2.4 Start-up Time
As shown in Figure 28, TL43xx has a fast response up to ~2 V and then slowly charges to it's programmed
value. This is due to the compensation capacitance (shown in Figure 24) the TL43xx has to meet it's stability
criteria. Despite the secondary delay, TL43xx still has a fast response suitable for many clamp applications.
10.2.2.3 Application Curves
27
24
21
Voltage (V)
18
Vsup
Vka=Vref
R1=10k: & R2=10k:
R1=38k: & R2=10k:
15
12
9
6
3
0
-3
-6
-5E-6
-3E-6
-1E-6
1E-6
Time (s)
3E-6
5E-6
D001
Figure 28. TL43xx Start-up Response
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10.3 System Examples
VI(BATT)
R
(see Note A)
2N222
2N222
30 Ω
4.7 kΩ
0.01 µF
TL431
VO
R2
0.1%
A.
R1
0.1%
R1 ö
æ
VO = ç 1 +
÷ Vref
R2 ø
è
R should provide cathode current ≥1 mA to the TL431 at minimum V(BATT).
Figure 29. Precision High-Current Series Regulator
VI(BATT)
IN
uA7805
OUT
Common
VO
R1
TL431
(
(
VO = 1 + R1 Vref
R2
Minimum V
V + 5V
O = ref
R2
Figure 30. Output Control of a Three-Terminal Fixed Regulator
VO
VI(BATT)
(
(
VO = 1 + R1 Vref
R2
R1
TL431
R2
Figure 31. High-Current Shunt Regulator
VI(BATT)
VO
R1
TL431
R2
A.
C
(see Note A)
Refer to the stability boundary conditions in Figure 16 and Figure 18 to determine allowable values for C.
Figure 32. Crowbar Circuit
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System Examples (continued)
IN
VI(BATT)
LM317
8.2 kΩ
OUT
VO ≈5 V, 1.5 A
Adjust
243 Ω
0.1%
TL431
243 Ω
0.1%
Figure 33. Precision 5-V, 1.5-A Regulator
VI(BATT)
VO ≈5 V
Rb
(see Note A)
27.4 kΩ
0.1%
TL431
27.4 kΩ
0.1%
A.
Rb should provide cathode current ≥1 mA to the TL431.
Figure 34. Efficient 5-V Precision Regulator
12 V
VCC
6.8 kΩ
5V
10 kΩ
−
10 kΩ
0.1%
TL431
10 kΩ
0.1%
+
X
Not
Used
TL598
Feedback
Figure 35. PWM Converter With Reference
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System Examples (continued)
R3
(see Note A)
VI(BATT)
R4
(see Note A)
R1B
R1A
Low Limit = 1 + R1B V ref
R2B
TL431
High Limit = 1 + R1A V ref
R2A
R2A
A.
LED on When Low Limit < VI(BATT) < High Limit
R2B
Select R3 and R4 to provide the desired LED intensity and cathode current ≥1 mA to the TL431 at the available
VI(BATT).
Figure 36. Voltage Monitor
650 Ω
12 V
R
2 kΩ
TL431
Off
On
æ
ö
12 V
Delay = R × C × In çç
÷÷
12
V
–
V
ref ø
è
C
Figure 37. Delay Timer
RCL
0.1%
VI(BATT)
IO
Iout =
R1
TL431
R1 =
V ref
+ IKA
R CL
V I(BATT)
I
O
h FE
+ IKA
Figure 38. Precision Current Limiter
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SLVS543O – AUGUST 2004 – REVISED JANUARY 2015
System Examples (continued)
VI(BATT)
IO
IO =
TL431
Vref
RS
RS
0.1%
Figure 39. Precision Constant-Current Sink
11 Power Supply Recommendations
When using TL43xx as a Linear Regulator to supply a load, designers will typically use a bypass capacitor on the
output/cathode pin. When doing this, be sure that the capacitance is within the stability criteria shown in
Figure 16 and Figure 18.
In order to not exceed the maximum cathode current, be sure that the supply voltage is current limited. Also, be
sure to limit the current being driven into the Ref pin, as not to exceed it's absolute maximum rating.
For applications shunting high currents, pay attention to the cathode and anode trace lengths, adjusting the width
of the traces to have the proper current density.
12 Layout
12.1 Layout Guidelines
Bypass capacitors should be placed as close to the part as possible. Current-carrying traces need to have widths
appropriate for the amount of current they are carrying; in the case of the TL43xx, these currents will be low.
12.2 Layout Example
TL432 - DBZ
(TOP VIEW)
Rref
Vin
REF
1
Rsup
Vsup
ANODE
3
CATHODE
2
GND
CL
GND
Figure 40. DBZ Layout example
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TL431
Click here
Click here
Click here
Click here
Click here
TL431A
Click here
Click here
Click here
Click here
Click here
TL431B
Click here
Click here
Click here
Click here
Click here
TL432
Click here
Click here
Click here
Click here
Click here
TL432A
Click here
Click here
Click here
Click here
Click here
TL432B
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
431AC
TL431ACDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(TACG ~ TACS)
TL431ACDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TACG
TL431ACDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(TACG ~ TACU)
TL431ACDBVTE4
ACTIVE
SOT-23
DBV
5
TBD
Call TI
Call TI
0 to 70
TL431ACDBVTG4
ACTIVE
SOT-23
DBV
5
TBD
Call TI
Call TI
0 to 70
TL431ACDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TAC3 ~ TACS ~
TACU)
TL431ACDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TAC3 ~ TACS ~
TACU)
TL431ACDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TAC3 ~ TACS ~
TACU)
TL431ACDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TAC3 ~ TACS ~
TACU)
TL431ACDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T4S ~ T4U)
TL431ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
431AC
TL431ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
431AC
TL431ACDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
431AC
TL431ACLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431AC
TL431ACLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431AC
TL431ACLPM
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431AC
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431ACLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431AC
TL431ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL431ACP
TL431ACPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
4A
TL431ACPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
4A
TL431ACPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431A
TL431ACPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431A
TL431ACPWE4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431A
TL431ACPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431A
TL431ACPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431A
TL431AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
431AI
TL431AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(TAIG ~ TAIS)
TL431AIDBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TAIG
TL431AIDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TAIG
TL431AIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(TAIG ~ TAIU)
TL431AIDBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TAIG
TL431AIDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TAIG
TL431AIDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TAI3 ~ TAIS ~
TAIU)
TL431AIDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TAI3 ~ TAIS ~
TAIU)
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431AIDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TAI3 ~ TAIS ~
TAIU)
TL431AIDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TAI3 ~ TAIS ~
TAIU)
TL431AIDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T5U
TL431AIDCKRE4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T5U
TL431AIDCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T5U
TL431AIDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T5U
TL431AIDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T5U
TL431AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
431AI
TL431AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
431AI
TL431AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
431AI
TL431AILP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
TL431AI
TL431AILPM
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
TL431AI
TL431AILPME3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
TL431AI
TL431AILPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
TL431AI
TL431AIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL431AIP
TL431AIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL431AIP
TL431AIPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
4B
TL431AIPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
4B
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431AQDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(TAQG ~ TAQU)
TL431AQDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(TAQG ~ TAQU)
TL431AQDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(TAQ3 ~ TAQS ~
TAQU)
TL431AQDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(TAQ3 ~ TAQS ~
TAQU)
TL431AQDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(TAQS ~ TAQU)
TL431AQDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(TAQS ~ TAQU)
TL431AQDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T7U
TL431AQDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T7U
TL431AQPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
4D
TL431AQPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
4D
TL431BCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(T3GG ~ T3GU)
TL431BCDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(T3GG ~ T3GU)
TL431BCDBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T3GG
TL431BCDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T3GG
TL431BCDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3G3 ~ T3GS ~
T3GU)
TL431BCDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3G3 ~ T3GS ~
T3GU)
TL431BCDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3G3 ~ T3GS ~
T3GU)
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431BCDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3G3 ~ T3GS ~
T3GU)
TL431BCDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T2U
TL431BCDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T2U
TL431BCDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
T431B
TL431BCLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
T431B
TL431BCLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
T431B
TL431BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL431BCP
TL431BCPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
4C
TL431BCPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
4C
TL431BCPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCPSRE4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BCPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T431B
TL431BID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z431B
TL431BIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(T3FG ~ T3FU)
Addendum-Page 5
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431BIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(T3FG ~ T3FU)
TL431BIDBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3FG
TL431BIDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3FG
TL431BIDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3F3 ~ T3FS ~
T3FU)
TL431BIDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3F3 ~ T3FS ~
T3FU)
TL431BIDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3F3 ~ T3FS ~
T3FU)
TL431BIDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3F3 ~ T3FS ~
T3FU)
TL431BIDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3U
TL431BIDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3U
TL431BIDCKTE4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3U
TL431BIDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3U
TL431BIDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z431B
TL431BIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z431B
TL431BIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
Z431B
TL431BIDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z431B
TL431BIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z431B
TL431BILP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
Z431B
TL431BILPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
Z431B
Addendum-Page 6
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431BILPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
Z431B
TL431BILPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
Z431B
TL431BIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL431BIP
TL431BIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL431BIP
TL431BIPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
4I
TL431BIPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
4I
TL431BQD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431BQ
TL431BQDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T3HU
TL431BQDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T3HU
TL431BQDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T3HU
TL431BQDBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T3HU
TL431BQDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3H3 ~ T3HS ~
T3HU)
TL431BQDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3H3 ~ T3HS ~
T3HU)
TL431BQDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3HS ~ T3HU)
TL431BQDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3HS ~ T3HU)
TL431BQDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T8U
TL431BQDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T8U
TL431BQDCKTE4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T8U
Addendum-Page 7
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431BQDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T8U
TL431BQDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431BQ
TL431BQDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431BQ
TL431BQDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431BQ
TL431BQDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431BQ
TL431BQLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 125
T431BQ
TL431BQLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 125
T431BQ
TL431BQLPM
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 125
T431BQ
TL431BQLPME3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 125
T431BQ
TL431BQLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 125
T431BQ
TL431BQLPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 125
T431BQ
TL431BQPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
3H
TL431BQPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
3H
TL431BQPSR
PREVIEW
SO
PS
8
2000
TBD
Call TI
Call TI
-40 to 125
TL431CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL431C
TL431CDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(T3CG ~ T3CS)
TL431CDBVRE4
ACTIVE
SOT-23
DBV
5
TBD
Call TI
Call TI
0 to 70
TL431CDBVRG4
ACTIVE
SOT-23
DBV
5
TBD
Call TI
Call TI
0 to 70
TL431CDBVT
ACTIVE
SOT-23
DBV
5
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
250
Addendum-Page 8
(T3CG ~ T3CS)
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431CDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T3CG
TL431CDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3C3 ~ T3CS ~
T3CU)
TL431CDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3C3 ~ T3CS ~
T3CU)
TL431CDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3CS ~ T3CU)
TL431CDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T3CS ~ T3CU)
TL431CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL431C
TL431CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
TL431C
TL431CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL431C
TL431CKTPR
OBSOLETE
PFM
KTP
2
TBD
Call TI
Call TI
0 to 70
TL431CLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431CLPB-TDJ
OBSOLETE
TO-92
LP
3
TBD
Call TI
Call TI
0 to 75
TL431CLPM
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431C
TL431CLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 70
TL431C
TL431CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL431CP
TL431CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL431CP
TL431CPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
43
TL431CPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
43
TL431CPSLE
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
TL431CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
Addendum-Page 9
TL431C
T431
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
TL431CPSRG4
ACTIVE
SO
PS
8
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
Device Marking
(4/5)
T431
TL431CPW
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TL431CPWE4
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TL431CPWG4
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TL431CPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TL431CPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TL431ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL431I
TL431IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3IG ~ T3IS)
TL431IDBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3IG
TL431IDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
T3IG
TL431IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3IG ~ T3IU)
TL431IDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3I3 ~ T3IS ~
T3IU)
TL431IDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3I3 ~ T3IS ~
T3IU)
TL431IDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3IS ~ T3IU)
TL431IDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T3IS ~ T3IU)
TL431IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL431I
TL431IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
TL431I
TL431IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL431I
TL431ILP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
TL431I
TL431ILPM
OBSOLETE
TO-92
LP
3
TBD
Call TI
Call TI
-40 to 85
Addendum-Page 10
T431
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431ILPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
-40 to 85
TL431I
TL431IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL431IP
TL431IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TL431IP
TL431IPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
3I
TL431IPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
3I
TL431MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TL431MJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TL431MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TL431QD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431Q
TL431QDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(T3QG ~ T3QU)
TL431QDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T3QG
TL431QDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(T3QG ~ T3QU)
TL431QDBVTE4
ACTIVE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
TL431QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3Q3 ~ T3QS ~
T3QU)
TL431QDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3Q3 ~ T3QS ~
T3QU)
TL431QDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3QS ~ T3QU)
TL431QDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T3QS ~ T3QU)
TL431QDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T6U
TL431QDCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T6U
Addendum-Page 11
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431QDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T6U
TL431QDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T6U
TL431QDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T431Q
TL431QPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
3Q
TL431QPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
3Q
TL432ACDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(T4BG ~ T4BU)
TL432ACDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T4B3 ~ T4BS ~
T4BU)
TL432ACDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T4B3 ~ T4BS ~
T4BU)
TL432ACDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T4BS ~ T4BU)
TL432ACDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T4BS ~ T4BU)
TL432AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(T4AG ~ T4AU)
TL432AIDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4A3 ~ T4AS ~
T4AU)
TL432AIDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4A3 ~ T4AS ~
T4AU)
TL432AIDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4A3 ~ T4AS ~
T4AU)
TL432AIDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4A3 ~ T4AS ~
T4AU)
TL432AIPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
2E
TL432AQDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T4DU
TL432AQDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T4DU
Addendum-Page 12
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL432AQDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T4DU
TL432AQDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T4D3 ~ T4DS ~
T4DU)
TL432AQDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T4D3 ~ T4DS ~
T4DU)
TL432AQDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T4DS ~ T4DU)
TL432AQDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T4DS ~ T4DU)
TL432AQPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
2F
TL432AQPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
2F
TL432BCDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TBCU
TL432BCDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TBCS ~ TBCU)
TL432BCDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TBCS ~ TBCU)
TL432BCDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(TBCS ~ TBCU)
TL432BCPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
2G
TL432BIDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4F3 ~ T4FS ~
T4FU)
TL432BIDBZRG4
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4F3 ~ T4FS ~
T4FU)
TL432BIDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4F3 ~ T4FS ~
T4FU)
TL432BIDBZTG4
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4F3 ~ T4FS ~
T4FU)
TL432BIPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
2H
TL432BQDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T4H3 ~ T4HS ~
T4HU)
Addendum-Page 13
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Device Marking
(4/5)
TL432BQDBZRG4
ACTIVE
SOT-23
DBZ
3
(T4H3 ~ T4HS ~
T4HU)
TL432BQDBZT
PREVIEW
SOT-23
DBZ
3
TBD
Call TI
Call TI
-40 to 125
TL432BQPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
TL432CDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
(T4CG ~ T4CU)
TL432CDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(T4CS ~ T4CU)
TL432CDBZTG4
OBSOLETE
SOT-23
DBZ
3
TBD
Call TI
Call TI
0 to 70
(T4CS ~ T4CU)
TL432CPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
2A
TL432IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(T4IG ~ T4IU)
TL432IDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4IS ~ T4IU)
TL432IDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(T4IS ~ T4IU)
TL432IPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
2B
TL432QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(T4QS ~ T4QU)
TL432QPK
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
2C
TL432QPKG3
ACTIVE
SOT-89
PK
3
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
2C
2J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 14
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL431A, TL431B, TL432A, TL432B :
• Automotive: TL431A-Q1, TL431B-Q1, TL432A-Q1, TL432B-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 15
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TL431ACDBVR
SOT-23
DBV
5
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
TL431ACDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TL431ACDBVRG4
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TL431ACDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431ACDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431ACDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431ACDBZT
SOT-23
DBZ
3
250
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431ACDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431ACDCKR
SC70
DCK
6
3000
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
TL431ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431ACDR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TL431ACDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431ACPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL431ACPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL431AIDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431AIDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
TL431AIDBVRG4
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431AIDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TL431AIDBVTG4
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431AIDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431AIDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431AIDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431AIDBZT
SOT-23
DBZ
3
250
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431AIDCKR
SC70
DCK
6
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431AIDCKT
SC70
DCK
6
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431AIDR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TL431AIDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431AIPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL431AQDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431AQDBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TL431AQDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431AQDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431AQDCKR
SC70
DCK
6
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431AQDCKT
SC70
DCK
6
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431BCDBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL431BCDBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL431BCDBVTG4
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431BCDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431BCDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431BCDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431BCDBZT
SOT-23
DBZ
3
250
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431BCDCKR
SC70
DCK
6
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431BCDCKT
SC70
DCK
6
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431BCPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL431BCPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL431BIDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431BIDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431BIDBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL431BIDBVTG4
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431BIDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431BIDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431BIDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431BIDBZT
SOT-23
DBZ
3
250
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431BIDCKR
SC70
DCK
6
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431BIDCKT
SC70
DCK
6
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431BIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431BIDR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TL431BIDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431BIPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TL431BQDBVR
SOT-23
DBV
5
3000
179.0
8.4
TL431BQDBVT
SOT-23
DBV
5
250
179.0
8.4
TL431BQDBZR
SOT-23
DBZ
3
3000
180.0
TL431BQDBZT
SOT-23
DBZ
3
250
180.0
TL431BQDCKR
SC70
DCK
6
3000
179.0
TL431BQDCKT
SC70
DCK
6
250
TL431BQDR
SOIC
D
8
2500
TL431CDBVR
SOT-23
DBV
5
TL431CDBVR
SOT-23
DBV
TL431CDBVT
SOT-23
DBV
TL431CDBVTG4
SOT-23
TL431CDBZR
TL431CDBZR
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.15
2.77
1.22
4.0
8.0
Q3
8.4
3.15
2.77
1.22
4.0
8.0
Q3
8.4
2.2
2.5
1.2
4.0
8.0
Q3
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL431CDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431CDR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TL431CDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431CPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL431CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL431IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431IDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
TL431IDBVRG4
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431IDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431IDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431IDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431IDR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TL431IDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL431IPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL431QDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431QDBVRG4
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431QDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL431QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL431QDCKR
SC70
DCK
6
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431QDCKT
SC70
DCK
6
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL431QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL432ACDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL432ACDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432ACDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432AIDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL432AIDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL432AIDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TL432AIDBZT
SOT-23
DBZ
3
250
178.0
9.2
TL432AIDBZT
SOT-23
DBZ
3
250
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.08
2.8
1.27
4.0
8.0
Q3
3.15
2.77
1.22
4.0
8.0
Q3
TL432AIPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432AQDBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL432AQDBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL432AQDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432AQDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432AQPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432BCDBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL432BCDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432BCDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432BCPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432BIDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432BIDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL432BIDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432BIDBZT
SOT-23
DBZ
3
250
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL432BIPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432BQDBZR
SOT-23
DBZ
3
3000
178.0
9.2
3.08
2.8
1.27
4.0
8.0
Q3
TL432BQDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432BQPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432CDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL432CDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432CPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TL432IDBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TL432IDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432IDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432IPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
TL432QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
TL432QPK
SOT-89
PK
3
1000
180.0
12.4
4.91
4.52
1.9
8.0
12.0
Q3
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL431ACDBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
TL431ACDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431ACDBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431ACDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431ACDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL431ACDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431ACDBZT
SOT-23
DBZ
3
250
180.0
180.0
18.0
TL431ACDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431ACDCKR
SC70
DCK
6
3000
202.0
201.0
28.0
TL431ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431ACDR
SOIC
D
8
2500
364.0
364.0
27.0
TL431ACDRG4
SOIC
D
8
2500
340.5
338.1
20.6
TL431ACPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL431ACPSR
SO
PS
8
2000
367.0
367.0
38.0
TL431AIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431AIDBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
TL431AIDBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431AIDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431AIDBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431AIDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL431AIDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431AIDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431AIDBZT
SOT-23
DBZ
3
250
180.0
180.0
18.0
TL431AIDCKR
SC70
DCK
6
3000
203.0
203.0
35.0
TL431AIDCKT
SC70
DCK
6
250
203.0
203.0
35.0
TL431AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431AIDR
SOIC
D
8
2500
364.0
364.0
27.0
TL431AIDRG4
SOIC
D
8
2500
340.5
338.1
20.6
TL431AIPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL431AQDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431AQDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431AQDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431AQDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431AQDCKR
SC70
DCK
6
3000
203.0
203.0
35.0
TL431AQDCKT
SC70
DCK
6
250
203.0
203.0
35.0
TL431BCDBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
TL431BCDBVT
SOT-23
DBV
5
250
203.0
203.0
35.0
TL431BCDBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431BCDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431BCDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL431BCDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431BCDBZT
SOT-23
DBZ
3
250
180.0
180.0
18.0
TL431BCDCKR
SC70
DCK
6
3000
203.0
203.0
35.0
TL431BCDCKT
SC70
DCK
6
250
203.0
203.0
35.0
TL431BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431BCPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL431BCPSR
SO
PS
8
2000
367.0
367.0
38.0
TL431BIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431BIDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431BIDBVT
SOT-23
DBV
5
250
203.0
203.0
35.0
TL431BIDBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431BIDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431BIDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL431BIDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431BIDBZT
SOT-23
DBZ
3
250
180.0
180.0
18.0
TL431BIDCKR
SC70
DCK
6
3000
203.0
203.0
35.0
TL431BIDCKT
SC70
DCK
6
250
203.0
203.0
35.0
TL431BIDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431BIDR
SOIC
D
8
2500
364.0
364.0
27.0
TL431BIDRG4
SOIC
D
8
2500
340.5
338.1
20.6
TL431BIPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL431BQDBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
TL431BQDBVT
SOT-23
DBV
5
250
203.0
203.0
35.0
TL431BQDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
Pack Materials-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL431BQDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431BQDCKR
SC70
DCK
6
3000
203.0
203.0
35.0
TL431BQDCKT
SC70
DCK
6
250
203.0
203.0
35.0
TL431BQDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431CDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431CDBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
TL431CDBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
TL431CDBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431CDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431CDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL431CDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431CDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431CDR
SOIC
D
8
2500
364.0
364.0
27.0
TL431CDRG4
SOIC
D
8
2500
340.5
338.1
20.6
TL431CPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL431CPSR
SO
PS
8
2000
367.0
367.0
38.0
TL431IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431IDBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
TL431IDBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431IDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431IDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431IDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431IDR
SOIC
D
8
2500
340.5
338.1
20.6
TL431IDR
SOIC
D
8
2500
364.0
364.0
27.0
TL431IDRG4
SOIC
D
8
2500
340.5
338.1
20.6
TL431IPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL431QDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431QDBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL431QDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TL431QDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL431QDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL431QDCKR
SC70
DCK
6
3000
203.0
203.0
35.0
TL431QDCKT
SC70
DCK
6
250
203.0
203.0
35.0
TL431QDR
SOIC
D
8
2500
340.5
338.1
20.6
TL432ACDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL432ACDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432ACDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL432AIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL432AIDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL432AIDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432AIDBZT
SOT-23
DBZ
3
250
180.0
180.0
18.0
TL432AIDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL432AIPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432AQDBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
Pack Materials-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL432AQDBVT
SOT-23
DBV
5
250
203.0
203.0
35.0
TL432AQDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432AQDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL432AQPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432BCDBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
TL432BCDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432BCDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL432BCPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432BIDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432BIDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL432BIDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL432BIDBZT
SOT-23
DBZ
3
250
180.0
180.0
18.0
TL432BIPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432BQDBZR
SOT-23
DBZ
3
3000
180.0
180.0
18.0
TL432BQDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432BQPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432CDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL432CDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432CPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TL432IDBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
TL432IDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432IDBZT
SOT-23
DBZ
3
250
202.0
201.0
28.0
TL432IPK
SOT-89
PK
3
1000
340.0
340.0
38.0
TL432QDBZR
SOT-23
DBZ
3
3000
202.0
201.0
28.0
TL432QPK
SOT-89
PK
3
1000
340.0
340.0
38.0
Pack Materials-Page 8
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPSF001F – JANUARY 1996 – REVISED JANUARY 2002
KTP (R-PSFM-G2)
PowerFLEX PLASTIC FLANGE-MOUNT PACKAGE
0.080 (2,03)
0.070 (1,78)
0.243 (6,17)
0.233 (5,91)
0.228 (5,79)
0.218 (5,54)
0.050 (1,27)
0.040 (1,02)
0.010 (0,25) NOM
0.130 (3,30) NOM
0.215 (5,46)
NOM
0.247 (6,27)
0.237 (6,02)
Thermal Tab
(See Note C)
0.287 (7,29)
0.277 (7,03)
0.381 (9,68)
0.371 (9,42)
0.100 (2,54)
0.090 (2,29)
0.032 (0,81) MAX
Seating Plane
0.090 (2,29)
0.180 (4,57)
0.004 (0,10)
0.005 (0,13)
0.001 (0,02)
0.031 (0,79)
0.025 (0,63)
0.010 (0,25) M
0.010 (0,25) NOM
Gage Plane
0.047 (1,19)
0.037 (0,94)
0.010 (0,25)
2°–ā6°
4073388/M 01/02
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
The center lead is in electrical contact with the thermal tab.
Dimensions do not include mold protrusions, not to exceed 0.006 (0,15).
Falls within JEDEC TO-252 variation AC.
PowerFLEX is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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