www.ctscorp.com 1 CTS Corporation Corporate Profile CTS Corporate Profile 3 F CTS Corporation was established in 1896 as Chicago Telephone Supply. F CTS Corporation designs, manufactures and sells a broad line of electronic components and sensors, and a provider of electronics manufacturing services (EMS), primarily serving the electronic needs of original equipment manufacturers (OEMs). F Major Markets Served: Automotive, Communications, Computer and Defense F Headquarters: Elkhart, Indiana (100 miles SE of Chicago). CTS is publicly traded on the New York Stock Exchange (CTS) F Annual Revenue: $500k million CTS Corporation Global Operations Electronic Components Automotive Sensors EMS Operations 4 Electronic Components Products ELTCC ECeramic Monoblock Duplexers ECeramic Monoblock Filters EClock Oscillators ECrystal Resonators EDIP Switches EEncoders EFuel Sender Elements EHeat Sinks EOCXO’s EPointing Devices and Cursor Controls EPiezoelectric Products EPotentiometers EResistor Networks EPower Switches ETCXO’s ETrimmers EVCSO’s EVCXO’s 5 Automotive Sensors Fuel Sender Belt Tension Sensor LTCC for Car Radar Exhaust Gas Recirculation Seat Position Sensor PPS Actuators Throttle Position Sensor & Electronic Throttle Control 6 Pedal Assembly Pedal Position Sensor Manufacturing Services (EMS) Design and Development Backplanes PCA Electronic Packaging Logistics Test Full System Integration 7 CTS Microelectronics FCTS Microelectronics Profile FCTS LTCC Product Examples CTS Microelectronics West Lafayette, Indiana •Founded in 1964 •Employees: 75 •ISO 9001 certified •MIL-PRF-38534 qualified and certified •MRP II class A certified Facilities EAdministrative Offices ELTCC Manufacturing EThick Film Manufacturing ESMT Assembly and Test EManufacturing Support EEngineering TOTAL 9 Size (Sq. Feet) 1,000 20,000 400 14,000 15,000 37,000 100,000 Cleanliness N/A 10,000 10,000 10,000 10,000 N/A Wireless Based LTCC Products - Examples 10 Tri-band VCO Diplexer 900 MHz Filter 1900 MHz Filter Hermetic LTCC Packages - Examples •18 GHz Radar Application •LTCC with cavities • 134 mm X 24 mm •Proof of design successful •Picture shows substrate without seal ring or heat spreader •10 GHz Down Converter •Backside Heat spreader •High frequency connectors •Microstrip feeds •Anti-Jam GPS Application •Cavities to mount chips •LTCC base with brazed seal ring and leads •Hermetic •39 mm X 57 mm •Approximately 76 mm X 46 mm •Hermetic •Chip and wire construction •Chip and wire construction •Proof of design successful •Digital MCM, 10 ICs, Most are ASICs •Low Volume Production 11 High Frequency LTCC Substrates - Examples RFIF Substrate RF Down Converter TD Course and LO Course Substrates 12 MIMC Substrates LNA and Exciter Substrates LTCC Substrate Array - Example 96 Segment Array for Bluetooth Application 13 LTCC Assembled Packages - Examples •Kovar seal ring Au88/12Ge attached to 1 mm thick •moly base with aluminum nitride network solder •attached with Pb90/10Sn solder •Backside has mounting studs Engine Controller •Seven FETs solder attached with Sn63/37Pb solder. •Control IC adhesively attached •130 Watts •50 mm X 50 mm •Spaceborne application •In low volume production 14 CTS Microelectronics LTCC Equipment LTCC Process Flow T y p ic a l P r o c e s s F lo w S e le c t T a p e S iz e P r e -C o n d itio n L ayer 1 L ayer 2 L ayer 3 … … … … … … … … … S ta b iliz e th e ta p e la y e r s fo r 3 0 m in u t e s a t 1 2 0 ° C . L ayer X F o r m V ia s F o r m V ia s F o r m V ia s F o r m V ia s .… C r e a te v ia h o le s w ith p u n c h , la se r , o r o th e r m e c h a n ic a l m e a n s. F ill V ia s F ill V ia s F ill V ia s F ill V ia s … ..F ill v ia s u sin g r e c o m m e n d e d m a te r ia ls a n d p r o c e ss in g C o n d u c to r C o n d u c to r C o n d u c to r C o n d u c to r … ..P a t te r n th e c o n d u c to r s u s in g r e c o m m e n d e d m a te r ia ls a n d p ro cesses. C o lla te / L a m in a te G r e e n C u t / S c r ib e B u r n o u t / C o f ir e S in g u la tio n 16 … … … … … … … … … S e le c t a p p lic a b le ta p e th ic k n e s s a n d t a p e s iz e . . … … … … … … … … ..A lig n a n d s ta c k la y e r s, la m in a te a t 3 0 0 0 to 5 0 0 0 P S I fo r 1 0 m in u t e s a t 7 0 °C . … … … … … … … … ..C u t o r s c r ib e g r e e n la m in a te u s in g la s e r , h o t k n ife , o r o t h e r r e c o m m e n d e d e q u ip m e n t . … … … … … … … … . B u r n o u t a n d c o fir e u sin g th e r e c o m m e n d e d o n e -s te p p r o file . … … … … … … … … .A ft e r t e s tin g a n d in sp e c t io n , p a r ts m a y b e c u t t o fin a l s iz e u s in g a d ia m o n d sa w , la se r , o r c e r a m ic s c r ib e r . I f d im e n sio n a l to le r a n c e is n o t e x tr e m e , th e p a r ts w h ic h w e r e p r e v io u sly g r e e n sc r ib e d m a y b e sn a p p ed . Via Punching - LTCC Baccini High Speed Punches *Also Have Ushio Punches 17 Screen Print - LTCC Baccini High Speed Printers *Used for via filling and screen printing. After printing, the vias and conductors have to be dried in an oven at 80 C to 120 C for 5 to 30 minutes. 18 Collate - LTCC Baccini Collators *Layer to layer vision alignment 19 Laminate - LTCC Isostatic Lamination Presses (ABB & PTC) *Stacked tape is vacuum packed in bags and pressed in hot water (70 C for approximately 10 minutes at 3,000 to 5,000 PSI) 20 Green Cut and Score - LTCC UHT G-Cut and PTC Hot Knifes *Ability to either singulate or score the substrate 21 Fire - LTCC 15 Zone Belt Kiln for Co-Fire (3 to 12 hours) *Also use Sierra Therm Box Kilns for Co-Fire (16 to 26 hours) 22 Continuity Test - LTCC Nidec-Read High Speed Continuity Tester 23 LTCC Equipment - Summary F F F F F F F F F F F F F F F F F F F F F 24 F Baccini High Speed Punches Ushio Punches Mitutoyo Marlin Coordinate Measurement Systems Baccini High Speed Printers MPM Printers With Vision Systems AMI Printers With Vision Systems Baccini Collators Tencor AS500 Profilemeter Isostatic Lamination Presses (ABB & PTC) Ozo Routers Convergent Energy Laser UHT G-Cut Hot Knife PTC Hot Knives Belt Kilns For Cofire Sierra Therm Box Kiln Nidec-Read High Speed Continuity Tester Teledyne Tac Continuity Testers OGP Smartscopes Cyberoptic Laser Profilometer Post Fire Belt Furnaces Teradyne W411 & GSI Lumonics W670 Passive Laser Trim Systems K&S Ceramic Saw CTS Microelectronics LTCC Design Guidelines LTCC - Main Advantages 26 F Parallel processing (compared to conventional thickfilm technology) F Mass production methods can be applied (automation capability) F Fabrication techniques are relatively simple and inexpensive F Electronic circuits can be integrated (using its hybrid nature) F Design and manufacture 3-dimensional circuits F Possibility of cutting tape / substrates into different shapes F Ability to bury passive components within the substrate allows for circuit size reduction (50% in comparison to a standard PCB) F Number of signal layers is almost unlimited F Ability to perform at frequencies at over 30 GHz F High resistance against ambient working temperatures (up to 350 C) F Good thermal conductivity compared to PCBs F Good match to semiconductor TCEs Typical Stackup - CTS Design Guidelines S eal R in g L ay er 2 0 Surface P ost F ire R esistor L ay er 1 9 L ay er 1 8 L ay er 1 7 L ay er 1 6 L ay er 1 5 B uried R esistor L ay er 1 4 L ay er 1 3 L ay er 1 2 L ay er 1 1 L ay er 1 0 L ay er 9 B uried R esistor L ay er 8 L ay er 7 L ay er 6 L ay er 5 L ay er 4 L ay er 3 L ay er 2 L ay er 1 H eat Sink B raze A u (2 C oats) B raze A u A u or A g C o nd uctor T ra nsition V ia F ill A u or A g C onductor A u o r A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u o r A g C onductor A u o r A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u or A g C onductor A u or A g V ia F ill A u o r A g C onductor T ran sition V ia Fill B raze A u B raze A u (2 C oats) Side M etal C onnections A u B raze or A g Solder 27 Primary LTCC Tape Systems Used at CTS Plate Size 6.5” x 6.5” Material 8” x 8” Max Active Area Max Active Area DuPont 951 4.688” x 4.688” 6.200” x 6.200” k = 7.8 (standard tape) DuPont 943 4.879” x 4.879” 6.451” x 6.451” k = 7.5 (low loss tape) Ferro A6 (M) (S) 4.539” x 4.539” 6.003” x 6.003” (M) k = 5.9 (microwave tape) (S) k = 5.9 (low cost microwave) Heraeus HL2000 5.353” x 5.353” 7.075” x 7.075” ENote: k = 7.3 (HERALOCK, near 0 shrink) Average shrinkage factors after co-fire are as follows: DuPont Ferro X and Y = 13% +/- .2% 15% +/- .2% Z = 15% +/- .5% 25% +/- .5% ESpecifications for Above Tape Systems are Available in CTS LTCC Design Guidelines 28 VIAS - CTS Design Guidelines ETypical EVia Sizes: 4,5,6,8 and 10 mil diameter - max 20 mils. sizes should be close to the tape thickness. EMinimum via edge spacing to desired fired edge - 10 mils. EMinimum via to via pitch within same tape layer - 2.5 x average via diameter. EMinimum via stagger between tape layers - 2 x via diameter. EStacking EMinimum of vias is acceptable through any number of tape layers. of one layer of via stagger is recommended for hermeticity. EConductor EThermal cover pads on through-layer vias are not recommended. vias are recommended as an 8 mil via diameter array. 2X Via Diameter Stagger 29 2.5X Average Via Diameter 10 mils Co-Fire Conductors - CTS Design Guidelines EMinimum line width - 4 mils. EMinimum line spacing - 4 mils. Internal Signal Lines EMinimum conductor spacing to via cover pad - 3 mils. E3 connections to vias less than 10 mils in diameter cover pad / catch pad 2 mils larger than the connecting via diameter. EVia mils Min. Space Cover/Catch Pad ELine E4 E2 mils Larger Ethan Via EDia. EMinimum conductor spacing to the line substrate edge minimum of 10 mils. ECo-fire conductor to co-fire conductor overlap minimum of 10 mils. mils Min. Line ESquare E4 Line End mils Min. Space Designed Substrate Edge EGold / Silver Interface - Mixed metal designs with silver traces / vias and external gold or solderable materials shall have the external tape layers via filled with Pd/Ag. 30 E 10 mils EMin. Space External Co-Fired Conductors - CTS Design Guidelines ESignal line width - minimum of 4 mils. EConductor ETab bond areas - minimum conductor width of 4 mils / minimum spacing 2 mils. EWire bond areas - co-fired with minimum of 4 mil lines and spaces. EConductor 31 Spacing - minimum of 4 mils. lines without via cover pad - square end. Post Fire Conductors - CTS Design Guidelines EMinimum line width - 5 mils. EMinimum spacing - 6 mils. EMinimum conductor-to-conductor overlaps - 5 mils for post fire to post fire conductors. EPost fire conductors to co-fire conductors - minimum of 8 mil overlap. EConductor E6 Spacing mil Min. ELaser E15 Probe Pads mils Sq. Min. ECovercoat 10 mils EWider than Resistor ELine Width E5 mils Min. EResistor EResistor E.030” 32 Size Sq. Min Overlap E5 mils Min Ground Planes - CTS Design Guidelines EGrid Pattern - minimum 10 mil lines and spaces. EEach plane shall be offset or a different grid angle pattern from the previous pattern. EPartial plane coverage of less than 75% of the designed substrate is not recommended. EInternal E10 plane perimeter to the designed substrate edge - minimum of 10 mils. mil minimum space shall separate the plane pattern and any feed-through signal or thermal via. EExternal plane perimeter to the fired substrate edge - minimum of 10 mils. Figure 3 10 mils Min. Space 33 Stagger based on grid line width 10 mils Min. Space Designed Substrate Edge Co-Fired (Buried) Resistors - CTS Design Guidelines EResistor to conductor overlap - 5 mils for co-fire resistors to co-fire conductors. EExposed conductor on either side of the resistor - minimum of 5 mils exposed. EResistors EResistor EAs-fired EBuried - designed with 100% of nominal value. size - minimum of 30 mils by 30 mils. resistor tolerance - minimum of +/- 30%. Resistor Capability - 10 ohms to 10 K EResistor/Conductor EOverlap E5 mils Min. EResistor ELength EResistor EWidth 34 E5 mils Min. Post Fire Resistors - CTS Design Guidelines EResistor size - minimum of 30 mils by 30 mils. EResistor to conductor overlap - minimum of 5 mils for post fire resistors to post fire conductors. EMinimum of 8 mils of overlap and 8 mils of exposed conductor on either side of the resistor shall be for post fired resistors to co-fired conductors. EResistors - aspect ratio 75%of the nominal value. EAll resistors shall be designed using the sheet resistivities as described in 6.2.7 of CTS design guidelines. ELaser EPost probe pad size - minimum of 15 mils square. Fire Resistor Capability - 100 - 1MEG ohms/sq. Resistor/Conductor Overlap Resistor Length Laser Trim Keep-out (one side only) 15 mils Min. 35 8 mils Min. Resistor Width 8 mils Min. Resistor Overcoat - CTS Design Guidelines ECovercoat Width - 10 mils wider than the designed resistor. ECovercoat Length - same as the designed resistor length, including overlap. ECovercoat is applied to all resistors designed with 100 ohms/square and 1 Meg ohms/square and higher resistor formulations. EActive 36 trim resistors shall have the covercoat applied to all or none of the resistors. Brazing - CTS Design Guidelines EBrazing E2 area consists of two conductor patterns: (1) adhesion (2) solderability. mils larger in width and 1 mil larger in length than the nominal pad design. EEnd lead pads - 2x the nominal pad design - up to 50 mils maximum. EDielectric pattern - combed shape - 2 mil conductor overlap. EDielectric fingers - extend beyond lead pad (opposite end of lead-out end) by 5 mils. EDielectric comb base - minimum of 15 mils wide. E(2) shall be the nominal designed pad size. ELead Lead Pads st 1 Cond. Pass is 1 mil > than Nom. Design Pad Size. (3 sides) pitch - minimum of 20 mils. End Lead Pad Designed Substrate Edge 37 Dielectric 2 mil Overlap of 1st Conductor Pass Dielectric 5 mil Min. Leads Seal Ring - CTS Design Guidelines ENominal EOutside ENominal EOutside E1st conductor brazing pattern - 40 mils wider than nominal seal ring width. corners of the conductor pattern - square. brazing conductor pattern - 40 mils wider than nominal seal ring width. corners of the conductor pattern - 20 mils less than nominal inside seal ring radius. conductor pattern - 2 mils smaller in width than the nominal designed size. Seal Ring EConductor EConductor Radius EBased on Seal Ring ERadius 38 ESeal Pattern Ring EConductor EPattern E40 mils Wider than ESeal Ring Width Cavities - CTS Design Guidelines ECavities or holes - produced in the unfired state (punch, router or laser). ECavity floor - minimum fired thickness 20 mils. ECavity walls - minimum of 100 mils wide. EStepped EVia cavities - acceptable. edge spacing to the cavity wall - minimum of 10 mils. ESignal and thermal vias in the cavity floor - acceptable. Cavities 10 mils Min 39 100 mils 100 mils Design Transfer - CTS Design Guidelines EGerber EEach data - 274x format is preferred. via, co-fire and post fire screening pass requires 1 Gerber file. EComposites EGerber EPaper data origins - coincident throughout the stackup. plots of each screening layers, vias and layer definitions - shall be included. EAutocad or .dxf formatted file - preferred for the generation of manufacturing documentation. ENetwork continuity testing - netlist with reference designators is required. EPreferred 40 sides - shall be exploded. netlist format - ASCII CAD Capabilities - CTS Design Guidelines •Intergraph ATDesigner V12.4. •MicroStation V5. •AutoCAD Versions 14 and 2000. •Innoveda’s FabFactory (formerly CAM350) 41 Summary •CTS is a Proven High Volume, High Reliability, Quality Manufacturer •15 Years of LTCC experience •40 Years of module experience •Focused on Technology Development, Productivity Improvement and Cost Reduction •In House Experienced LTCC Engineering Team •In House LTCC Prototype Labs •State-of-the-art Manufacturing Facilities •Please Visit us in West Lafayette, Indiana 42