16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC AD5421 FEATURES GENERAL DESCRIPTION 16-bit resolution and monotonicity Pin selectable NAMUR-compliant ranges 4 mA to 20 mA 3.8 mA to 21 mA 3.2 mA to 24 mA NAMUR-compliant alarm currents Downscale alarm current = 3.2 mA Upscale alarm current = 22.8 mA/24 mA Total unadjusted error (TUE): 0.05% maximum INL error: 0.0035% FSR maximum Output TC: 3 ppm/°C typical Quiescent current: 300 μA maximum Flexible SPI-compatible serial digital interface with Schmitt triggered inputs On-chip fault alerts via FAULT pin or alarm current Automatic readback of fault register on each write cycle Slew rate control function Gain and offset adjust registers On-chip reference TC: 4 ppm/°C maximum Selectable regulated voltage output Loop voltage range: 5.5 V to 52 V Temperature range: −40°C to +105°C TSSOP package HART compatible The AD5421 is a complete, loop-powered, 4 mA to 20 mA digital-to-analog converter (DAC) designed to meet the needs of smart transmitter manufacturers in the industrial control industry. The DAC provides a high precision, fully integrated, low cost solution in a compact TSSOP package. The AD5421 includes a regulated voltage output that is used to power itself and other devices in the transmitter. This regulator provides a regulated 1.8 V to 12 V output voltage. The AD5421 also contains 1.22 V and 2.5 V references, thus eliminating the need for a discrete regulator and voltage reference. The AD5421 can be used with standard HART® FSK protocol communication circuitry without any degradation in specified performance. The high speed serial interface is capable of operating at 30 MHz and allows for simple connection to commonly used microprocessors and microcontrollers via a SPI-compatible, 3-wire interface. The AD5421 is guaranteed monotonic to 16 bits. It provides 0.0015% integral nonlinearity, 0.0012% offset error, and 0.0006% gain error under typical conditions. The AD5421 is available in a 28-lead TSSOP and is specified over the extended industrial temperature range of −40°C to +105°C. APPLICATIONS Industrial process control 4 mA to 20 mA loop-powered transmitters Smart transmitters FUNCTIONAL BLOCK DIAGRAM LOOP VOLTAGE MONITOR FAULT SYNC SCLK SDIN SDO LDAC RANGE0 RANGE1 VLOOP REG_SEL0 REG_SEL1 REG_SEL2 REGOUT REGIN INPUT REGISTER CONTROL LOGIC VOLTAGE REGULATOR DRIVE RSET 24kΩ 16 GAIN/OFFSET ADJUSTMENT REGISTERS 16-BIT DAC TEMPERATURE SENSOR 11.5kΩ 52Ω LOOP– ALARM_CURRENT_DIRECTION VREF AD5421 RINT/REXT REFOUT2 REFOUT1 REFIN CIN REXT1 REXT2 COM 09128-001 IODVDD DVDD Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD5421 TABLE OF CONTENTS Features .............................................................................................. 1 On-Chip ADC ............................................................................ 21 Applications ....................................................................................... 1 Voltage Regulator ....................................................................... 21 General Description ......................................................................... 1 Loop Current Slew Rate Control .............................................. 21 Functional Block Diagram .............................................................. 1 Power-On Default ...................................................................... 21 Revision History ............................................................................... 2 HART Communications ........................................................... 22 Specifications..................................................................................... 3 Serial Interface ................................................................................ 24 AC Performance Characteristics ................................................ 7 Input Shift Register .................................................................... 24 Timing Characteristics ................................................................ 7 Register Readback ...................................................................... 24 Absolute Maximum Ratings............................................................ 9 DAC Register .............................................................................. 25 Thermal Resistance ...................................................................... 9 Control Register ......................................................................... 26 ESD Caution .................................................................................. 9 Fault Register .............................................................................. 27 Pin Configuration and Function Descriptions ........................... 10 Offset Adjust Register ................................................................ 28 Typical Performance Characteristics ........................................... 12 Gain Adjust Register .................................................................. 28 Terminology .................................................................................... 18 Applications Information .............................................................. 30 Theory of Operation ...................................................................... 19 Determining the Expected Total Error ................................... 30 Fault Alerts .................................................................................. 19 Thermal and Supply Considerations ....................................... 31 External Current Setting Resistor ............................................ 20 Outline Dimensions ....................................................................... 32 Loop Current Range Selection.................................................. 20 Ordering Guide .......................................................................... 32 Connection to Loop Power Supply .......................................... 20 REVISION HISTORY 2/11—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD5421 SPECIFICATIONS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 ACCURACY, INTERNAL RSET Resolution Total Unadjusted Error (TUE) 2 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Min 16 −0.126 −0.041 −0.22 −0.12 Gain Error TC 3 Full-Scale Error Full-Scale Error TC3 Downscale Alarm Current Upscale Alarm Current ACCURACY, EXTERNAL RSET (24 kΩ) Resolution Total Unadjusted Error (TUE)2 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error TC3 Gain Error Gain Error TC3 Full-Scale Error Full-Scale Error TC3 Downscale Alarm Current Upscale Alarm Current Max Unit 3.19 22.77 3.21 22.83 Bits % FSR % FSR % FSR % FSR ppm FSR % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C mA mA 23.97 24.03 mA 16 −0.048 −0.027 −0.12 −0.06 +0.048 +0.027 +0.12 +0.06 −0.0035 −0.08 −1 −0.056 −0.008 3 Offset Error TC Gain Error Typ −0.107 −0.035 −0.126 −0.041 ±0.0064 ±0.011 210 ±0.0015 ±0.006 ±0.0008 1 ±0.0058 4 ±0.0065 5 +0.126 +0.041 +0.22 +0.12 +0.0035 +0.08 +1 +0.056 +0.008 +0.107 +0.035 +0.126 +0.041 3.19 22.79 3.21 22.81 Bits % FSR % FSR % FSR % FSR ppm FSR % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C mA mA 23.99 24.01 mA −0.0035 −0.08 −1 −0.021 −0.007 −0.03 −0.023 −0.047 −0.028 ±0.002 ±0.003 40 ±0.0015 ±0.006 ±0.0012 0.5 ±0.0006 1 ±0.0017 1 +0.0035 +0.08 +1 +0.021 +0.007 +0.03 +0.023 +0.047 +0.028 Rev. 0 | Page 3 of 32 Test Conditions/Comments C grade C grade, TA = 25°C B grade B grade, TA = 25°C Drift after 1000 hours at TA = 125°C C grade B grade Guaranteed monotonic TA = 25°C TA = 25°C TA = 25°C 4 mA to 20 mA and 3.8 mA to 21 mA ranges 3.2 mA to 24 mA range Assumes ideal resistor C grade C grade, TA = 25°C B grade B grade, TA = 25°C Drift after 1000 hours at TA = 125°C C grade B grade Guaranteed monotonic TA = 25°C TA = 25°C TA = 25°C 4 mA to 20 mA and 3.8 mA to 21 mA ranges 3.2 mA to 24 mA range AD5421 Parameter1 OUTPUT CHARACTERISTICS3 Loop Compliance Voltage4 Min 75 2.498 Output Voltage Drift vs. Time3 Capacitive Load3 Load Current3, 6 Short-Circuit Current3 Power Supply Sensitivity3 Thermal Hysteresis3 Load Regulation3 100 V V ppm FSR 15 ppm FSR 1.2 μA/mA REGOUT < 5.5 V, loop current = 24 mA REGOUT = 12 V, loop current = 24 mA Drift after 1000 hours at TA = 125°C, loop current = 12 mA, internal RSET Drift after 1000 hours at TA = 125°C, loop current = 12 mA, external RSET Loop current = 12 mA, load current from REGOUT = 5 mA See Figure 19 for a load line graph Stable operation Loop current = 12 mA 2 400 3 1 kΩ mH μA/V MΩ ppm FSR/°C ppm FSR/°C 50 0.2 nA p-p mV rms 195 256 nA/√Hz nA/√Hz 2.5 800 V MΩ For specified performance V ppm/°C ppm/°C μV p-p nV/√Hz nV/√Hz ppm nF mA mA μV/V ppm ppm mV/mA Ω TA = 25°C C grade B grade 0.1 12 Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density3 Short-Circuit Current Line Regulation3 Test Conditions/Comments 50 Noise Spectral Density Load Regulation3 Output Impedance REFOUT2 Pin Output Voltage Output Impedance REGOUT OUTPUT Output Voltage Output Voltage TC3 Output Voltage Accuracy Externally Available Current3, 6 Unit 0 Output Noise 0.1 Hz to 10 Hz 500 Hz to 10 kHz REFERENCE INPUT (REFIN PIN)3 Reference Input Voltage5 DC Input Impedance REFERENCE OUTPUTS REFOUT1 Pin Output Voltage Temperature Coefficient Max LOOP− + 5.5 LOOP− + 12.5 Loop Current Long-Term Stability Loop Current Error vs. REGOUT Load Current Resistive Load Inductive Load Power Supply Sensitivity Output Impedance Output TC Typ 1.18 2.5 1.5 2 7.5 245 70 200 10 4 6.5 2 285 5 0.1 0.1 2.503 4 10 1.227 72 1.28 V kΩ 12 V ppm/°C % mA 1.8 −4 3.15 110 ±2 12 0.2 +4 23 500 10 8 mA mV/V mV/V mV/mA Rev. 0 | Page 4 of 32 Loop current = 12 mA, internal RSET Loop current = 12 mA, external RSET HART bandwidth; measured across 500 Ω load At 1 kHz At 10 kHz At 1 kHz At 10 kHz Drift after 1000 hours at TA = 125°C Stable operation Short circuit to COM First temperature cycle Second temperature cycle Measured at 0 mA and 1 mA loads TA = 25°C Voltage regulator output See Table 10 Assuming 4 mA flowing in the loop and during HART communications Internal NMOS External NMOS AD5421 Parameter 1 Inductive Load Capacitive Load ADC ACCURACY Die Temperature VLOOP Input DVDD OUTPUT Output Voltage Externally Available Current3, 6 Short-Circuit Current Load Regulation DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Input Current Pin Capacitance DIGITAL OUTPUTS3 SDO Pin Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Pin Output Low Voltage, VOL Output High Voltage, VOH FAULT THRESHOLDS ILOOP Under ILOOP Over Temp 140°C Min 2 Max ±5 ±1 Unit mH μF Test Conditions/Comments Stable operation Stable operation °C % Can be overdriven up to 5.5 V 3.17 3.15 3.3 3.48 7.7 11 V mA mA mV/mA 0.7 × IODVDD 0.25 × IODVDD 0.21 0.63 1.46 −0.015 +0.015 5 0.4 IODVDD − 0.5 −0.01 +0.01 5 V V V V V μA pF 0.4 ILOOP – 0.01% FSR ILOOP + 0.01% FSR 133 IODVDD = 1.8 V IODVDD = 3.3 V IODVDD = 5.5 V Per pin Per pin V V mA mA °C °C 0.3 0.6 V V 260 Measured at 0 mA and 3 mA loads SCLK, SYNC, SDIN, LDAC V V μA 90 5.5 1.71 Assuming 4 mA flowing in the loop and during HART communications pF IODVDD − 0.5 Temp 100°C VLOOP 6V VLOOP 12V POWER REQUIREMENTS REGIN IODVDD Quiescent Current Typ 50 10 52 5.5 300 1 V V μA Fault removed when temperature ≤ 125°C Fault removed when temperature ≤ 85°C Fault removed when VLOOP ≥ 0.4 V Fault removed when VLOOP ≥ 0.7 V With respect to LOOP− With respect to COM Temperature range: −40°C to +105°C; typical at +25°C. Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers. 3 Guaranteed by design and characterization; not production tested. 4 The voltage between LOOP− and REGIN must be 5.5 V or greater. 5 The AD5421 is factory calibrated with an external 2.5 V reference connected to REFIN. 6 This is the current that the output is capable of sourcing. The load current originates from the loop and, therefore, contributes to the total current consumption figure. 2 Rev. 0 | Page 5 of 32 AD5421 Loop voltage = 24 V; REFIN = REFOUT1 (2.5 V internal reference); RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1, 2 ACCURACY, INTERNAL RSET Total Unadjusted Error (TUE) 3 Relative Accuracy (INL) Offset Error Offset Error TC Gain Error Gain Error TC Full-Scale Error Full-Scale Error TC ACCURACY, EXTERNAL RSET (24 kΩ) Total Unadjusted Error (TUE)3 Relative Accuracy (INL) Offset Error Offset Error TC Gain Error Gain Error TC Full-Scale Error Full-Scale Error TC Min −0.157 −0.117 −0.004 −0.004 −0.04 −0.025 −0.128 −0.093 −0.157 −0.117 C Grade Typ ±0.0172 ±0.0015 ±0.0025 1 ±0.0137 5 ±0.0172 6 Max Unit +0.157 +0.117 +0.004 +0.004 +0.04 +0.025 % FSR % FSR % FSR % FSR % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C +0.128 +0.093 +0.157 +0.117 Test Conditions/Comments TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C Assumes ideal resistor −0.133 −0.133 −0.004 −0.004 −0.029 −0.029 −0.11 −0.106 −0.133 −0.133 ±0.0252 ±0.0015 ±0.0038 0.5 ±0.0197 2 ±0.0252 2 +0.133 +0.133 +0.004 +0.004 +0.029 +0.029 +0.11 +0.106 +0.133 +0.133 1 % FSR % FSR % FSR % FSR % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C Temperature range: −40°C to +105°C; typical at +25°C. Specifications guaranteed by design and characterization; not production tested. 3 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers. 2 Rev. 0 | Page 6 of 32 AD5421 AC PERFORMANCE CHARACTERISTICS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1 DYNAMIC PERFORMANCE Loop Current Settling Time Loop Current Slew Rate AC Loop Voltage Sensitivity 1 Min Typ Max 50 400 1.3 Unit Test Conditions/Comments μs μA/μs μA/V To 0.1% FSR, CIN = open circuit CIN = open circuit 1200 Hz to 2200 Hz, 5 V p-p, RL = 3 kΩ Temperature range: −40°C to +105°C; typical at +25°C. TIMING CHARACTERISTICS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX. Table 4. Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Limit at TMIN, TMAX 33 17 17 17 10 25 5 5 25 10 70 0 70 Unit ns min ns min ns min ns min ns min μs min ns min ns min μs min ns min ns max ns min ns max Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Minimum SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge LDAC pulse width low SCLK rising edge to SDO valid (CL SDO = 30 pF) SYNC falling edge to SCLK rising edge setup time SYNC rising edge to SDO tristate (CL SDO = 30 pF) 1 Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 2 and Figure 3. 2 Table 5. SPI Watchdog Timeout Periods T0 0 0 0 0 1 1 1 1 1 Parameter 1 T1 T2 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Min 43 87 436 873 1746 2619 3493 4366 Typ 50 100 500 1000 2000 3000 4000 5000 Max 59 117 582 1163 2326 3489 4652 5814 Specifications guaranteed by design and characterization; not production tested. Rev. 0 | Page 7 of 32 Unit ms ms ms ms ms ms ms ms AD5421 Timing Diagrams t1 t12 SCLK 1 8 2 9 10 11 t3 SDIN D23 D16 t4 D15 12 22 24 23 t2 D14 D13 D2 D1 D0 t8 t7 t13 D15 SDO t6 D14 D13 D2 D1 D0 t5 t11 SYNC t10 09128-002 t9 LDAC Figure 2. Serial Interface Timing Diagram SDIN 1 8 9 D23 D16 D15 24 D0 1 8 D23 D16 INPUT WORD SPECIFIES REGISTER TO BE READ SDO 9 24 D15 D0 NOP OR REGISTER ADDRESS D15 UNDEFINED DATA D0 SPECIFIED REGISTER DATA CLOCKED OUT SYNC Figure 3. Readback Timing Diagram Rev. 0 | Page 8 of 32 09128-003 SCLK AD5421 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 6. Parameter REGIN to COM REGOUT to COM Digital Inputs to COM RANGE0, RANGE1, RINT/REXT, ALARM_CURRENT_DIRECTION, REG_SEL0, REG_SEL1, REG_SEL2 Digital Inputs to COM SCLK, SDIN, SYNC, LDAC Digital Outputs to COM SDO, FAULT REFIN to COM REFOUT1, REFOUT2 VLOOP to COM LOOP− to COM DVDD to COM IODVDD to COM REXT1, CIN to COM REXT2 to COM DRIVE to COM Operating Temperature Range (TA) Industrial Storage Temperature Range Junction Temperature (TJ MAX) Power Dissipation Lead Temperature, Soldering (10 sec) ESD Human Body Model Field Induced Charged Device Model Machine Model Rating −0.3 V to +60 V −0.3 V to +14 V −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE −0.3 V to IODVDD + 0.3 V or +7 V (whichever is less) −0.3 V to IODVDD + 0.3 V or +7 V (whichever is less) −0.3 V to +7 V −0.3 V to +4.7 V −0.3 V to +60 V −5 V to +0.3 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +4.3 V −0.3 V to +0.3 V −0.3 V to +11 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 28-Lead TSSOP_EP (RE-28-2) ESD CAUTION −40°C to +105°C −65°C to +150°C 125°C (TJ MAX − TA)/θJA JEDEC Industry Standard J-STD-020 3 kV 1.5 kV 200 V Rev. 0 | Page 9 of 32 θJA 32 θJC 9 Unit °C/W AD5421 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IODVDD 1 28 REGOUT SDO 2 27 REGIN SCLK 3 26 DRIVE SDIN 5 AD5421 LDAC 6 TOP VIEW (Not to Scale) FAULT 7 DVDD 8 25 VLOOP 24 LOOP– 23 REXT2 22 REXT1 21 CIN ALARM_CURRENT_DIRECTION 9 20 REFOUT1 RINT/REXT 10 19 REFOUT2 RANGE0 11 18 REFIN RANGE1 12 17 REG_SEL0 COM 13 16 REG_SEL1 COM 14 15 REG_SEL2 NOTES 1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE SAME POTENTIAL AS THE COM PIN AND TO A COPPER PLANE FOR OPTIMUM THERMAL PERFORMANCE. 09128-004 SYNC 4 Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic IODVDD 2 SDO 3 SCLK 4 SYNC 5 6 SDIN LDAC 7 FAULT 8 9 DVDD ALARM_ CURRENT_ DIRECTION 10 RINT/REXT 11, 12 RANGE0, RANGE1 COM REG_SEL2, REG_SEL1, REG_SEL0 REFIN REFOUT2 REFOUT1 13, 14 15, 16, 17 18 19 20 Description Digital Interface Supply Pin. Digital thresholds are referenced to the voltage applied to this pin. A voltage from 1.71 V to 5.5 V can be applied to this pin. Serial Data Output. Used to clock data from the input shift register. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This input operates at clock speeds up to 30 MHz. Frame Synchronization Input, Active Low. This is the frame synchronization signal for the serial interface. When SYNC is low, data is transferred on the falling edge of SCLK. The input shift register data is latched on the rising edge of SYNC. Serial Data Input. Data must be valid on the falling edge of SCLK. Load DAC Input, Active Low. This pin is used to update the DAC register and, consequently, the output current. If LDAC is tied permanently low, the DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is delayed until the falling edge of LDAC. The LDAC pin should not be left unconnected. Fault Alert Output Pin, Active High. This pin is asserted high when a fault is detected. Detectable faults are loss of SPI interface control, communication error (PEC), loop current out of range, insufficient loop voltage, and overtemperature. For more information, see the Fault Alerts section. 3.3 V Digital Power Supply Output. This pin should be decoupled to COM with 100 nF and 1 μF capacitors. Alarm Current Direction Select. This pin is used to select whether the alarm current is upscale (22.8 mA/24 mA) or downscale (3.2 mA). Connecting this pin to DVDD selects an upscale alarm current (22.8 mA/24 mA); connecting this pin to COM selects a downscale alarm current (3.2 mA). For more information, see the Power-On Default section. Current Setting Resistor Select. When this pin is connected to DVDD, the internal current setting resistor is selected. When this pin is connected to COM, the external current setting resistor is selected. An external resistor can be connected between the REXT1 and REXT2 pins. Digital Input Pins. These two pins select the loop current range (see the Loop Current Range Selection section). Ground Reference Pin for the AD5421. These three pins together select the regulator output (REGOUT) voltage (see the Voltage Regulator section). Reference Voltage Input. VREFIN = 2.5 V for specified performance. Internal Reference Voltage Output (1.22 V). Internal Reference Voltage Output (2.5 V). Rev. 0 | Page 10 of 32 AD5421 Pin No. 21 Mnemonic CIN 22, 23 REXT1, REXT2 24 25 LOOP− VLOOP 26 DRIVE 27 REGIN 28 REGOUT EPAD Exposed Pad Description External Capacitor Connection and HART FSK Input. An external capacitor connected from CIN to COM implements an output slew rate control function (see the Loop Current Slew Rate Control section). HART FSK signaling can also be coupled through a capacitor to this pin (see the HART Communications section). Connection for External Current Setting Resistor. A precision 24 kΩ resistor can be connected between these pins for improved performance. Loop Current Return Pin. Voltage Input Pin. Voltage input range is 0 V to 2.5 V. The voltage applied to this pin is digitized to eight bits, which are available in the fault register. This pin can be used for general-purpose voltage monitoring, but it is intended for monitoring of the loop supply voltage. Connecting the loop voltage to this pin via a 20:1 resistor divider allows the AD5421 to monitor and feed back the loop voltage. The AD5421 also generates an alert if the loop voltage is close to the minimum operating value (see the Loop Voltage Fault section). Gate Connection for External Depletion Mode MOSFET. For more information, see the Connection to Loop Power Supply section. Voltage Regulator Input. The loop voltage can be connected directly to this pin. Or, to reduce on-chip power dissipation, an external pass transistor can be connected at this pin to stand off the loop voltage. For more information, see the Connection to Loop Power Supply section. The REGIN pin should be decoupled to the LOOP− pin with a 100 nF capacitor. Voltage Regulator Output. Pin selectable values are from 1.8 V to 12 V via the REG_SEL0, REG_SEL1, and REG_SEL2 pins (see the Voltage Regulator section). The exposed paddle should be connected to the same potential as the COM pin and to a copper plane for optimum thermal performance. Rev. 0 | Page 11 of 32 AD5421 TYPICAL PERFORMANCE CHARACTERISTICS 0.015 EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET 0.8 OFFSET ERROR (% FSR) 0.010 0.4 0.2 0 –0.2 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C 4mA TO 20mA RANGE EXT VREF EXT RSET –0.4 –0.6 –0.8 0 10k 20k 0 30k 40k 50k 60k DAC CODE VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω EXT NMOS –0.010 –40 –15 1.0 0.03 0.8 0.02 85 0.01 GAIN ERROR (% FSR) 0.4 0.2 0 –0.2 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C 4mA TO 20mA RANGE EXT VREF EXT RSET –0.4 –0.6 –0.8 0 10k 20k 0 –0.01 –0.02 VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω EXT NMOS –0.03 –0.04 EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET –0.05 30k 40k 50k 60k DAC CODE –0.06 –40 09128-006 –15 60 85 Figure 9. Gain Error vs. Temperature 0.0012 RLOAD = 250Ω TA = 25°C 4mA TO 20mA RANGE 0 35 TEMPERATURE (°C) Figure 6. Differential Nonlinearity Error vs. Code 0.01 10 0.0010 MAX INL 0.0008 INL ERROR (% FSR) –0.01 –0.02 –0.03 –0.05 –0.06 0 10k EXT, RSET EXT, NMOS EXT, 24V EXT, RSET EXT, NMOS INT, 24V EXT, RSET EXT, NMOS INT, 52V INT, RSET INT, NMOS EXT, 24V INT, RSET INT, NMOS INT, 24V INT, RSET INT, NMOS INT, 52V 20k 30k 40k 0.0004 0.0002 0 –0.0002 EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω –0.0004 MIN INL –0.0006 50k DAC CODE 60k 09128-007 VREF VREF VREF VREF VREF VREF –0.04 0.0006 Figure 7. Total Unadjusted Error vs. Code –0.0008 –40 –15 10 35 60 85 TEMPERATURE (°C) Figure 10. Integral Nonlinearity Error vs. Temperature Rev. 0 | Page 12 of 32 09128-010 DNL ERROR (LSB) 60 Figure 8. Offset Error vs. Temperature 0.6 TOTAL UNADJUSTED ERROR (% FSR) 35 TEMPERATURE (°C) Figure 5. Integral Nonlinearity Error vs. Code –1.0 10 09128-009 –1.0 0.005 –0.005 09128-005 INL ERROR (LSB) 0.6 09128-008 1.0 AD5421 0.5 0.0006 MAX INL 0.4 0.0004 0.3 VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω 0.1 0 –0.1 MIN DNL –0.2 –0.3 0.0002 0 MIN INL –0.0002 RLOAD = 250Ω TA = 25°C 3.8mA TO 21mA RANGE EXT VREF EXT RSET –0.0004 –0.4 –15 10 35 60 85 TEMPERATURE (°C) –0.0006 09128-011 –0.5 –40 0 –0.01 VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω EXT NMOS 50 60 –0.05 EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET –15 10 35 60 85 TEMPERATURE (°C) 0.0027 0.0025 0.0023 0.0021 0.0019 RLOAD = 250Ω TA = 25°C 3.8mA TO 21mA RANGE EXT VREF EXT RSET 0.0017 0.0015 0 0.0024 0.03 OFFSET ERROR (% FSR) 0.02 0.01 0 –0.01 VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω EXT NMOS EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET 10 50 60 0.0020 0.0018 0.0016 0.0014 0.0012 35 60 TEMPERATURE (°C) 85 09128-013 –15 40 RLOAD = 250Ω TA = 25°C 3.8mA TO 21mA RANGE EXT VREF EXT RSET 0.0022 –0.06 –40 30 Figure 15. Total Unadjusted Error vs. Loop Supply Voltage 0.04 –0.05 20 LOOP SUPPLY VOLTAGE (V) Figure 12. Total Unadjusted Error vs. Temperature –0.04 10 Figure 13. Full-Scale Error vs. Temperature 0.0010 0 10 20 30 40 50 LOOP SUPPLY VOLTAGE (V) Figure 16. Offset Error vs. Loop Supply Voltage Rev. 0 | Page 13 of 32 60 09128-016 –0.04 –0.06 –40 FULL-SCALE ERROR (% FSR) 40 09128-015 TOTAL UNADJUSTED ERROR (% FSR) 0.01 09128-012 TOTAL UNADJUSTED ERROR (% FSR) 0.02 –0.03 30 0.0029 0.03 –0.02 20 Figure 14. Integral Nonlinearity Error vs. Loop Supply Voltage 0.04 –0.03 10 LOOP SUPPLY VOLTAGE (V) Figure 11. Differential Nonlinearity Error vs. Temperature –0.02 0 09128-014 INL ERROR (% FSR) DNL ERROR (LSB) MAX DNL 0.2 AD5421 0.0005 COMPLIANCE VOLTAGE HEADROOM (V) 0.0010 0 –0.0005 –0.0010 –0.0015 0 10 20 30 40 50 60 LOOP SUPPLY VOLTAGE (V) 4.55 4.50 4.45 4.40 4.35 –40 0.0025 6 LOOP CURRENT ERROR (µA) 7 0.0020 0.0015 0.0010 0.0005 RLOAD = 250Ω TA = 25°C 3.8mA TO 21mA RANGE EXT VREF EXT RSET 0 10 20 30 40 50 60 LOOP SUPPLY VOLTAGE (V) 5 1000 750 OPERATING AREA 500 250 0 10 20 80 100 4 3 2 0 0 30 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REGOUT LOAD CURRENT (mA) VOLTAGE ACROSS 250Ω LOAD RESISTOR (µV) 1250 50 LOOP SUPPLY VOLTAGE (V) 09128-019 LOAD RESISTANCE (Ω) 1500 0 60 Figure 21. Loop Current Error vs. REGOUT Load Current TA = 25°C EXT VREF ILOOP = 24mA EXT RSET 1750 40 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C ILOOP = 20mA Figure 18. Full-Scale Error vs. Loop Supply Voltage 2000 20 1 09128-018 –0.0005 0 Figure 20. Compliance Voltage Headroom vs. Temperature 0.0030 0 –20 TEMPERATURE (°C) Figure 17. Gain Error vs. Loop Supply Voltage FULL-SCALE ERROR (% FSR) 4.60 09128-021 –0.0025 09128-017 –0.0020 RLOAD = 250Ω 3.2mA TO 24mA RANGE EXT VREF ILOOP = 24mA 4.65 Figure 19. Load Resistance Load Line vs. Loop Supply Voltage (Voltage Between LOOP− and REGIN) 8 6 4 2 0 –2 VLOOP = 24V EXT NMOS EXT VREF ILOOP = 4mA RLOAD = 250Ω TA = 25°C –4 –6 –8 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) Figure 22. Loop Current Noise, 0.1 Hz to 10 Hz Bandwidth Rev. 0 | Page 14 of 32 09128-022 GAIN ERROR (% FSR) 4.70 RLOAD = 250Ω TA = 25°C 3.8mA TO 21mA RANGE EXT VREF EXT RSET 09128-020 0.0015 1.0 0.244 VLOOP = 24V ILOOP = 4mA 1.33mV p-p EXT NMOS RLOAD = 500Ω 0.2mV rms INT VREF TA = 25°C 0.8 0.6 IODVDD CURRENT (µA) 0.240 0.4 0.2 0 –0.2 –0.4 0.236 0.234 0.232 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.226 0 0.5 1.0 09128-027 0 2.0 1.5 DIGITAL LOGIC VOLTAGE (V) Figure 23. Loop Current Noise, 500 Hz to 10 kHz Bandwidth (HART Bandwidth) Figure 26. IODVDD Current vs. Digital Logic Voltage, Increasing and Decreasing, IODVDD = 1.8 V 6 0.60 IODVDD = 3.3V TA = 25°C FALLING IODVDD CURRENT (µA) 5 4 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C CIN = OPEN CIRCUIT 3 2 RISING 0.55 DECREASING INCREASING 0.50 0.45 0 –40 –30 –20 –10 0 10 20 30 40 TIME (µs) 0.40 0 0.5 1.0 1.5 2.0 2.5 3.0 09128-028 1 09128-025 3.5 DIGITAL LOGIC VOLTAGE (V) Figure 24. Full-Scale Loop Current Step Figure 27. IODVDD Current vs. Digital Logic Voltage, Increasing and Decreasing, IODVDD = 3.3 V 6 1.3 FALLING IODVDD = 5V TA = 25°C 1.2 5 IODVDD CURRENT (µA) DECREASING 4 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C CIN = 22nF 3 2 1.1 1.0 INCREASING 0.9 0.8 RISING 1 –0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) 3.0 09128-026 0 –1.0 0.7 Figure 25. Full-Scale Loop Current Step, CIN = 22 nF 0.6 0 1 2 3 4 DIGITAL LOGIC VOLTAGE (V) 5 6 09128-029 VOLTAGE ACROSS 250Ω LOAD RESISTOR (V) INCREASING 0.228 –0.8 TIME (Seconds) VOLTAGE ACROSS 250Ω LOAD RESISTOR (V) DECREASING 0.238 0.230 –0.6 –1.0 IODVDD = 1.8V TA = 25°C 0.242 09128-023 VOLTAGE ACROSS 500Ω LOAD RESISTOR (mV) AD5421 Figure 28. IODVDD Current vs. Digital Logic Voltage, Increasing and Decreasing, IODVDD = 5 V Rev. 0 | Page 15 of 32 AD5421 1.84 –15 1.82 –20 1.81 –25 1.80 –30 1.79 –35 1.78 –40 1.77 –45 2 4 6 8 10 –15 3.25 –20 3.20 –25 –30 3.15 –35 3.10 3.00 12 REGOUT LOAD CURRENT (mA) –40 –45 –50 0 1 REFOUT1 VOLTAGE NOISE (µV) 260.5 260.0 259.5 1 0 –1 –2 10 20 30 40 50 –4 09128-031 0 60 LOOP SUPPLY VOLTAGE (V) 0 1 2 3 4 5 6 7 8 10 9 TIME (Seconds) Figure 30. Quiescent Current vs. Loop Supply Voltage Figure 33. REFOUT1 Voltage Noise, 0.1 Hz to 10 Hz Bandwidth REFOUT1 VOLTAGE (V) VLOOP = 24V EXT NMOS VIH = IODVDD VIL = COM TA = 25°C 263 262 261 260 3.0 1 2.5 0 2.0 –1 1.5 –2 1.0 –3 259 0.5 257 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 0 –4 VLOOP = 24V EXT NMOS TA = 25°C 258 09128-032 QUIESCENT CURRENT (µA) VLOOP = 24V EXT NMOS TA = 25°C –3 259.0 09128-034 261.0 2 0 1 –5 2 3 4 5 6 REFOUT1 LOAD CURRENT (mA) Figure 31. Quiescent Current vs. Temperature Figure 34. REFOUT1 Voltage vs. Load Current Rev. 0 | Page 16 of 32 7 REFOUT1 VOLTAGE CHANGE (mV) QUIESCENT CURRENT (µA) 261.5 264 5 3 262.0 265 4 4 TA = 25°C 262.5 266 3 Figure 32. DVDD Output Voltage vs. Load Current 263.0 258.5 2 DVDD LOAD CURRENT (mA) Figure 29. REGOUT Voltage vs. Load Current 263.5 –10 3.30 3.05 –50 0 –5 09128-035 1.76 3.35 09128-030 REGOUT VOLTAGE (V) 1.83 VLOOP = 24V EXT NMOS TA = 25°C DVDD OUTPUT VOLTAGE CHANGE (mV) 1.85 0 3.40 0.25 0 VLOOP = 24V –5 EXT NMOS TA = 25°C –10 09128-033 REGOUT LOAD CURRENT (mA) 0.10 0.15 0.20 DVDD OUTPUT VOLTAGE (V) 0.05 REGOUT VOLTAGE CHANGE (mV) 0 AD5421 2.5012 250 60 DEVICES SHOWN VLOOP = 24V EXT NMOS RLOAD = 250Ω ILOOP = 3.2mA 2.5010 200 ADC CODE (Decimal) REFOUT1 VOLTAGE (V) 2.5008 2.5006 2.5004 2.5002 2.5000 2.4998 150 100 50 –20 0 20 40 60 80 0 –40 09128-036 2.4994 –40 100 TEMPERATURE (°C) 250 MEAN TC = 1.5ppm/°C 40 60 80 100 VLOOP = 24V EXT NMOS TA = 25°C ADC CODE (Decimal) 200 20 15 10 150 100 09128-037 TEMPERATURE COEFFICIENT (ppm/°C) 0 0 0.5 1.0 1.5 2.0 VLOOP PIN INPUT VOLTAGE (V) Figure 36. REFOUT1 Temperature Coefficient Histogram (C Grade Device) Figure 38. On-Chip ADC Code vs. VLOOP Pin Input Voltage Rev. 0 | Page 17 of 32 2.5 09128-039 50 5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 POPULATION (%) 20 Figure 37. On-Chip ADC Code vs. Die Temperature 25 0 0 DIE TEMPERATURE (°C) Figure 35. REFOUT1 Voltage vs. Temperature, 60 Devices Shown (C Grade Device) 30 –20 09128-038 2.4996 AD5421 TERMINOLOGY Total Unadjusted Error Total unadjusted error (TUE) is a measure of the total output error. TUE consists of INL error, offset error, gain error, and output drift over temperature, in the case of maximum TUE. TUE is expressed in % FSR. Relative Accuracy or Integral Nonlinearity (INL) Error Relative accuracy, or integral nonlinearity (INL) error, is a measure of the maximum deviation in the output current from a straight line passing through the endpoints of the transfer function. INL error is expressed in % FSR. Differential Nonlinearity (DNL) Error Differential nonlinearity (DNL) error is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Offset Error Offset error is a measure of the output error when zero code is loaded to the DAC register and is expressed in % FSR. Offset Error Temperature Coefficient (TC) Offset error TC is a measure of the change in offset error with changes in temperature and is expressed in ppm FSR/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer function from the ideal and is expressed in % FSR. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature and is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register and is expressed in % FSR. Loop Compliance Voltage Headroom Loop compliance voltage headroom is the minimum voltage between the LOOP− and REGIN pins for which the output current is equal to the programmed value. Output Temperature Coefficient (TC) Output TC is a measure of the change in the output current at 12 mA with changes in temperature and is expressed in ppm FSR/°C. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to −40°C to +105°C and back to +25°C. The hysteresis is specified for the first and second temperature cycles and is expressed in mV. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The voltage reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output voltage over a given temperature range. Voltage reference TC is expressed in ppm/°C as follows: ⎛ VREF_MAX − VREF_MIN ⎞ ⎟ × 10 6 TC = ⎜ ⎜V ⎟ × Temp_Range REF_NOM ⎝ ⎠ where: VREF_MAX is the maximum reference output voltage measured over the total temperature range. VREF_MIN is the minimum reference output voltage measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5 V. Temp_Range is the specified temperature range (−40°C to +105°C). Full-Scale Error Temperature Coefficient (TC) Full-scale error TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C. Rev. 0 | Page 18 of 32 AD5421 THEORY OF OPERATION In the case of data readback, if the AD5421 is addressed with a 32-bit frame, it generates the 8-bit frame check sequence and appends it to the end of the 24-bit data stream to create a 32-bit data stream. UPDATE ON SYNC HIGH SYNC SCLK MSB D23 FAULT ALERTS The AD5421 provides a number of fault alert features. All faults are signaled to the controller via the FAULT pin and the fault register. In the case of a loss of communication between the AD5421 and the microcontroller (SPI fault), the AD5421 programs the loop current to an alarm value. If the controller detects that the FAULT pin is set high, it should then read the fault register to determine the cause of the fault. LSB D0 24-BIT DATA SDIN 24-BIT DATA TRANSFER—NO ERROR CHECKING UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC SCLK MSB D31 SPI Fault The SPI fault is asserted if there is no valid communication to any register of the AD5421 for more than a user-defined period. The user can program the time period using the SPI watchdog timeout bits of the control register. The SPI fault bit of the fault register indicates the fault on the SPI bus. Because this fault is caused by a loss of communication between the controller and the AD5421, the loop current is also forced to the alarm value. SDIN LSB D8 24-BIT DATA D7 D0 8-BIT FCS FAULT PIN GOES HIGH IF ERROR CHECK FAILS FAULT 32-BIT DATA TRANSFER WITH ERROR CHECKING 09128-049 The AD5421 is an integrated device designed for use in looppowered, 4 mA to 20 mA smart transmitter applications. In a single chip, the AD5421 provides a 16-bit DAC and current amplifier for digital control of the loop current, a voltage regulator to power the entire transmitter, a voltage reference, fault alert functions, a flexible SPI-compatible serial interface, gain and offset adjust registers, as well as other features and functions. The features of the AD5421 are described in the following sections. Figure 39. PEC Timing Current Loop Fault Packet Error Checking The current loop (ILOOP) fault is asserted when the actual loop current is not within ±0.01% FSR of the programmed loop current. If the measured loop current is less than the programmed loop current, the ILOOP Under bit of the fault register is set. If the measured loop current is greater than the programmed loop current, the ILOOP Over bit of the fault register is set. The FAULT pin is set to logic high in either case. To verify that data has been received correctly in noisy environments, the AD5421 offers the option of error checking based on an 8-bit cyclic redundancy check (CRC). Packet error checking (PEC) is enabled by writing to the AD5421 with a 32-bit serial frame, where the least significant eight bits are the frame check sequence (FCS). The device controlling the AD5421 should generate the 8-bit FCS using the following polynomial: An ILOOP Over condition occurs when the value of the load current sourced from the AD5421 (via REGOUT, REFOUT1, REFOUT2, or DVDD) is greater than the loop current that is programmed to flow in the loop. An ILOOP Under condition occurs when there is insufficient compliance voltage to support the programmed loop current, caused by excessive load resistance or low loop supply voltage. The direction of the alarm current (downscale or upscale) is selected via the ALARM_CURRENT_DIRECTION pin. Connecting this pin to DVDD selects an upscale alarm current (22.8 mA/24 mA); connecting this pin to COM selects a downscale alarm current (3.2 mA). C(x) = x 8 + x 2 + x + 1 Overtemperature Fault The 8-bit FCS is appended to the end of the data-word, and 32 data bits are sent to the AD5421 before SYNC is taken high. If the check is valid, the data is accepted. If the check fails, the FAULT pin is asserted and the PEC bit of the fault register is set. After the fault register is read, the PEC bit is reset low and the FAULT pin returns low. There are two overtemperature alert bits in the fault register: Temp 100°C and Temp 140°C. If the die temperature of the AD5421 exceeds either 100°C or 140°C, the appropriate bit is set. If the Temp 140°C bit is set in the fault register, the FAULT pin is set to logic high. Rev. 0 | Page 19 of 32 AD5421 Loop Voltage Fault LOOP CURRENT RANGE SELECTION There are two loop voltage alert bits in the fault register: VLOOP 12V and VLOOP 6V. If the voltage between the VLOOP and COM pins falls below 0.6 V (corresponding to a 12 V loop supply value), the VLOOP 12V bit is set; this bit is cleared when the voltage returns above 0.7 V. Similarly, if the voltage between the VLOOP and COM pins falls below 0.3 V (corresponding to a 6 V loop supply value), the VLOOP 6V bit is set; this bit is cleared when the voltage returns above 0.4 V. If the VLOOP 6V bit is set in the fault register, the FAULT pin is set to logic high. To select the loop current range, connect the RANGE0 and RANGE1 pins to the COM and DVDD pins, as shown in Table 9. Figure 40 illustrates how a resistor divider enables the monitoring of the loop supply with the VLOOP input. The recommended resistor divider consists of a 1 MΩ and a 19 MΩ resistor that provide a 20:1 ratio, allowing the 2.5 V input range of the VLOOP pin to monitor loop supplies up to 50 V. With a 20:1 divider ratio, the preset VLOOP 6V and VLOOP 12V alert bits of the fault register generate loop supply faults according to their stated values. If another divider ratio is used, the fault bits generate faults at values that are not equal to 6 V and 12 V. Table 9. Selecting the Loop Current Range RANGE1 Pin COM COM DVDD DVDD RANGE0 Pin COM DVDD COM DVDD Loop Current Range 4 mA to 20 mA 3.8 mA to 21 mA 3.2 mA to 24 mA 3.8 mA to 21 mA CONNECTION TO LOOP POWER SUPPLY The AD5421 is powered from the 4 mA to 20 mA current loop. Typically, the power supply is located far from the transmitter device and has a value of 24 V. The AD5421 can be connected directly to the loop power supply and can tolerate a voltage up to a maximum of 52 V (see Figure 41). REGIN AD5421 REGIN 1MΩ DRIVE VLOOP RL LOOP– RL COM 09128-050 19MΩ VLOOP LOOP– Figure 41. Direct Connection of the AD5421 to Loop Power Supply 09128-048 COM Figure 40. Resistor Divider Connection at VLOOP Pin EXTERNAL CURRENT SETTING RESISTOR The 24 kΩ resistor RSET, shown in Figure 1, converts the DAC output voltage to a current, which is then mirrored with a gain of 221 to the LOOP− pin. The stability of the loop current over temperature is dependent on the temperature coefficient of RSET. Table 1 and Table 2 outline the performance specifications of the AD5421 with both the internal RSET resistor and an external, 24 kΩ RSET resistor. Using the internal RSET resistor, a total unadjusted error of better than 0.126% FSR can be expected. Using an external resistor gives improved performance of 0.048% FSR. This specification assumes an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. For more information, see the Determining the Expected Total Error section. Figure 41 shows how the AD5421 is connected directly to the loop power supply. An alternative power connection is shown in Figure 42, which shows a depletion mode N-channel MOSFET connected between the AD5421 and the loop power supply. The use of this device keeps the voltage drop across the AD5421 at approximately 12 V, limiting the worst-case on-chip power dissipation to 288 mW (12 V × 24 mA = 288 mW). If the AD5421 is connected directly to the loop supply as shown in Figure 41, the potential worst-case on-chip power dissipation for a 24 V loop power supply is 576 mW (24 V × 24 mA = 576 mW). The power dissipation changes in proportion to the loop power supply voltage. T1 DN2540 BSP129 200kΩ REGIN AD5421 DRIVE VLOOP RL LOOP– COM 09128-051 AD5421 VLOOP Figure 42. MOSFET Connecting the AD5421 to Loop Power Supply Rev. 0 | Page 20 of 32 AD5421 The AD5421 contains an on-chip ADC used to measure and feed back to the fault register either the temperature of the die or the voltage between the VLOOP and COM pins. The select ADC input bit (Bit D8) of the control register selects the parameter to be converted. A conversion is initiated with command byte 00001000 (necessary only if auto fault readback is disabled). This command byte powers on the ADC and performs the conversion. A read of the fault register returns the conversion result. If auto readback of the fault register is required, the ADC must first be powered up by setting the on-chip ADC bit (Bit D7) of the control register. Taking five time constants as the required time to reach the final value, CSLEW can be determined for a desired response time, t, as follows: C SLEW = where: t is the desired time for the output current to reach its final value. RDAC is the resistance of the DAC core, either 15.22 kΩ or 16.11 kΩ, depending on the selected loop current range. For a response time of 5 ms, VOLTAGE REGULATOR Table 10. Setting the Voltage Regulator Output REG_SEL2 COM COM COM COM DVDD DVDD DVDD REG_SEL1 COM COM DVDD DVDD COM COM DVDD REG_SEL0 COM DVDD COM DVDD COM DVDD COM Regulated Output Voltage (V) 1.8 2.5 3.0 3.3 5.0 9.0 12.0 LOOP CURRENT SLEW RATE CONTROL The rate of change of the loop current can be controlled by connecting an external capacitor between the CIN pin and COM. This reduces the rate of change of the loop current. The output resistance of the DAC (RDAC) together with the CSLEW capacitor generate a time constant that determines the response of the loop current (see Figure 43). RDAC V-TO-I CIRCUITRY C SLEW = 10 ms 5 × 15,220 ≈ 133 nF The responses for both of these configurations are shown in Figure 44. 6 CSLEW = 68nF 5 4 CSLEW = 267nF CSLEW = 133nF 3 2 1 2 6 10 14 18 22 Figure 44. 4 mA to 20 mA Step with Slew Rate Control The CIN pin can also be used as a coupling input for HART FSK signaling. The HART signal must be ac-coupled to the CIN input. The capacitor through which the HART signal is coupled must be considered in the preceding calculations, where the total capacitance is CSLEW + CHART. For more information, see the HART Communications section. 09128-052 Figure 43. Slew Capacitor Circuit The resistance of the DAC is typically 15.22 kΩ for the 4 mA to 20 mA and 3.8 mA to 21 mA loop current ranges. The DAC resistance changes to 16.11 kΩ when the 3.2 mA to 24 mA loop current range is selected. τ = RDAC × CSLEW ≈ 68 nF TIME (ms) LOOP– The time constant of the circuit is expressed as 5 ms 5 × 15,220 For a response time of 10 ms, 0 –2 CIN CSLEW C SLEW = VOLTAGE ACROSS 250Ω LOAD RESISTOR (V) The on-chip voltage regulator provides a regulated voltage output to supply the AD5421 and the remainder of the transmitter circuitry. The output voltage range is from 1.8 V to 12 V and is selected by the states of three digital input pins (see Table 10). The regulator output is accessed at the REGOUT pin. t 5 × R DAC 09128-053 ON-CHIP ADC POWER-ON DEFAULT The AD5421 powers on with all registers loaded with their default values and with the loop current in the alarm state set to 3.2 mA or 22.8 mA/24 mA (depending on the state of the ALARM_ CURRENT_DIRECTION pin and the selected range). The AD5421 remains in this state until it is programmed with new values. The SPI watchdog timer is enabled by default with a timeout period of 1 sec. If there is no communication with the AD5421 within 1 sec of power-on, the FAULT pin is set. Rev. 0 | Page 21 of 32 AD5421 HART COMMUNICATIONS Output Noise During Silence and Analog Rate of Change The AD5421 can be interfaced to a Highway Addressable Remote Transducer (HART) modem to enable HART digital communications over the 2-wire loop connection. Figure 45 shows how the modem frequency shift keying (FSK) output is connected to the AD5421. The AD5421 has a direct influence on two important specifications relating to the HART communications protocol: output noise during silence and analog rate of change. Figure 23 shows the measurement of the AD5421 output noise in the HART extended bandwidth; the noise measurement is 0.2 mV rms, within the required 2.2 mV rms value. AD5421 DRIVE VLOOP RL LOOP– CIN CSLEW COM CHART HART MODEM 09128-054 HART_OUT HART_IN Figure 45. Connecting a HART Modem to the AD5421 To achieve a 1 mA p-p FSK current signal on the loop, the voltage at the CIN pin must be 111 mV p-p. Assuming a 500 mV p-p output from the HART modem, this means that the signal must be attenuated by a factor of 4.5. The following equation can be used to calculate the values of the CHART and CSLEW capacitors. 4.5 = C HART + C SLEW C HART From this equation, the ratio of CHART to CSLEW is 1 to 3.5. This ratio of the capacitor values sets the amplitude of the HART FSK signal on the loop. The absolute values of the capacitors set the response time of the loop current, as well as the bandwidth presented to the HART signal connected at the CIN pin. The bandwidth must pass frequencies from 500 Hz to 10 kHz. The two capacitors and the internal impedance, RDAC, form a highpass filter. The 3 dB frequency of this high-pass filter should be less than 500 Hz and can be calculated as follows: f 3dB = 2 × π × R DAC 1 × (C HART + C SLEW ) To achieve a 500 Hz high-pass 3 dB frequency cutoff, the combined values of CHART and CSLEW should be 21 nF. To ensure the correct HART signal amplitude on the current loop, the final values for the capacitors are CHART = 4.7 nF and CSLEW = 16.3 nF. The output of the AD5421 naturally slews at approximately 880 mA/ms, a rate that is far too great to comply with the HART specifications. To reduce the slew rate, a capacitor can be connected from the CIN pin to COM, as described in the Loop Current Slew Rate Control section. To reduce the slew rate enough so that the HART specification is met, a capacitor value in the region of 4.7 μF is required, resulting in a full-scale transition time of 500 ms. Many applications will regard this time as too slow, in which case the slew rate will need to be digitally controlled by writing a sequence of codes to the DAC register so that the output response follows the desired curve. Figure 46 shows a digitally controlled full-scale step and the resulting filter output. In Figure 46, it can be seen that the peak amplitude of the filter output signal is less than the required 150 mV, and the transition time is approximately 30 ms. 12 150 10 100 8 50 6 0 4 –50 2 –100 0 –50 –150 –30 –10 10 TIME (ms) 30 50 OUTPUT OF HART DIGITAL FILTER (mV) HCF_TOOL-31 100nF 09128-060 REGIN VOLTAGE ACROSS 500Ω LOAD RESISTOR (V) 200kΩ To meet the analog rate of change specification, the rate of change of the 4 mA to 20 mA current must be slow enough so that it does not interfere with the HART digital signaling. This is determined by forcing a full-scale loop current change through a 500 Ω load resistor and applying the resulting voltage signal to the HART digital filter (HCF_TOOL-31). The peak amplitude of the signal at the filter output must be less than 150 mV. To achieve this, the rate of change of the loop current must be restricted to less than approximately 1.3 mA/ms. Figure 46. Digitally Controlled Full-Scale Step and Resulting HART Digital Filter Output Signal Rev. 0 | Page 22 of 32 AD5421 Figure 47 shows the circuit diagram for this measurement. The 47 nF and 168 nF capacitor values for CHART and CSLEW provide adequate filtering of the digital steps, ensuring that they do not cause interference. REGIN AD5421 VLOOP 100nF RL LOOP– 168nF COM 47nF FROM HART MODEM 09128-061 CIN Figure 47. Circuit Diagram for Figure 46 Rev. 0 | Page 23 of 32 AD5421 SERIAL INTERFACE The address/command byte decoding is described in Table 11. The AD5421 is controlled by a versatile, 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with the SPI, QSPI™, MICROWIRE®, and DSP standards. Figure 2 shows the timing diagram. The interface operates with either a continuous or noncontinuous gated burst clock. Table 11. Address/Command Byte Functions Address/Command Byte 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 10000001 10000010 10000011 10000100 10000101 The write sequence begins with a falling edge of the SYNC signal; data is clocked in on the SDIN data line on the falling edge of SCLK. On the rising edge of SYNC, the 24 bits of data are latched; the data is transferred to the addressed register and the programmed function is executed (either a change in DAC output or mode of operation). If packet error checking on the SPI interface is required using cyclic redundancy codes, an additional eight bits must be written to the AD5421, creating a 32-bit serial interface. In this case, 32 bits are written to the AD5421 before SYNC is brought high. INPUT SHIFT REGISTER The input shift register is 24 bits wide (32 bits wide if CRC error checking of the data is required). Data is loaded into the device MSB first as a 24-/32-bit word under the control of a serial clock input, SCLK. The input shift register consists of an 8-bit address/ command byte, a 16-bit data-word, and an optional 8-bit CRC, as shown in Table 12 and Table 13. Function Write to DAC register Write to control register Write to offset adjust register Write to gain adjust register Load DAC Force alarm current Reset Initiate VLOOP/temp measurement No operation Read DAC register Read control register Read offset adjust register Read gain adjust register Read fault register REGISTER READBACK To read back a register, Bit D11 of the control register must be set to Logic 1 to disable the automatic readback of the fault register. Table 12. Input Shift Register MSB D23 D22 D21 D20 D19 D18 Address/command byte D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 Data-word D6 D5 D4 D3 D2 D1 LSB D0 Table 13. Input Shift Register with CRC MSB LSB D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address/command byte Data-word CRC Rev. 0 | Page 24 of 32 AD5421 For the 3.8 mA to 21 mA output range, the loop current can be expressed as follows: DAC REGISTER The DAC register is a read/write register and is addressed as described in Table 11. The data programmed to the DAC register determines the loop current, as shown in the Ideal Output Transfer Function section and in Table 15. ⎛ 17.2 mA ⎞ I LOOP = ⎜⎜ 16 ⎟⎟ × D + 3.8 mA ⎝ 2 ⎠ For the 3.2 mA to 24 mA output range, the loop current can be expressed as follows: Ideal Output Transfer Function The transfer function describing the relationship between the data programmed to the DAC register and the loop current is expressed by the following three equations. For the 4 mA to 20 mA output range, the loop current can be expressed as follows: ⎛ 20.8 mA ⎞ I LOOP = ⎜⎜ ⎟⎟ × D + 3.2 mA 16 ⎠ ⎝ 2 where D is the decimal value of the DAC register. ⎛ 16 mA ⎞ I LOOP = ⎜⎜ 16 ⎟⎟ × D + 4 mA ⎝ 2 ⎠ Table 14. DAC Register Bit Map MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 16-bit data D6 D5 D4 D3 D2 D1 Table 15. Relationship of DAC Register Code to Ideal Loop Current (Gain = 65,536; Offset = 0) DAC Register Code 0x0000 0x0001 … 0x7FFF 0x8000 … 0xFFFE 0xFFFF 4 mA to 20 mA Range 4 4.00024 … 11.9997 12 … 19.9995 19.9997 Ideal Loop Current (mA) 3.8 mA to 21 mA Range 3.8 3.80026 … 12.39974 12.4 … 20.99947 20.99974 Rev. 0 | Page 25 of 32 3.2 mA to 24 mA Range 3.2 3.2003 … 13.5997 13.6 … 23.9994 23.9997 LSB D0 AD5421 CONTROL REGISTER The control register is a read/write register and is addressed as described in Table 11. The data programmed to the control register determines the mode of operation of the AD5421. Table 16. Control Register Bit Map MSB D15 D14 D13 SPI watchdog timeout T0 T1 T2 D12 SPI watchdog timer D11 Auto fault readback D10 Alarm on SPI fault D9 Set min loop current D8 Select ADC input D7 On-chip ADC D6 Power down internal reference D5 VLOOP fault alert D4 D3 D2 D1 Reserved LSB D0 Table 17. Control Register Bit Descriptions Control Bits SPI watchdog timeout SPI watchdog timer Auto fault readback Alarm on SPI fault Set min loop current Select ADC input On-chip ADC Power down internal reference VLOOP fault alert Description The T0, T1, and T2 bits allow the user to program the watchdog timeout period. The watchdog timer is reset when a valid write to any AD5421 register occurs or when a NOP command is written. T0 T1 T2 Timeout Period 0 0 0 50 ms 0 0 1 100 ms 0 1 0 500 ms 0 1 1 1 sec (default) 1 0 0 2 sec 1 0 1 3 sec 1 1 0 4 sec 1 1 1 5 sec 0 = SPI watchdog timer is enabled (default). 1 = SPI watchdog timer is disabled. This bit specifies whether the fault register contents are automatically clocked out on the SDO pin on each write operation. (The fault register can always be addressed for readback.) 0 = fault register contents are clocked out on the SDO pin (default). 1 = fault register contents are not clocked out on the SDO pin. This bit specifies whether the loop current is forced to the alarm value when an SPI fault is detected (that is, the watchdog timer times out). When an SPI fault is detected, the SPI fault bit of the fault register and the FAULT pin are always set. 0 = loop current is forced to the alarm value when an SPI fault is detected (default). 1 = loop current is not forced to the alarm value when an SPI fault is detected. 0 = normal operation (default). 1 = loop current is set to its minimum value so that the total current flowing in the loop consists only of the operating current of the AD5421 and its associated circuitry. 0 = on-chip ADC measures the voltage between the VLOOP and COM pins (default). 1 = on-chip ADC measures the temperature of the AD5421 die. 0 = on-chip ADC is disabled (default). 1 = on-chip ADC is enabled. 0 = internal voltage reference is powered up (default). 1 = internal voltage reference is powered down and an external voltage reference source is required. This bit specifies whether the FAULT pin is set when the voltage between the VLOOP and COM pins falls to approximately 0.3 V. (The VLOOP 6V bit of the fault register is always set.) 0 = FAULT pin is not set when the VLOOP − COM voltage falls to approximately 0.3 V. 1 = FAULT pin is set when the VLOOP − COM voltage falls to approximately 0.3 V. Rev. 0 | Page 26 of 32 AD5421 FAULT REGISTER The read-only fault register is addressed as described in Table 11. The bits in the fault register indicate a range of possible fault conditions. Table 18. Fault Register Bit Map MSB D15 SPI D14 PEC D13 ILOOP Over D12 ILOOP Under D11 Temp 140°C D10 Temp 100°C D9 VLOOP 6V D8 VLOOP 12V D7 D6 D5 D4 D3 D2 VLOOP/temperature value D1 LSB D0 Table 19. Fault Register Bit Descriptions Fault Alert SPI FAULT Pin Set Yes Yes PEC (packet error check) ILOOP Over ILOOP Under Temp 140°C Yes Yes Yes Temp 100°C No VLOOP 6V Yes VLOOP 12V No VLOOP/temperature value N/A Description This bit is set high to indicate the loss of the SPI interface signaling. This fault occurs if there is no valid communication to the AD5421 over the SPI interface for more than the user-defined timeout period. The occurrence of this fault also forces the loop current to the alarm value if Bit D10 of the control register is at Logic 0. The alarm current direction is determined by the state of the ALARM_CURRENT_DIRECTION pin. This bit is set high when an error in the SPI communication is detected using cyclic redundancy check (CRC) error detection. See the Packet Error Checking section for more information. This bit is set high when the actual loop current is greater than the programmed loop current. This bit is set high when the actual loop current is less than the programmed loop current. This bit is set high to indicate an overtemperature fault. This bit is set if the die temperature of the AD5421 exceeds approximately 140°C. This bit is cleared when the temperature returns below approximately 125°C. This bit is set high to indicate an increasing temperature of the AD5421. This bit is set if the die temperature of the AD5421 exceeds approximately 100°C. This bit is cleared when the temperature returns below approximately 85°C. This bit is set high when the voltage between the VLOOP and COM pins falls below approximately 0.3 V (representing a 6 V loop supply voltage with 20:1 resistor divider connected at VLOOP). This bit is cleared when the voltage returns above approximately 0.4 V. This bit is set high when the voltage between the VLOOP and COM pins falls below approximately 0.6 V (representing a 12 V loop supply voltage with 20:1 resistor divider connected at VLOOP). This bit is cleared when the voltage returns above approximately 0.7 V. These eight bits represent either the voltage between the VLOOP and COM pins or the AD5421 die temperature, depending on the setting of Bit D8 of the control register (see the On-Chip ADC Transfer Function Equations section). 8-Bit Value VLOOP − COM Voltage (V) Die Temperature (°C) 00000000 0 +300 … … … 11111111 2.49 −55 On-Chip ADC Transfer Function Equations The transfer function equation for the die temperature is as follows: The transfer function equation for the measurement of the voltage between the VLOOP and COM pins is as follows: Die Temperature = 125 − (1.771 × (D − 128)) VLOOP − COM = (2.5/256) × D where D is the 8-bit digital code returned by the on-chip ADC. where D is the 8-bit digital code returned by the on-chip ADC. Rev. 0 | Page 27 of 32 AD5421 OFFSET ADJUST REGISTER The offset adjust register is a read/write register and is addressed as described in Table 11. Table 20. Offset Adjust Register Bit Map MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 16-bit offset adjust data D5 D4 D3 D2 D1 LSB D0 D3 D2 D1 LSB D0 Table 21. Offset Adjust Register Adjustment Range Offset Adjust Register Data 65535 65534 … 32769 32768 (default) 32767 … 1 0 Digital Offset Adjustment (LSBs) +32767 +32766 … +1 0 −1 … −32767 −32768 GAIN ADJUST REGISTER The gain adjust register is a read/write register and is addressed as described in Table 11. Table 22. Gain Adjust Register Bit Map MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 16-bit gain adjust data D5 D4 Table 23. Gain Adjust Register Adjustment Range Gain Adjust Register Data 65535 (default) 65534 … 32769 32768 32767 … 1 0 Digital Gain Adjustment at Full-Scale Output (LSBs) 0 −1 … −32767 −32768 −32769 … −65534 −65535 Rev. 0 | Page 28 of 32 AD5421 Transfer Function Equations with Offset and Gain Adjust Values For the 3.2 mA to 24 mA output range, the loop current can be expressed as follows: When the offset adjust and gain adjust register values are taken into account, the transfer equations can be expressed as follows. I LOOP For the 4 mA to 20 mA output range, the loop current can be expressed as follows: I LOOP ⎤ ⎡ ⎛ 16 mA ⎞ ⎥ ⎢ ⎜⎜ 16 ⎟⎟ × Gain 2 ⎠ ⎥ × = ⎢⎝ D ⎥ ⎢ 216 ⎥ ⎢ ⎥⎦ ⎣⎢ ⎛ ⎡⎛ 20.8 mA ⎞ ⎤⎞ + ⎜ 3.2 mA + ⎢⎜⎜ ⎟⎟ × (Offset − 32,768 )⎥ ⎟ 16 ⎜ ⎟ ⎠ ⎣⎝ 2 ⎦⎠ ⎝ where: D is the decimal value of the DAC register. Gain is the decimal value of the gain adjust register. Offset is the decimal value of the offset adjust register. ⎛ ⎡⎛ 16 mA ⎞ ⎤⎞ + ⎜ 4 mA + ⎢⎜⎜ 16 ⎟⎟ × (Offset − 32,768 )⎥ ⎟ ⎜ ⎟ ⎠ ⎣⎝ 2 ⎦⎠ ⎝ For the 3.8 mA to 21 mA output range, the loop current can be expressed as follows: I LOOP ⎤ ⎡ ⎛ 20.8 mA ⎞ ⎟⎟ × Gain ⎥ ⎢ ⎜⎜ 16 2 ⎠ ⎥ × = ⎢⎝ D ⎥ ⎢ 216 ⎥ ⎢ ⎥⎦ ⎣⎢ Note that the offset adjust register cannot adjust the zero-scale output value downward. ⎤ ⎡ ⎛ 17.2 mA ⎞ ⎟⎟ × Gain ⎥ ⎢ ⎜⎜ 16 2 ⎠ ⎥ × = ⎢⎝ D ⎥ ⎢ 216 ⎥ ⎢ ⎥⎦ ⎣⎢ ⎛ ⎡⎛ 17.2 mA ⎞ ⎤⎞ + ⎜ 3.8 mA + ⎢⎜⎜ ⎟⎟ × (Offset − 32,768 )⎥ ⎟ 16 ⎜ ⎟ ⎠ ⎣⎝ 2 ⎦⎠ ⎝ Rev. 0 | Page 29 of 32 AD5421 APPLICATIONS INFORMATION Figure 48 shows a typical connection diagram for the AD5421 configured in a HART capable smart transmitter. To reduce power dissipation on the chip, a depletion mode MOSFET (T1), such as a DN2540 or BSP129, can be connected between the loop voltage and the AD5421, as shown in Figure 48. DETERMINING THE EXPECTED TOTAL ERROR The AD5421 can be set up in a number of different configurations, each of which achieves different levels of accuracy, as described in Table 1 and Table 2. With the internal voltage reference and internal RSET enabled, a maximum total error of 0.157% of full-scale range can be expected for the C grade device over the temperature range of −40°C to +105°C. If a low loop voltage is used, T1 does not need to be inserted, and the loop voltage can connect directly to REGIN (see Figure 41). In Figure 48, all interface signal lines are connected to the microcontroller. To reduce the number of interface signal lines, the LDAC signal can be connected to COM, and the SDO and FAULT lines can be left unconnected. However, this configuration disables the use of the fault alert features. Other configurations specify an external voltage reference, an external RSET resistor, or both an external voltage reference and external RSET resistor. In these configurations, the specifications assume that the external voltage reference and external RSET resistor are ideal. Therefore, the errors associated with these components must be added to the data sheet specifications to determine the overall performance. The performance depends on the specifications of these components. Under normal operating conditions, the voltage between COM and LOOP− does not exceed 1.5 V, and the voltage at LOOP− is negative with respect to COM. If it is possible that the voltage at LOOP− may be forced positive with respect to COM, or if the voltage difference between LOOP− and COM may be forced in excess of 5 V, a 4.7 V low leakage Zener diode should be placed between COM and the LOOP− pin, as shown in Figure 48, to protect the AD5421 from potential damage. OPTIONAL MOSFET DN2540 BSP129 2.5V 2µF 1µF T1 200kΩ 0.1µF 0.1µF IODVDD DVDD REGOUT 100nF REGIN VLOOP RANGE0 VLOOP REFOUT1 REFIN REG_SEL2 REFOUT2 0.1µF VZ = 4.7V R1 COM 0.1µF RL 1MΩ REXT1 REG_SEL1 MCU 19MΩ LOOP– AD5421 REG_SEL0 REXT2 OPTIONAL RESISTOR CIN COM SETS REGULATOR VOLTAGE 47nF 168nF VCC HART MODEM TxD RxD HART_OUT RTS CD HART_IN GND Figure 48. AD5421 Application Diagram for HART Capable Smart Transmitter Rev. 0 | Page 30 of 32 09128-055 24-BIT Σ-Δ ADC DRIVE ALARM_CURRENT_DIRECTION RINT/REXT SYNC SCLK SDIN SDO FAULT LDAC ADuC7060 SENSOR RANGE1 AD5421 To determine the absolute worst-case overall error, the reference and RSET errors can be directly summed with the specified AD5421 maximum error. For example, when using an external reference and external RSET resistor, the maximum AD5421 error is 0.048% of full-scale range. Assuming that the absolute errors for the voltage reference and RSET resistor are, respectively, 0.04% and 0.05% with temperature coefficients of 3 ppm/°C and 2 ppm/°C, respectively, the overall worst-case error is as follows: Worst-Case Error = AD5421 Error + VREF Absolute Error + VREF TC + RSET Absolute Error + RSET TC Excessive junction temperature can occur if the AD5421 experiences elevated voltages across its terminals while regulating the loop current at a high value. The resulting junction temperature depends on the ambient temperature. Table 24 provides the bounds of operation at maximum ambient temperature and maximum supply voltage. This information is displayed graphically in Figure 49 and Figure 50. These figures assume that the exposed paddle is connected to a copper plane of approximately 6 cm2. 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 A further improvement can be gained by performing a two-point calibration at zero scale and full scale, thus reducing the absolute errors of the voltage reference and RSET resistor to a combined error of 1 LSB or 0.0015% FSR. After performing this calibration, the total maximum error becomes 45 65 85 105 AMBIENT TEMPERATURE (°C) 09128-056 This is the absolute worst-case value when the AD5421 operates over the temperature range of −40°C to +105°C. An error of this value is very unlikely to occur because the temperature coefficients of the individual components do not exhibit the same drift polarity, and, therefore, an element of cancelation occurs. For this reason, the TC values should be added in a root of squares fashion. POWER DISSIPATION (W) 4.0 Worst-Case Error = 0.048% + 0.04% + [(3/106) × 100 × 145]% + 0.05% + [(2/106) × 100 × 145]% = 0.21% FSR Figure 49. Maximum Power Dissipation vs. Ambient Temperature 60 50 To reduce this error value further, a voltage reference and RSET resistor with lower TC specifications must be chosen. THERMAL AND SUPPLY CONSIDERATIONS The AD5421 is designed to operate at a maximum junction temperature of 125°C. To ensure reliable and specified operation over the lifetime of the product, it is important that the device not be operated under conditions that cause the junction temperature to exceed this value. 40 30 20 10 0 25 45 65 85 105 AMBIENT TEMPERATURE (°C) 09128-057 0.048% + 0.0015% + (0.0435%) 2 + (0.029%) 2 = 0.102% FSR SUPPLY VOLTAGE (V) Total Error = Figure 50. Maximum Supply Voltage vs. Ambient Temperature Table 24. Thermal and Supply Considerations (External MOSFET Not Connected) Parameter Maximum Power Dissipation Description Maximum permitted power dissipation when operating at an ambient temperature of 105°C 28-Lead TSSOP Package Maximum Ambient Temperature Maximum permitted ambient temperature when operating from a supply of 52 V while regulating a loop current of 22.8 mA TJ MAX − (PD × θ JA ) = Maximum Supply Voltage Maximum permitted supply voltage when operating at an ambient temperature of 105°C while regulating a loop current of 22.8 mA Rev. 0 | Page 31 of 32 TJ MAX − TA θ JA = 125 − 105 32 = 625 mW 125 − ((52 × 0.0228) × 32) = 87 o C TJ MAX − TA I LOOP × θ JA = 125 − 105 0.0228 × 32 = 27 V AD5421 OUTLINE DIMENSIONS 9.80 9.70 9.60 5.55 5.50 5.45 15 28 4.50 4.40 4.30 3.05 3.00 2.95 EXPOSED PAD (Pins Up) 6.40 BSC 1 14 PIN 1 INDICATOR BOTTOM VIEW 1.05 1.00 0.80 1.20 MAX SEATING PLANE 0.30 0.19 0.20 0.09 0.25 8° 0.15 MAX 0° 0.05 MIN COPLANARITY 0.10 0.65 BSC 0.75 0.60 0.45 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 05-08-2006-A TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-153-AET Figure 51. 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-28-2) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5421BREZ-REEL AD5421BREZ-REEL7 AD5421CREZ-RL AD5421CREZ-RL7 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09128-0-2/11(0) Rev. 0 | Page 32 of 32 Package Option RE-28-2 RE-28-2 RE-28-2 RE-28-2