Single-Channel, 12-/16-Bit, Serial Input, 4 mA to 20 mA, Current Source DAC, HART Connectivity AD5410/AD5420 Data Sheet FEATURES GENERAL DESCRIPTION 12-/16-bit resolution and monotonicity Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA ±0.01% FSR typical total unadjusted error (TUE) ±3 ppm/°C typical output drift Flexible serial digital interface On-chip output fault detection On-chip reference (10 ppm/°C maximum) Feedback/monitoring of output current Asynchronous clear function Power supply (AVDD) range 10.8 V to 40 V; AD5410AREZ/AD5420AREZ 10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ Output loop compliance to AVDD − 2.5 V Temperature range: −40°C to +85°C 24-lead TSSOP and 40-lead LFCSP packages The AD5410/AD5420 are low cost, precision, fully integrated 12-/16-bit converters offering a programmable current source output designed to meet the requirements of industrial process control applications. The output current range is programmable at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of 0 mA to 24 mA. The output is open-circuit protected. The device operates with a power supply (AVDD) range from 10.8 V to 60 V. Output loop compliance is 0 V to AVDD − 2.5 V. APPLICATIONS The total unadjusted error is typically ±0.01% FSR. Process control Actuator control PLC HART network connectivity COMPANION PRODUCTS The flexible serial interface is SPI, MICROWIRE™, QSPI™, and DSP compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The device also includes a power-on reset function, ensuring that the device powers up in a known state, and an asynchronous CLEAR pin that sets the output to the low end of the selected current range. HART Modem: AD5700, AD5700-1 FUNCTIONAL BLOCK DIAGRAM DVCC SELECT CAP1 DVCC CAP2 AV DD R3SENSE AD5410/AD5420 R2 R3 CLEAR INPUT SHIFT REGISTER AND CONTROL LOGIC POWERON RESET 12/16 IOUT 12-/16-BIT DAC FAULT RSET VREF RSET REFOUT REFIN GND 07027-001 LATCH SCLK SDIN SDO BOOST Figure 1. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5410/AD5420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 AD5410/AD5420 Features ............................................................ 22 Applications ....................................................................................... 1 Fault Alert .................................................................................... 22 General Description ......................................................................... 1 Asynchronous Clear (CLEAR) ................................................. 22 Companion Products ....................................................................... 1 Internal Reference ...................................................................... 22 Functional Block Diagram .............................................................. 1 External Current Setting Resistor ............................................ 22 Revision History ............................................................................... 3 Digital Power Supply.................................................................. 22 Specifications..................................................................................... 4 External Boost Function............................................................ 22 AC Performance Characteristics ................................................ 6 HART Communication ............................................................. 23 Timing Characteristics ................................................................ 6 Digital Slew Rate Control .......................................................... 23 Absolute Maximum Ratings ............................................................ 8 IOUT Filtering Capacitors ............................................................ 25 ESD Caution .................................................................................. 8 Feedback/Monitoring of Output Current ............................... 25 Pin Configuration and Function Descriptions ............................. 9 Applications Information .............................................................. 27 Typical Performance Characteristics ........................................... 11 Driving Inductive Loads............................................................ 27 Terminology .................................................................................... 16 Transient Voltage Protection .................................................... 27 Theory of Operation ...................................................................... 17 Layout Guidelines....................................................................... 27 Architecture ................................................................................. 17 Galvanically Isolated Interface ................................................. 27 Serial Interface ............................................................................ 17 Microprocessor Interfacing ....................................................... 28 Power-On State ........................................................................... 20 Thermal and Supply Considerations ....................................... 28 Transfer Function ....................................................................... 20 Industrial, HART Compatible Analog Output Application . 29 Data Register ............................................................................... 20 Outline Dimensions ....................................................................... 30 Control Register .......................................................................... 20 Ordering Guide .......................................................................... 30 Reset Register .............................................................................. 21 Status Register ............................................................................. 21 Rev. H | Page 2 of 30 Data Sheet AD5410/AD5420 REVISION HISTORY 4/15—Rev. G to Rev. H Changes to Table 3 ............................................................................ 6 Changes to Table 5 ............................................................................ 9 10/14—Rev. F to Rev. G Changes to Power-On State Section .............................................20 10/13—Rev. E to Rev. F Moved Revision History ................................................................... 3 Changes to Figure 51 ......................................................................27 Changes to Figure 55 ......................................................................29 3/13—Rev. D to Rev. E Changes to Table 4 ............................................................................ 7 Added Figure 40, Renumbered Sequentially ...............................19 Changes to Table 10 ........................................................................20 Changes to Thermal and Supply Considerations Section and Table 21 .....................................................................................27 Updated Outline Dimensions ........................................................29 5/12—Rev. C to Rev. D Reorganized Layout ........................................................... Universal Changes to Product Title .................................................................. 1 Added Companion Products Section; Changes to Features Section and Applications Section .................................................... 1 Changes to Table 5 ............................................................................ 9 Change to Figure 8 ..........................................................................11 Added HART Communication Section and Figure 41, Renumbered Sequentially ..............................................................21 Changes to Industrial, HART Compatible Analog Output Application Section and Figure 54 ................................................27 11/11—Rev. B to Rev. C Changes to Table 10 ........................................................................ 18 2/10—Rev. A to Rev. B Changes to Figure 46 ..................................................................... 23 8/09—Rev. 0 to Rev. A Changes to Features and General Description ............................. 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Introduction to Table 4 and to Table 4 ...................... 7 Added Figure 6, Changes to Figure 5 and Table 5 ........................ 8 Added Feedback/Monitoring of Output Current Section, Including Figure 45 to Figure 47; Renumbered Subsequent Figures .............................................................................................. 23 Changes to Thermal and Supply Considerations Section and Table 21 ............................................................................................. 26 Updated Outline Dimensions........................................................ 28 Changes to Ordering Guide ........................................................... 28 3/09—Revision 0: Initial Version Rev. H | Page 3 of 30 AD5410/AD5420 Data Sheet SPECIFICATIONS AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 OUTPUT CURRENT RANGES ACCURACY, INTERNAL RSET Resolution Total Unadjusted Error (TUE) Relative Accuracy (INL)2 Differential Nonlinearity (DNL) Offset Error Offset Error Temperature Coefficient (TC)3 Gain Error Gain Error Temperature Coefficient (TC)3 Full-Scale Error Full-Scale Error Temperature Coefficient (TC)3 ACCURACY, EXTERNAL RSET Resolution Total Unadjusted Error (TUE) Relative Accuracy (INL)2 Differential Nonlinearity (DNL) Offset Error Offset Error Temperature Coefficient (TC)3 Gain Error Gain Error Temperature Coefficient (TC)3 Full-Scale Error Full-Scale Error Temperature Coefficient (TC)3 OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage Output Current Drift vs. Time Resistive Load Inductive Load DC Power Supply Rejection Ratio (PSRR) Min 0 0 4 16 12 −0.3 −0.13 −0.5 −0.3 −0.024 −0.032 −1 −0.27 −0.12 −0.18 −0.03 −0.22 −0.06 −0.2 −0.1 16 12 −0.15 −0.06 −0.3 −0.1 −0.012 −0.032 −1 −0.1 −0.03 −0.08 −0.05 −0.15 −0.06 Typ ±0.08 ±0.15 ±0.08 ±16 ±0.006 ±0.012 ±10 ±0.08 ±12 ±0.01 ±0.02 ±0.006 ±3 ±0.003 ±4 ±0.01 ±7 0 Max 24 20 20 +0.3 +0.13 +0.5 +0.3 +0.024 +0.032 +1 +0.27 +0.12 +0.18 +0.03 +0.22 +0.06 +0.2 +0.1 +0.15 +0.06 +0.3 +0.1 +0.012 +0.032 +1 +0.1 +0.03 +0.08 +0.05 +0.15 +0.06 AVDD − 2.5 50 20 1200 50 1 Rev. H | Page 4 of 30 Unit mA mA mA Test Conditions/Comments Bits Bits % FSR % FSR % FSR % FSR % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR AD5420 AD5410 AD5420 AD5420, TA = 25°C AD5410 AD5410, TA = 25°C AD5420 AD5410 Guaranteed monotonic ppm FSR/°C % FSR % FSR ppm FSR/°C Bits Bits % FSR % FSR % FSR % FSR % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C V ppm FSR ppm FSR Ω mH µA/V TA = 25°C AD5420 AD5420, TA = 25°C AD5410 AD5410, TA = 25°C TA = 25°C Assumes an ideal 15 kΩ resistor AD5420 AD5410 AD5420 AD5420, TA = 25°C AD5410 AD5410, TA = 25°C AD5420 AD5410 Guaranteed monotonic TA = 25°C TA = 25°C TA = 25°C Internal RSET, drift after 1000 hours at 125°C External RSET, drift after 1000 hours at 125°C TA = 25°C Data Sheet Parameter1 Output Impedance Output Current Leakage R3 Resistor Value R3 Resistor Temperature Coefficient (TC) IBIAS Current IBIAS Current Temperature Coefficient (TC) REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference TC3, 4 Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density3 Output Voltage Drift vs. Time3 Capacitive Load3 Load Current3 Short-Circuit Current3 Load Regulation3 DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS3 SDO Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Output Low Voltage, VOL Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS AVDD DVCC Input Voltage Output Voltage Output Load Current3 Short-Circuit Current3 AIDD DICC Power Dissipation AD5410/AD5420 Min 36 399 Typ 50 60 40 30 444 30 Max 44 489 Unit MΩ pA Ω ppm/°C µA ppm/°C Test Conditions/Comments Output disabled TA = 25°C 4.95 25 5 30 5.05 V kΩ For specified performance 4.995 5.000 1.8 18 100 50 600 5 7 95 5.005 10 V ppm/°C µV p-p nV/√Hz ppm nF mA mA ppm/mA TA = 25°C At 10 kHz Drift after 1000 hours, TA = 125°C JEDEC compliant 2 0.8 +1 −1 10 0.4 DVCC − 0.5 −1 Sinking 200 µA Sourcing 200 µA 0.4 V V V 10 kΩ pull-up resistor to DVCC 2.5 mA load current 10 kΩ pull-up resistor to DVCC 40 60 V V TSSOP package LFCSP package 5.5 V V mA mA mA mA mA mW mW Internal supply disabled DVCC can be overdriven up to 5.5 V +1 0.6 3.6 2.7 Per pin Per pin V V µA pF 5 10.8 10.8 V V µA pF 4.5 5 20 3 4 1 144 50 Output disabled Output enabled VIH = DVCC, VIL = GND AVDD = 40 V, IOUT = 0 mA AVDD = 15 V, IOUT = 0 mA Temperature range: −40°C to +85°C; typical at +25°C. For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured from Code 256 for the AD5420 and Code 16 for the AD5410. 3 Guaranteed by design and characterization but not production tested. 4 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C. 1 2 Rev. H | Page 5 of 30 AD5410/AD5420 Data Sheet AC PERFORMANCE CHARACTERISTICS AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 DYNAMIC PERFORMANCE Output Current Settling Time2 Min AC PSRR 1 2 Typ Max 10 40 −75 Unit Test Conditions/Comments µs µs dB 16 mA step, to 0.1% FSR 16 mA step, to 0.1% FSR, L = 1 mH 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage Guaranteed by design and characterization; not production tested. Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit. TIMING CHARACTERISTICS AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 WRITE MODE t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 READBACK MODE t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 DAISY-CHAIN MODE t21 t22 t23 t24 t25 t26 t27 t28 t29 Limit at TMIN, TMAX Unit Description 33 13 13 13 5 5 5 40 20 5 ns min ns min ns min ns min µs min ns min ns min ns min ns min µs max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time CLEAR pulse width CLEAR activation time 90 40 40 13 40 5 5 40 35 35 ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO = 50 pF)4 LATCH rising edge to SDO tristate 90 40 40 13 40 5 5 40 35 ns min ns min ns min ns min ns min ns min ns min ns min ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO = 50 pF)4 Guaranteed by characterization but not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. See Figure 2, Figure 3, and Figure 4. 4 CLSDO = capacitive load on SDO output. 1 2 3 Rev. H | Page 6 of 30 Data Sheet AD5410/AD5420 t1 SCLK 1 2 24 t2 t3 t4 t5 LATCH t7 t6 SDIN t8 DB23 DB0 t9 CLEAR t10 07027-002 IOUT Figure 2. Write Mode Timing Diagram t11 SCLK 1 2 t14 2 1 24 t13 t12 8 9 23 22 24 t15 LATCH DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ t20 t19 X SDO UNDEFINED DATA X X X DB15 FIRST 8 BITS ARE DON’T CARE BITS DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 3. Readback Mode Timing Diagram t21 SCLK 1 2 26 25 24 48 t22 t23 t24 t25 LATCH t27 t26 SDIN DB0 DB23 INPUT WORD FOR DAC N SDO DB23 DB23 t29 DB0 t28 DB0 INPUT WORD FOR DAC N – 1 DB23 UNDEFINED DB0 INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. H | Page 7 of 30 07027-004 SDIN t18 t17 07027-003 t16 AD5410/AD5420 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 80 mA do not cause SCR latch-up. Table 4. Parameter AVDD to GND DVCC to GND Digital Inputs to GND Digital Outputs to GND REFIN, REFOUT to GND IOUT to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 24-Lead TSSOP_EP Package Thermal Impedance, θJA Thermal Impedance, θJC 40-Lead LFCSP Package Thermal Impedance, θJA Thermal Impedance, θJC Power Dissipation Lead Temperature Soldering ESD (Human Body Model) Rating −0.3 V to +60 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or +7 V (whichever is less) −0.3 V to DVCC + 0.3 V or +7 V (whichever is less) −0.3 V to +7 V −0.3 V to AVDD Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −40°C to +85°C1 −65°C to +150°C 125°C 35°C/W2 9°C/W 33°C/W2 4°C/W (TJ max − TA)/θJA JEDEC industry standard J-STD-020 2 kV 1 Power dissipated on chip must be derated to keep junction temperature below 125°C. The assumption is that the maximum power dissipation condition is sourcing 24 mA into ground from AVDD with a 4 mA on-chip current. 2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with thermal vias. Ref: JEDEC JESD51 documents. Rev. H | Page 8 of 30 Data Sheet AD5410/AD5420 NC FAULT 3 22 CAP2 GND 4 NC 1 FAULT 2 GND 3 GND 4 CLEAR 5 LATCH 6 SCLK 7 SDIN 8 SDO 9 NC 10 21 CAP1 20 BOOST TOP VIEW (Not to Scale) 19 IOUT 18 R3SENSE SCLK 8 17 NC SDIN 9 16 DVCC SELECT SDO 10 15 REFIN GND 11 14 REFOUT GND 12 13 RSET LATCH 7 AD5410/AD5420 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC CAP2 CAP1 BOOST IOUT R3SENSE NC DVCC SELECT NC NC NC GND GND GND GND RSET REFOUT REFIN NC NC GND 5 CLEAR 6 PIN 1 INDICATOR 11 12 13 14 15 16 17 18 19 20 AD5410/ AD5420 NOTES 1. NC = NO CONNECT. 2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. NOTES 1. NC = NO CONNECT. 2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 07027-053 AVDD 23 40 39 38 37 36 35 34 33 32 31 24 07027-005 GND 1 DVCC 2 NC DVCC NC GND AVDD NC NC NC NC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. LFCSP Pin Configuration Figure 5. TSSOP Pin Configuration Table 5. Pin Function Descriptions TSSOP Pin No. 1, 4, 5, 12 2 3 LFCSP Pin No. 3, 4, 14, 15, 37 39 2 Mnemonic GND DVCC FAULT 6 5 CLEAR 7 6 LATCH 8 7 SCLK 9 10 8 9 SDIN SDO 11 13 12, 13 16 GND RSET 14 17 REFOUT 15 16 18 23 REFIN DVCC SELECT 17, 23 1, 10, 11, 19, 20, 21, 22, 24, 30, 31, 32, 33, 34, 35, 38, 40 NC Description These pins must be connected to ground. Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. Fault Alert. This pin is asserted low when an open circuit is detected between IOUT and GND or an overtemperature is detected. The FAULT pin is an open-drain output and must be connected to DVCC through a pull-up resistor (typically 10 kΩ). Active High Input. Asserting this pin sets the output current to the zero-scale value, which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA. Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data into the relevant register. In the case of the data register, the output current is also updated. Serial Clock Input. Data is clocked into the input shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the rising edge of SCLK. Serial Data Output. This pin is used to clock data from the device in daisy-chain or readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and Figure 4. Ground Reference Pin. An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the overall performance of the device. See the Specifications and AD5410/AD5420 Features sections. Internal Reference Voltage Output. VREFOUT = 5 V ± 5 mV at TA = 25°C. Typical temperature drift is 1.8 ppm/°C. External Reference Voltage Input. VREFIN = 5 V ± 50 mV for specified performance. This pin, when connected to GND, disables the internal supply, and an external supply must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. In this case, it is recommended to connect a 0.1 μF capacitor between DVCC and GND. See the AD5410/AD5420 Features section. Do not connect to these pins. Rev. H | Page 9 of 30 AD5410/AD5420 Data Sheet TSSOP Pin No. 18 LFCSP Pin No. 25 Mnemonic R3SENSE 19 20 26 27 IOUT BOOST 21 28 CAP1 22 29 CAP2 24 25 (EPAD) 36 41 (EPAD) AVDD Exposed pad Description The voltage measured between this pin and the BOOST pin is directly proportional to the output current and can be used as a monitor/feedback feature. This should be used as a voltage sense output only; current should not be sourced from this pin. See the AD5410/AD5420 Features section. Current Output Pin. Optional External Transistor Connection. Connecting an external transistor reduces the power dissipated in the AD5410/AD5420. See the AD5410/AD5420 Features section. Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features section. Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features section. Also HART Input Connection, see Device Features Section. Positive Analog Supply Pin. Voltage ranges from 10.8 V to 40 V. Ground Reference Connection. It is recommended that the exposed pad be thermally connected to a copper plane for enhanced thermal performance. Rev. H | Page 10 of 30 Data Sheet AD5410/AD5420 TYPICAL PERFORMANCE CHARACTERISTICS 0.004 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET , BOOST TRANSISTOR INTERNAL RSET , BOOST TRANSISTOR 0.002 INL ERROR (% FSR) –0.002 –0.004 –0.006 –0.008 –0.010 0 10,000 20,000 30,000 40,000 CODE 50,000 0.6 0.003 INL ERROR (% FSR) 0 –0.2 –0.4 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET, BOOST TRANSISTOR INTERNAL RSET, BOOST TRANSISTOR –1.0 0 10,000 20,000 30,000 40,000 CODE 50,000 0.01 0.6 DNL ERROR (LSB) –0.01 –0.03 AVDD = 24V TA = 25°C RLOAD = 250Ω –0.09 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET , BOOST TRANSISTOR INTERNAL RSET , BOOST TRANSISTOR 0 10,000 20,000 30,000 40,000 CODE 50,000 0 20 40 TEMPERATURE (°C) 60 80 AVDD = 24V ALL RANGES INTERNAL AND EXTERNAL RSET 0.4 0.2 0 –0.2 –0.4 –0.6 07027-008 TOTAL UNADJUSTED ERROR (% FSR) 0.8 –0.15 –20 Figure 11. Integral Nonlinearity Error vs. Temperature, External RSET 1.0 –0.13 AVDD = 24V 0mA TO 24mA RANGE –0.001 0.03 –0.11 80 0 0.05 –0.07 60 0.001 –0.003 –40 60,000 Figure 8. Differential Nonlinearity Error vs. Code –0.05 0 20 40 TEMPERATURE (°C) –0.002 07027-007 DNL ERROR (LSB) 0.2 –0.8 –20 0.002 0.4 –0.6 –0.006 Figure 10. Integral Nonlinearity Error vs. Temperature, Internal RSET AVDD = 24V TA = 25°C RLOAD = 250Ω 0.8 –0.004 –0.010 –40 60,000 Figure 7. Integral Nonlinearity Error vs. Code 1.0 –0.002 –0.008 07027-006 AVDD = 2.4V TA = 25°C RLOAD = 250Ω 0 07027-009 0 07027-109 INL ERROR (% FSR) 0.002 AVDD = 24V 0mA TO 24mA RANGE 60,000 Figure 9. Total Unadjusted Error vs. Code 07027-010 0.004 –0.8 –1.0 –40 –20 0 20 40 TEMPERATURE (°C) 60 Figure 12. Differential Nonlinearity Error vs. Temperature Rev. H | Page 11 of 30 80 AD5410/AD5420 Data Sheet 0.015 TA = 25°C 0mA TO 24mA RANGE AVDD = 24V 0.010 INL ERROR (% FSR) 0 –0.05 –0.10 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.15 –0.20 –0.25 –40 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET –20 0 0.005 0 –0.005 –0.010 20 40 TEMPERATURE (°C) 60 –0.015 80 10 0.015 AVDD = 24V 0.05 INL ERROR (%FSR) 0 –0.05 –0.10 30 35 40 –20 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 0 20 0.005 0 –0.005 –0.010 40 60 –0.015 07027-014 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO 07027-017 –0.25 –40 25 AVDD (V) TA = 25°C 0mA TO 24mA RANGE 0.010 –0.20 20 0.020 0.10 –0.15 15 Figure 16. Integral Nonlinearity Error vs. AVDD, External RSET Figure 13. Total Unadjusted Error vs. Temperature OFFSET ERROR (% FSR) 07027-011 0.05 07027-013 TOTAL UNADJUSTED ERROR (%FSR) 0.10 –0.020 10 80 15 20 TEMPERATURE (°C) 25 AVDD (V) 30 35 40 Figure 17. Integral Nonlinearity Error vs. AVDD, Internal RSET Figure 14. Offset Error vs. Temperature 1.0 0.06 0.04 TA = 25°C 0mA TO 24mA RANGE 0.8 AVDD = 24V 0.6 DNL ERROR (LSB) 0 –0.02 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.06 –0.08 –0.10 –40 –20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 20 40 TEMPERATURE (°C) 60 0.4 0.2 0 –0.2 –0.4 –0.6 07027-012 –0.04 07027-018 GAIN ERROR (% FSR) 0.02 –0.8 –1.0 10 80 Figure 15. Gain Error vs. Temperature 15 20 25 AVDD (V) 30 35 40 Figure 18. Differential Nonlinearity Error vs. AVDD, External RSET Rev. H | Page 12 of 30 Data Sheet AD5410/AD5420 1.0 2.5 AVDD = 15V IOUT = 24mA RLOAD = 500Ω 0.8 TA = 25°C 0mA TO 24mA RANGE 2.0 HEADROOM VOLTAGE (V) 0.4 0.2 0 –0.2 –0.4 1.5 1.0 0.5 07027-015 –0.6 –0.8 –1.0 10 15 20 25 30 35 0 –40 40 07027-019 DNL ERROR (LSB) 0.6 –20 0 AVDD (V) Figure 19. Differential Nonlinearity Error vs. AVDD, Internal RSET 60 80 Figure 22. Compliance Voltage Headroom vs. Temperature 3.5 0.025 TA = 25°C 0mA TO 24mA RANGE 0.020 AVDD = 24V TA = 25°C RLOAD = 250Ω 3.0 0.015 OUTPUT CURRENT (µA) 2.5 0.005 0 –0.005 –0.010 –0.015 10 15 20 25 30 35 2.0 1.5 1.0 0.5 0 40 07027-020 0.010 07027-016 TOTAL UNADJUSTED ERROR (% FSR) 20 40 TEMPERATURE (°C) 0 100 200 300 TIME (µs) AVDD (V) 400 500 600 Figure 23. Output Current vs. Time on Power-Up Figure 20. Total Unadjusted Error vs. AVDD, External RSET 20 0.05 10 OUTPUT CURRENT (µA) 0.01 –0.01 –0.03 TA = 25°C 0mA TO 24mA RANGE –0.05 –0.07 –0.09 AVDD = 24V TA = 25°C RLOAD = 250Ω 0 –10 –20 –30 –0.11 –0.13 –0.15 10 15 20 25 30 35 –40 07027-021 07027-032 TOTAL UNADJUSTED ERROR (%FSR) 0.03 –50 0 40 AVDD (V) 0.5 1.0 1.5 2.0 2.5 3.0 TIME (µs) 3.5 4.0 4.5 Figure 24. Output Current vs. Time on Output Enable Figure 21. Total Unadjusted Error vs. AVDD, Internal RSET Rev. H | Page 13 of 30 5.0 AD5410/AD5420 Data Sheet 900 TA = 25°C 800 700 AVDD DICC (µA) 600 DVCC = 5V 500 3 400 REFERENCE OUTPUT 300 200 0.5 1.0 1.5 2.0 2.5 3.0 3.5 LOGIC VOLTAGE (V) 4.0 4.5 5.0 07027-025 0 0 1 07027-022 DVCC = 3V 100 CH1 2.00V CH3 5.00V Figure 25. DICC vs. Logic Input Voltage M200µs CH3 2.1V Figure 28. Reference Turn-on Transient 5.0 TA = 25°C IOUT = 0mA 4.5 4.0 AIDD (mA) 3.5 3.0 2.5 1 2.0 1.5 0.5 0 10 20 15 25 AVDD (V) 35 30 07027-026 07027-023 1.0 40 CH1 2µV M2.00s LINE 1.8V Figure 29. Reference Noise (0.1 Hz to 10 Hz Bandwidth) Figure 26. AIDD vs. AVDD 9 TA = 25°C 7 6 5 1 4 3 2 1 0 –21 –19 –17 –15 –13 –11 –9 –7 –5 LOAD CURRENT (mA) –3 –1 07027-027 07027-024 DVCC OUTPUT VOLTAGE (V) 8 1 CH1 20µV Figure 27. DVCC Output Voltage vs. Load Current M2.00s LINE Figure 30. Reference Noise (100 kHz Bandwidth) Rev. H | Page 14 of 30 0V Data Sheet AD5410/AD5420 70 5.0005 40 30 20 TA = 25°C AVDD = 40V OUTPUT DISABLED 10 07027-028 0 –10 0 5 10 4.9990 4.9985 4.9980 4.9975 4.9970 4.9965 4.9960 4.9955 45 40 30 35 20 25 15 COMPLIANCE VOLTAGE (V) 4.9995 07027-031 REFERENCE OUTPUT VOLTAGE (V) 50 LEAKAGE CURRENT (pA) TA = 25°C AVDD = 24V 5.0000 60 0 Figure 31. Output Leakage Current vs. Compliance Voltage 3 4 5 6 LOAD CURRENT (mA) 7 8 9 30 50 DEVICES SHOWN AVDD = 24V 5.002 OUTPUT CURRENT (µA) 5.000 4.999 4.998 0x8000 TO 0x7FFF 0x7FFF TO 0x8000 AVDD = 24V TA = 25°C RLOAD = 250Ω 20 5.001 10 0 –10 –20 0 20 40 TEMPERATURE (°C) 60 07027-049 07027-029 –20 4.997 –40 –30 80 0 2 Figure 32. Reference Output Voltage vs. Temperature 4 6 8 10 12 TIME (µs) 14 16 18 20 Figure 35. Digital-to-Analog Glitch 45 25 AVDD = 24V 40 20 OUTPUT CURRENT (mA) 35 30 25 20 15 10 TA = 25°C AVDD = 24V RLOAD = 300Ω 15 10 5 0 0 1 2 3 4 5 6 7 8 TEMPERATURE COEFFICIENT (ppm/°C) 9 0 –1 10 Figure 33. Reference Temperature Coefficient Histogram 07027-134 5 07027-030 POPULATION (%) 2 Figure 34. Reference Output Voltage vs. Load Current 5.003 REFERENCE OUTPUT VOLTAGE (V) 1 0 1 2 3 4 TIME (µs) 5 6 Figure 36. 4 mA to 20 mA Output Current Step Rev. H | Page 15 of 30 7 8 AD5410/AD5420 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in % FSR, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 7. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 8. Total Unadjusted Error (TUE) Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies and temperature. TUE is expressed in % FSR. A typical TUE vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5410/AD5420 are monotonic over their full operating temperature range. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the data register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range (% FSR). Full-Scale Error Temperature Coefficient (TC) This is a measure of the change in full-scale error with changes in temperature. Full-scale error TC is expressed in ppm FSR/°C. Gain Error Temperature Coefficient (TC) This is a measure of the change in gain error with changes in temperature. Gain error TC is expressed in ppm FSR/°C. Current Loop Compliance Voltage This is the maximum voltage at the IOUT pin for which the output current is equal to the programmed value. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The voltage reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range, expressed in ppm/°C as follows: V REFmax − V REFmin 6 TC = × 10 V × TempRange REFnom where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 5 V. TempRange is the specified temperature range, −40°C to +85°C. Reference Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 15. Rev. H | Page 16 of 30 Data Sheet AD5410/AD5420 THEORY OF OPERATION The AD5410/AD5420 are precision digital-to-current loop output converters designed to meet the requirements of industrial process control applications. They provide a high precision, fully integrated, low cost single-chip solution for generating current loop outputs. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The desired output configuration is user selectable via the control register. ARCHITECTURE The DAC core architecture of the AD5410/AD5420 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 37. The four MSBs of the 12-bit or 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. The remaining 8/12 bits of the dataword drive Switch S0 to Switch S7 or Switch S0 to Switch S11 of an 8-/12-bit voltage mode R-2R ladder network. VOUT 2R 2R 2R 2R 2R 2R 2R S0 S1 S7/S11 E1 E2 E15 8-/12-BIT R-2R LADDER 07027-033 VREFIN FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 37. DAC Ladder Structure The voltage output from the DAC core is converted to a current (see Figure 38) that is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground. AVDD The serial interface works with both a continuous and noncontinuous SCLK. A continuous SCLK source can be used only if LATCH is taken high after the correct number of data bits has been clocked in. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data. The first rising edge of SCLK that clocks in the MSB of the dataword marks the beginning of the write cycle. Exactly 24 rising clock edges must be applied to SCLK before LATCH is brought high. If LATCH is brought high before the 24th rising SCLK edge, the data written is invalid. If more than 24 rising SCLK edges are applied before LATCH is brought high, the input data is also invalid. Table 6. Input Shift Register Format MSB DB23 to DB16 Address byte IOUT Address Byte 00000000 00000001 00000010 Function No operation (NOP) Data register Readback register value as per read address (see Table 8) Control register Reset register Daisy-Chain Operation 07027-034 A1 RSET LSB DB15 to DB0 Data-word Table 7. Address Byte Functions 01010101 01010110 T2 A2 T1 Standalone Operation R3 R2 12-/16-BIT DAC SCLK. The input shift register consists of eight address bits and 16 data bits, as shown in Table 6. The 24-bit word is unconditionally latched on the rising edge of LATCH. Data continues to be clocked in irrespective of the state of LATCH. On the rising edge of LATCH, the data that is present in the input shift register is latched; that is, the last 24 bits to be clocked in before the rising edge of LATCH is the data that is latched. The timing diagram for this operation is shown in Figure 2. Figure 38. Voltage-to-Current Conversion Circuitry SERIAL INTERFACE The AD5410/AD5420 are controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz. They are compatible with SPI, QSPI, MICROWIRE, and DSP standards. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together, as shown in Figure 39. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Daisy-chain mode is enabled by setting the DCEN bit of the control register. The first rising edge of SCLK that clocks in the MSB of the dataword marks the beginning of the write cycle. SCLK is continuously applied to the input shift register. If more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the SDO line. This data, having been clocked out on the previous falling SCLK edge, is valid on the rising edge of SCLK. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Rev. H | Page 17 of 30 AD5410/AD5420 Data Sheet Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5410/AD5420 devices in the chain. When the serial transfer to all devices is complete, LATCH is taken high. This latches the input data in each device in the daisy chain. The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data. See Figure 4 for a timing diagram. AD5410/ AD5420* CONTROLLER DATA OUT SCLK CONTROL OUT LATCH Readback mode is invoked by setting the address byte and read address as shown in Table 9 and Table 8 when writing to the input shift register. The next write to the AD5410/AD5420 should be a NOP command, which clocks out the data from the previously addressed register, as shown in Figure 3. By default, the SDO pin is disabled. After having addressed the AD5410/ AD5420 for a read operation, a rising edge on LATCH enables the SDO pin in anticipation of data being clocked out. After the data has been clocked out on SDO, a rising edge on LATCH disables (tristate) the SDO pin once again. To read back the data register, for example, the following sequence should be implemented: 1. SDIN SERIAL CLOCK Readback Operation 2. DATA IN SDO SDIN Write 0x020001 to the AD5410/AD5420 input shift register. This configures the part for read mode with the data register selected. Follow this with a second write, a NOP condition, 0x000000. During this write, the data from the data register is clocked out on the SDO line. Table 8. Read Address Decoding AD5410/ AD5420* Read Address 00 01 10 SCLK LATCH SDO Function Read status register Read data register Read control register SDIN AD5410/ AD5420* SCLK LATCH *ADDITIONAL PINS OMITTED FOR CLARITY. 07027-035 SDO Figure 39. Daisy Chaining the AD5410/AD5420 Table 9. Input Shift Register Contents for a Read Operation MSB DB23 0 1 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 1 DB16 0 X = don’t care. Rev. H | Page 18 of 30 DB15 to DB2 X1 LSB DB1 DB0 Read address Data Sheet AD5410/AD5420 POWER-ON SOFTWARE RESET CONTROL REGISTER WRITE (ONE WRITE COMMAND) • SELECT RSET EXTERNAL/INTERNAL • SET THE REQUIRED RANGE • CONFIGURE THE SLEW RATE CONTROL (IF REQUIRED) • CONFIGURE DAISY CHAIN MODE (IF REQUIRED) • ENABLE THE OUTPUT CONTROL REGISTER WRITE • DISABLE OUTPUT DATA REGISTER WRITE RSET CONFIGURATION CHANGE RANGE CHANGE Figure 40. Programming Sequence to Write/Enable the Output Correctly Rev. H | Page 19 of 30 07027-300 • WRITE REQUIRED CODE TO DATA REGISTER AD5410/AD5420 Data Sheet POWER-ON STATE DATA REGISTER Upon power-on of the AD5410/AD5420, the power-on reset circuit ensures that all registers are loaded with zero code. As such, the output is disabled (tristate). Also upon power-on, internal calibration registers are read, and the data is applied to internal calibration circuitry. For a reliable read operation, there must be sufficient voltage on the AVDD supply when the read event is triggered by the DVCC power supply powering up. Powering up the DVCC supply after the AVDD supply has reached at least 5 V ensures this. If DVCC and AVDD are powered up simultaneously, then the supplies should be powered up at a rate greater than, typically, 5000 V/sec. If the internal DVCC is enabled, the supplies should be powered up at a rate greater than, typically, 2000 V/sec. If this cannot be achieved, simply issue a reset command to the AD5410/AD5420 after power-on. This performs a power-on reset event, reading the calibration registers and ensuring specified operation of the AD5410/AD5420. To ensure correct calibration and to allow the internal reference to settle to its correct trim value, 40 µs should be allowed after a successful power on reset. The data register is addressed by setting the address byte of the input shift register to 0x01. The data to be written to the data register is entered in Position DB15 to Position DB4 for the AD5410 and in Position DB15 to Position DB0 for the AD5420, as shown in Table 12 and Table 13, respectively. CONTROL REGISTER The control register is addressed by setting the address byte of the input shift register to 0x55. The data to be written to the control register is entered in Position DB15 to Position DB0, as shown in Table 14. The control register bit functions are described in Table 10. Table 10. Control Register Bit Functions Bit REXT Description Setting this bit selects the external current setting resistor. See the AD5410/AD5420 Features section for further details. When using an external current setting resistor, it is recommended to only set REXT when also setting the OUTEN bit. Alternately, REXT can be set before the OUTEN bit is set, but the range (see Table 11) must be changed on the write in which the output is enabled. See Figure 40 for best practice. Output enable. This bit must be set to enable the output. Digital slew rate control. See the AD5410/AD5420 Features section. Digital slew rate control. See the AD5410/AD5420 Features section. Digital slew rate control enable. Daisy-chain enable. Output range select. See Table 11. TRANSFER FUNCTION For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is respectively expressed as IOUT OUTEN SR Clock 20 mA = N × D 2 SR Step 24 mA IOUT = N × D 2 SREN DCEN R2, R1, R0 16 mA IOUT = N × D + 4 mA 2 Table 11. Output Range Options R2 1 1 1 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. R1 0 1 1 R0 1 0 1 Output Range Selected 4 mA to 20 mA current range 0 mA to 20 mA current range 0 mA to 24 mA current range Table 12. Programming the AD5410 Data Register MSB DB15 1 DB14 DB13 DB12 DB7 DB6 DB5 DB4 DB3 X1 DB2 X1 DB1 X1 LSB DB0 X1 DB9 DB8 DB7 16-bit data-word DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0 DB11 DB10 DB9 12-bit data-word DB8 X = don’t care. Table 13. Programming the AD5420 Data Register MSB DB15 DB14 DB13 DB12 DB11 DB10 Table 14. Programming the Control Register MSB DB15 0 DB14 0 DB13 REXT DB12 OUTEN DB11 DB10 DB9 SR clock DB8 Rev. H | Page 20 of 30 DB7 DB6 DB5 SR step DB4 SREN DB3 DCEN DB2 R2 DB1 R1 LSB DB0 R0 Data Sheet AD5410/AD5420 RESET REGISTER Table 15. Status Register Bit Functions The reset register is addressed by setting the address byte of the input shift register to 0x56. The reset register contains a single reset bit at Position DB0, as shown in Table 16. Writing a logic high to this bit performs a reset operation, restoring the part to its power-on state. Bit IOUT Fault Slew Active Description This bit is set if a fault is detected on the IOUT pin. This bit is set while the output value is slewing (slew rate control enabled). This bit is set if the AD5410/AD5420 core temperature exceeds approximately 150°C. Overtemp STATUS REGISTER The status register is a read-only register. The status register bit functionality is shown in Table 15 and Table 17. Table 16. Programming the Reset Register MSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 Reserved DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0 Reset Table 17. Decoding the Status Register MSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 Reserved DB8 DB7 DB6 Rev. H | Page 21 of 30 DB5 DB4 DB3 DB2 IOUT fault DB1 Slew active LSB DB0 Overtemp AD5410/AD5420 Data Sheet AD5410/AD5420 FEATURES FAULT ALERT EXTERNAL CURRENT SETTING RESISTOR The AD5410/AD5420 are equipped with a FAULT pin, which is an open-drain output allowing several AD5410/AD5420 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios: In Figure 38, RSET is an internal sense resistor as part of the voltage-to-current conversion circuitry. The stability of the output current over temperature is dependent on the stability of the value of RSET. An external precision 15 kΩ low drift resistor can be connected from the RSET pin of the AD5410/AD5420 to ground; this improves the overall performance of the AD5410/ AD5420. The external resistor is selected via the control register. See Table 14. • The voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The IOUT current is controlled by a PMOS transistor and internal amplifier, as shown in Figure 38. The internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus, the FAULT output activates slightly before the compliance limit is reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain and an output error does not occur before the FAULT output becomes active. If the core temperature of the AD5410/AD5420 exceeds approximately 150°C. The IOUT fault and overtemp bits of the status register are used in conjunction with the FAULT pin to inform the user which fault condition caused the FAULT pin to be asserted. See Table 17 and Table 15. ASYNCHRONOUS CLEAR (CLEAR) CLEAR is an active high clear that clears the current output to the bottom of its programmed range. It is necessary to maintain CLEAR high for a minimum amount of time (see Figure 2) to complete the operation. When the CLEAR signal is returned low, the output remains at the cleared value. The preclear value can be restored by pulsing the LATCH signal low without clocking any data. A new value cannot be programmed until the CLEAR pin is returned low. DIGITAL POWER SUPPLY By default, the DVCC pin accepts a power supply of 2.7 V to 5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V power supply can be output on the DVCC pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. This facility offers the advantage of not having to bring a digital supply across an isolation barrier. The internal power supply is enabled by leaving the DVCC SELECT pin unconnected. To disable the internal supply, DVCC SELECT should be tied to 0 V. DVCC is capable of supplying up to 5 mA of current. See Figure 27 for a load regulation graph. EXTERNAL BOOST FUNCTION The addition of an external boost transistor, as shown in Figure 41, reduces the power dissipated in the AD5410/AD5420 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 40 V can be used. The external boost capability allows the AD5410/AD5420 to be used at the extremes of the supply voltage, load current, and temperature range. The boost transistor can also be used to reduce the amount of temperature-induced drift in the part. This minimizes the temperature-induced drift of the on-chip voltage reference, which improves drift and linearity. MJD31C OR 2N3053 BOOST AD5410/ AD5420 IOUT INTERNAL REFERENCE 1kΩ The AD5410/AD5420 contain an integrated +5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature drift coefficient of 10 ppm/°C maximum. The reference voltage is buffered and externally available for use elsewhere within the system. See Figure 34 for a load regulation graph of the integrated reference. Rev. H | Page 22 of 30 0.022µF RL Figure 41. External Boost Configuration 07027-036 • Data Sheet AD5410/AD5420 HART COMMUNICATION Table 18. Slew Rate Update Clock Values The AD5410/AD5420 contain a CAP2 pin, into which a HART signal can be coupled. The HART signal appears on the current output if the output is enabled. To achieve a 1 mA peak-to-peak current, the signal amplitude at the CAP2 pin must be 48 mV peak-to-peak. Assuming that the modem output amplitude is 500 mV peak-to-peak, its output must be attenuated by 500/48 = 10.42. If this voltage is used, the current output should meet the HART amplitude specifications. Figure 42 shows the recommended circuit for attenuating and coupling in the HART signal. SR Clock 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 07027-200 CAP2 HART MODEM C1 OUTPUT Figure 42. Coupling HART Signal In determining the absolute values of the capacitors, ensure that the FSK output from the modem is passed undistorted. Thus, the bandwidth presented to the modem output signal must pass 1200 Hz and 2200 Hz frequencies. The recommended values are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART. DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5410/AD5420 allows the user to control the rate at which the output current changes. With the slew rate control feature disabled, the output current changes at a rate of approximately 16 mA in 10 µs (see Figure 36). This varies with load conditions. To reduce the slew rate, enable the slew rate control feature. With the feature enabled via the SREN bit of the control register (see Table 14), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the control register, as shown in Table 14. The parameters are SR clock and SR step. SR clock defines the rate at which the digital slew is updated, SR step defines by how much the output value changes at each update. Both parameters together define the rate of change of the output current. Table 18 and Table 19 outline the range of values for both the SR clock and SR step parameters. Figure 43 shows the output current changing for ramp times of 10 ms, 50 ms, and 100 ms. Table 19. Slew Rate Step Size Options SR Step 000 001 010 011 100 101 110 111 AD5410 Step Size (LSB) 1/16 1/8 1/4 1/2 1 2 4 8 AD5420 Step Size (LSB) 1 2 4 8 16 32 64 128 25 TA = 25°C AVDD = 24V RLOAD = 300Ω 20 15 10 5 0 –10 10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5 50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7 100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5 0 10 20 30 40 50 60 TIME (ms) 70 80 90 07027-139 C2 OUTPUT CURRENT (mA) AVDD Update Clock Frequency (Hz) 257,730 198,410 152,440 131,580 115,740 69,440 37,590 25,770 20,160 16,030 10,290 8280 6900 5530 4240 3300 100 110 Figure 43. Output Current Slewing Under Control of the Digital Slew Rate Control Feature Rev. H | Page 23 of 30 AD5410/AD5420 Data Sheet The time it takes for the output current to slew over a given output range can be expressed as follows: Slew Time = Output Change (1) Step Size × Update Clock Frequency × LSB Size where: Slew Time is expressed in seconds. Output Change is expressed in amps. When the slew rate control feature is enabled, all output changes change at the programmed slew rate. If the CLEAR pin is asserted, the output slews to the zero-scale value at the programmed slew rate. The output can be halted at its current value with a write to the control register. To avoid halting the output slew, the slew active bit can be read to check that the slew has completed before writing to any of the AD5410/ AD5420 registers (see Table 17). The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. Table 20 shows the range of programmable slew times for a fullscale change on any of the output ranges. The values in Table 20 were obtained using Equation 1. The digital slew rate control feature results in a staircase formation on the current output, as shown in Figure 47. Figure 47 also shows how the staircase can be removed by connecting capacitors to the CAP1 and CAP2 pins, as described in the IOUT Filtering Capacitors section. Table 20. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range Update Clock Frequency (Hz) 257,730 198,410 152,440 131,580 115,740 69,440 37,590 25,770 20,160 16,030 10,290 8280 6900 5530 4240 3300 1 0.25 0.33 0.43 0.50 0.57 0.9 1.7 2.5 3.3 4.1 6.4 7.9 9.5 12 15 20 2 0.13 0.17 0.21 0.25 0.28 0.47 0.87 1.3 1.6 2.0 3.2 4.0 4.8 5.9 7.7 9.9 4 0.06 0.08 0.11 0.12 0.14 0.24 0.44 0.64 0.81 1.0 1.6 2.0 2.4 3.0 3.9 5.0 Rev. H | Page 24 of 30 8 0.03 0.04 0.05 0.06 0.07 0.12 0.22 0.32 0.41 0.51 0.80 1.0 1.2 1.5 1.9 2.5 Step Size (LSBs) 16 0.016 0.021 0.027 0.031 0.035 0.06 0.11 0.16 0.20 0.26 0.40 0.49 0.59 0.74 0.97 1.24 32 0.008 0.010 0.013 0.016 0.018 0.03 0.05 0.08 0.10 0.13 0.20 0.25 0.30 0.37 0.48 0.62 64 0.004 0.005 0.007 0.008 0.009 0.015 0.03 0.04 0.05 0.06 0.10 0.12 0.15 0.19 0.24 0.31 128 0.0020 0.0026 0.0034 0.0039 0.0044 0.007 0.014 0.020 0.025 0.03 0.05 0.06 0.07 0.09 0.12 0.16 Data Sheet AD5410/AD5420 IOUT FILTERING CAPACITORS 6.8 OUTPUT CURRENT (mA) AVDD C1 C2 AVDD CAP1 GND CAP2 6.4 6.3 6.1 –1 The capacitors form a filter on the current output circuitry, as shown in Figure 45, reducing the bandwidth and the slew rate of the output current. Figure 46 shows the effect the capacitors have on the slew rate of the output current. To achieve significant reductions in the rate of change, very large capacitor values are required, which may not be suitable in some applications. In this case, the digital slew rate control feature should be used. The capacitors can be used in conjunction with the digital slew rate control feature as a means of smoothing out the steps caused by the digital code increments, as shown in Figure 47. C1 C2 AVDD CAP2 NO EXTERNAL CAPS 10nF ON CAP1 10nF ON CAP2 BOOST 12.5kΩ IOUT 07027-038 RSET 1 2 3 4 TIME (ms) 6 VR 3 − I BIAS R3 (2) AVDD RMETAL R3 40Ω 20 R3SENSE BOOST IOUT TA = 25°C AVDD = 24V RLOAD = 300Ω IBIAS 444µA 0 0.5 1.0 1.5 2.0 TIME (ms) Figure 48. Structure of Current Output Circuit 07027-142 5 0 –0.5 07027-050 10 NO CAPACITOR 10nF ON CAP1 10nF ON CAP2 47nF ON CAP1 47nF ON CAP2 2.5 3.0 3.5 8 where: VR3 is the voltage drop across R3 measured between the R3SENSE and BOOST pins. IBIAS is a constant bias current flowing through R3 with a typical value of 444 µA. R3 is the resistance value of resistor R3 with a typical value of 40 Ω. 25 15 7 For feedback or monitoring of the output current value, a sense resistor can be placed in series with the IOUT output pin and the voltage drop across it measured. As well as being an additional component, the resistor increases the compliance voltage required. An alternative method is to use a resistor that is already in place. R3 is such a resistor and is internal to the AD5410/AD5420, as shown in Figure 48. By measuring the voltage between the R3SENSE and BOOST pins, the value of the output current can be calculated as follows: Figure 45. IOUT Filter Circuitry OUTPUT CURRENT (mA) 5 FEEDBACK/MONITORING OF OUTPUT CURRENT I OUT = 4kΩ 0 Figure 47. Smoothing Out the Steps Caused by the Digital Slew Rate Control Feature 40Ω DAC 6.5 6.2 Figure 44. IOUT Filtering Capacitors CAP1 6.6 IOUT 07027-037 AD5410/ AD5420 TA = 25°C AVDD = 24V RLOAD = 300Ω 6.7 07027-043 Capacitors can be placed between CAP1 and AVDD, and CAP2 and AVDD, as shown in Figure 44. 4.0 Figure 46. Slew Controlled 4 mA to 20 mA Output Current Step Using External Capacitors on the CAP1 and CAP2 Pins Rev. H | Page 25 of 30 AD5410/AD5420 Data Sheet R3 and IBIAS both have a tolerance of ±10% and a temperature coefficient of 30 ppm/°C. Connecting to R3SENSE rather than AVDD avoids incorporating into R3 internal metal connections that have large temperature coefficients and result in large errors. See Figure 49 for a plot of R3 vs. ambient temperature and Figure 50 for a plot of R3 vs. output current. To eliminate errors due to the tolerances of R3 and IBIAS, a twomeasurement calibration can be performed as the following example illustrates: 1. 40.98 40.96 IOUT = 12mA R3 = VR3/(12mA + 444µA) 2. R3 RESISTANCE (Ω) 40.94 40.92 40.90 Using this information and Equation 2, two simultaneous equations can be generated from which the values of R3 and IBIAS can be calculated as follows: 40.88 40.86 40.84 VR 3 − I BIAS R3 V ⇒ I BIAS = R 3 − I OUT R3 I OUT = 40.82 –20 0 20 40 60 AMBIENT TEMPERATURE (°C) 80 100 07027-051 40.80 40.78 –40 Program code 0x1000 and measure IOUT and VR3. In this example, the measured values are IOUT = 1.47965 mA VR3 = 79.55446 mV Program Code 0xF000 and measure IOUT and VR3 again. The measured values this time are IOUT = 22.46754 mA VR3 = 946.39628 mV Figure 49. R3 Resistor Value vs. Temperature Simultaneous Equation 1 42.0 TA = 25°C 41.8 R3 = VR3/(IOUT + 444µA) I BIAS = 41.6 Simultaneous Equation 2 41.4 I BIAS = 41.2 41.0 0.94639628 − 0.02246754 R3 From these two equations, 40.8 R3 = 41.302 Ω and I BIAS = 446.5 μA 40.6 40.4 And Equation 2 becomes 40.2 40.0 0 5 10 15 IOUT (mA) 20 25 I OUT = 07027-052 R3 (Ω) 0.07955446 − 0.00147965 R3 Figure 50. R3 Resistor Value vs. IOUT Rev. H | Page 26 of 30 VR 3 − 446.5µA 41.302 Data Sheet AD5410/AD5420 APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads, connect a 0.01 μF capacitor between IOUT and GND. This ensures stability with loads beyond 50 mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling. Alternatively, the capacitor can be connected from CAP1 and/or CAP2 to AVDD to reduce the slew rate of the current. The digital slew rate control feature may also prove useful in this situation. TRANSIENT VOLTAGE PROTECTION The AD5410/AD5420 contain ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5410/AD5420 from excessively high voltage transients, external power diodes and a surge current limiting resistor may be required, as shown in Figure 51. The constraint on the resistor value is that during normal operation, the output level at IOUT must remain within its voltage compliance limit of AVDD − 2.5 V, and the two protection diodes and resistor must have appropriate power ratings. Further protection can be provided with transient voltage suppressors (TVS), or transorbs. These are available as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppressors (protect against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field connected nodes be protected. AVDD AVDD AD5410/ AD5420 IOUT RL 07027-039 GND RP capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5410/AD5420 should use as large a trace as possible to provide low impedance paths and to reduce the effects of glitches on the power supply line. Fastswitching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because noise can couple through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best method but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder side. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The iCoupler® family of products from Analog Devices, Inc., provides voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5410/AD5420 is ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 52 shows a 4-channel isolated interface to the AD5410/ AD5420 using an ADuM1400. For further information, visit www.analog.com. Figure 51. Output Transient Voltage Protection In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board (PCB) on which the AD5410/AD5420 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5410/AD5420 are in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5410/AD5420 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF ADuM1400* SERIAL CLOCK OUT VIA SERIAL DATA OUT VIB SYNC OUT VIC CONTROL OUT VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE *ADDITIONAL PINS OMITTED FOR CLARITY. Rev. H | Page 27 of 30 Figure 52. Isolated Interface VOA TO SCLK VOB TO SDIN VOC TO LATCH VOD TO CLEAR 07027-040 CONTROLLER LAYOUT GUIDELINES AD5410/AD5420 Data Sheet MICROPROCESSOR INTERFACING 2.5 Microprocessor interfacing to the AD5410/AD5420 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a latch signal. The AD5410/AD5420 require a 24-bit data-word with data valid on the rising edge of SCLK. LFCSP POWER DISSIPATION (W) 2.0 For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents of the registers can be read using the readback function. 1.5 TSSOP 1.0 THERMAL AND SUPPLY CONSIDERATIONS 0 The AD5410/AD5420 are designed to operate at a maximum junction temperature of 125°C. It is important that the device not be operated under conditions that cause the junction temperature to exceed this value. Excessive junction temperature can occur if the AD5410/AD5420 are operated from the maximum AVDD, while driving the maximum current (24 mA) directly to ground. In this case, the ambient temperature should be controlled or AVDD should be reduced. 40 45 50 55 60 65 70 75 AMBIENT TEMPERATURE (°C) 80 85 07027-055 0.5 Figure 53. Maximum Power Dissipation vs. Ambient Temperature 65 LFCSP 60 SUPPLY VOLTAGE (V) 55 At the maximum ambient temperature of 85°C, the 24-lead TSSOP can dissipate 1.14 W, and the 40-Lead LFCSP can dissipate 1.21 W. To ensure that the junction temperature does not exceed 125°C while driving the maximum current of 24 mA directly into ground (also adding an on-chip current of 4 mA), AVDD should be reduced from the maximum rating to ensure that the package is not required to dissipate more power than previously stated (see Table 21, Figure 53, and Figure 54). 50 45 TSSOP 40 35 25 25 35 45 55 65 AMBIENT TEMPERATURE (°C) 75 85 07027-054 30 Figure 54. Maximum Supply Voltage vs. Ambient Temperature Table 21. Thermal and Supply Considerations Consideration Maximum Allowed Power Dissipation When Operating at an Ambient Temperature of 85°C Maximum Allowed Ambient Temperature When Operating from a Supply of 40 V/60 V and Driving 24 mA Directly to Ground Maximum Allowed Supply Voltage When Operating at an Ambient Temperature of 85°C and Driving 24 mA Directly to Ground TSSOP T J max − T A LFCSP = Θ JA 125 − 85 T J max − T A = 1.14 W = Θ JA 35 ( ) 125 − 85 = 1.21 W 33 ( ) T J max − P D × Θ JA = 125 − 40 × 0.028 × 35 = 86° C T J max − PD × Θ JA = 125 − 60 × 0.028 × 33 = 70° C T J max − T A T J max − T A AI DD × Θ JA = 125 − 85 = 40 V 0.028 × 35 AI DD × Θ JA Rev. H | Page 28 of 30 = 125 − 85 0.028 × 33 = 43 V Data Sheet AD5410/AD5420 supply connections. A 24 V TVS is placed on the IOUT connection, and a 36 V TVS is placed on the field supply input. For added protection, clamping diodes are connected from the IOUT pin to the AVDD and GND power supply pins. The recommended external band-pass filter for the AD5700 HART modem includes a 150 kΩ resistor, which limits current to a sufficiently low level to adhere to intrinsic safety requirements. In this case, the input has higher transient voltage protection and should, therefore, not require additional protection circuitry, even in the most demanding of industrial environments. INDUSTRIAL, HART COMPATIBLE ANALOG OUTPUT APPLICATION Many industrial control applications have requirements for accurately controlled current output signals, and the AD5410/ AD5420 are ideal for such applications. Figure 55 shows the AD5410/AD5420 in a circuit design for an output module specifically for use in an industrial control application. The design provides for a HART-enabled current output, with the HART capability provided by the AD5700/AD5700-1 HART modem, the industry’s lowest power and smallest footprint HART-compliant IC modem. For additional space-savings, the AD5700-1 offers a 0.5% precision internal oscillator. The HART_OUT signal from the AD5700 is attenuated and ac-coupled into the CAP2 pin of the AD5420. Further information on this configuration can be found in Application Note AN-1065. An alternative method of coupling the HART signal into the RSET pin (only applicable of the external RSET is used), is available in Circuit Note CN-0270. Use of either configuration results in the AD5700 HART modem output modulating the 4 mA to 20 mA analog current without affecting the dc level of the current. This circuit adheres to the HART physical layer specifications as defined by the HART Communication Foundation. Isolation between the AD5410/AD5420 and the backplane circuitry is provided with the ADuM1400 and ADuM1200 iCoupler digital isolators; further information on iCoupler products is available at www.analog.com. The internally generated digital power supply of the AD5410/AD5420 powers the field side of the digital isolators, removing the need to generate a digital power supply on the field side of the isolation barrier. The AD5410/AD5420 digital supply out-put supplies up to 5 mA, which is more than enough to supply the 2.8 mA requirement of the ADuM1400 and ADuM1200 operating at a logic signal frequency of up to 1 MHz. To reduce the number of isolators required, nonessential signals such as CLEAR can be connected to GND and FAULT, and SDO can be left unconnected, reducing the isolation requirements to just three signals. Doing so, however, disables the fault alert features of the part. The module is powered from a field supply of 24 V. This supplies AVDD directly. For transient overvoltage protection, transient voltage suppressors (TVS) are placed on both the IOUT and field + 24V FIELD SUPPLY 10µF SMAJ36CA 36V 0.1µF BACKPLANE SUPPLY 0.1µF ADuM1400 MICROCONTROLLER DIGITAL OUTPUTS UART INTERFACE DIGITAL INTPUTS VDD1 NC VIA VIB VIC VID GND1 GND1 VDD2 VE2 VOA VOB VOC VOD GND2 GND2 VDD2 VOA VOB GND2 VDD1 VIA VIB GND1 C3 10kΩ DVCC CAP1 DVCC SELECT AVDD AD5410/AD5420 CLEAR LATCH SCLK SDIN IOUT FAULT SDO CAP2 18Ω IOUT GND REFOUT REFIN ADuM1200 C1 2.2nF 0.1µF C2 22nF 0.1µF AVDD ADuM1402 VDD1 VE1 VIA VIB VOC VOC GND1 GND1 VDD2 VE2 VOA VOB VIC VID GND2 GND2 VCC HART_OUT TXD RTS RXD CD AD5700/AD5700-1 REF 1.2MΩ ADC_IP AGND DGND 300pF 1.2MΩ 1µF 150kΩ 150pF Figure 55. AD5410/AD5420 in an Industrial Analog Output Application Rev. H | Page 29 of 30 07027-048 BACKPLANE INTERFACE 0.1µF FIELD GROUND AD5410/AD5420 Data Sheet OUTLINE DIMENSIONS 5.02 5.00 4.95 7.90 7.80 7.70 24 13 4.50 4.40 4.30 3.25 3.20 3.15 EXPOSED PAD (Pins Up) 6.40 BSC 1 12 BOTTOM VIEW TOP VIEW 1.05 1.00 0.80 0.15 0.05 8° 0° 0.20 0.09 0.30 0.19 0.65 BSC SEATING PLANE 0.10 COPLANARITY FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.75 0.60 0.45 061708-A 1.20 MAX COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 56. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters 6.10 6.00 SQ 5.90 0.60 MAX 0.60 MAX PIN 1 INDICATOR 31 30 5.85 5.75 SQ 5.65 PIN 1 INDICATOR 0.50 BSC 40 1 10 21 20 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.20 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.30 0.23 0.18 11 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-01-2012-D TOP VIEW 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTOM VIEW) COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 57. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5410AREZ AD5410AREZ-REEL7 AD5410ACPZ-REEL AD5410ACPZ-REEL7 AD5420AREZ AD5420AREZ-REEL7 AD5420ACPZ-REEL AD5420ACPZ-REEL7 EVAL-AD5420EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Resolution 12 Bits 12 Bits 12 Bits 12 Bits 16 Bits 16 Bits 16 Bits 16 Bits TUE 0.3% Max 0.3% Max 0.3% Max 0.3% Max 0.15% Max 0.15% Max 0.15% Max 0.15% Max Z = RoHS Compliant Part. ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07027-0-4/15(H) Rev. H | Page 30 of 30 Package Description 24-Lead TSSOP_EP 24-Lead TSSOP_EP 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 24-Lead TSSOP_EP 24-Lead TSSOP_EP 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ Evaluation Board Package Option RE-24 RE-24 CP-40-1 CP-40-1 RE-24 RE-24 CP-40-1 CP-40-1