EVAL6472PD Fully integrated stepper motor driver mounting the L6472 in a high power PowerSO package Data brief Description The EVAL6472PD demonstration board is a fully integrated microstepping motor driver. In combination with the STEVAL-PCC009V2 communication board and the SPIN evaluation software, the board allows the user to investigate all the features of the L6472 device. In particular, the board can be used to regulate the L6472 parameters in order to fit application requirements. The 4-layer layout and the PowerSo package allow the top thermal performance to be obtained. The EVAL6472PD supports the daisy chain configuration making it suitable for the evaluation of the L6472 in the multi motor applications. EVAL6472PD Features Voltage range from 8 V to 45 V Phase current up to 3 Ar.m.s. Dual SPI connector (with daisy chain configuration suitable) SW input FLAG and BUSY LED indicators High thermal performance (Rthj-a12 °C/W typical) Suitable for use in combination with the STEVAL-PCC009V2 March 2015 DocID023463 Rev 2 For further information contact your local STMicroelectronics sales office. 1/11 www.st.com Board description EVAL6472PD Board description Table 1. EVAL6472PD specifications Parameter Value Supply voltage (VS) 8 to 45 V Maximum output current (each phase) 3 Ar.m.s. Logic supply voltage (VREG) Externally supplied: 3.3 V Internally supplied: 3 V typical Logic interface voltage (VDD) Externally supplied: 3.3 V or 5 V Internally supplied: VREG Low level logic input voltage 0V High level logic input voltage VDD(1) Operating temperature -25 to +125 °C L6472PD thermal resistance junction to ambient 12 °C/W typical 1. All logic inputs are 5 V tolerant. Figure 1. Jumper and connector location FLAG LED (Red) Application reference area Power supply connector (8 V - 45 V) BUSY LED (Amber) JP1: VDD supply from master SPI connector JP3: Daisy chain termination Master SPI connector Slave SPI connector JP2: VDD to VREG connection ADCIN input OSCIN/OSCOUT connector External switch connector (SW input) Phase A connector Phase B connector AM14850v1 2/11 DocID023463 Rev 2 EVAL6472PD Board description Table 2. Jumper and connector description Name Type Function M1 Power supply Motor supply voltage M2 Power output Bridge A outputs M3 Power output Bridge B outputs CN1 SPI connector Master SPI CN2 SPI connector Slave SPI CN3 NM connector OSCIN and OSCOUT pins CN4 NM connector External switch input TP1 (VS) Test point Motor supply voltage test point TP2 (VDD) Test point Logic interface supply voltage test point TP3 (VREG) Test point Logic supply voltage/L6472 internal regulator test point TP5 (GND) Test point Ground test point TP6 (GND) Test point Ground test point TP8 (STCK) Test point Step-clock input test point TP9 (STBY/RES) Test point Standby/reset input test point TP10 (FLAG) Test point FLAG output test point TP11 (BUSY/SYNC) Test point BUSY/SYNC output test point Table 3. Master SPI connector pinout (J10) Pin number Type 1 Open drain output L6472 BUSY output 2 Open drain output L6472 FLAG output 3 Ground Ground 4 Supply EXT_VDD (can be used as external logic power supply) 5 Digital output 6 Digital input SPI serial clock signal (connected to L6472 CK input) 7 Digital input SPI “Master Out Slave In” signal (connected to L6472 SDI input) 8 Digital input SPI slave select signal (connected to L6472 CS input) 9 Digital input L6472 step-clock input 10 Digital input L6472 standby/reset input Description SPI “Master In Slave Out” signal (connected to L6472 SDO output through daisy chain termination jumper JP2) DocID023463 Rev 2 3/11 11 Board description EVAL6472PD Table 4. Slave SPI connector pinout (J11) 4/11 Pin number Type 1 Open drain output L6472 BUSY output 2 Open drain output L6472 FLAG output 3 Ground Ground 4 Supply EXT_VDD (can be used as external logic power supply) 5 Digital output 6 Digital input SPI serial clock signal (connected to L6472 CK input) 7 Digital input SPI “Master Out Slave In” signal (connected to L6472 SDO output) 8 Digital input SPI slave select signal (connected to L6472 CS input) 9 Digital input L6472 step-clock input 10 Digital input L6472 standby/reset input Description SPI “Master In Slave Out” signal (connected to pin 5 of J10) DocID023463 Rev 2 3 1 VDD 2 1 DocID023463 Rev 2 2 1 FLAG 470 2 1 BUSY 1 2 N.M. CN4 SW C3 10nF/50V L6472PD R8 10K 28 470 DL2 EP R7 E_PAD DL1 TP11 BUSY 3 1 SPI_OUT CN2 2 4 6 8 10 C13 10nF/6.3V SW 19 1 12 R6 VDD CS CK SDI SDO STCK STBY_RES FLAG BUSY_SYNC ADCIN SW DGND TP10 FLAG C12 3.3nF/6.3V 30 26 27 25 32 6 31 29 8 7 OSCOUT OSCIN D1 BAV99 VBOOT PGND PGND AGND D2 BZX585-B3V6 nCS CK SDI SDO ADCIN SW 11 VREG 2 1 3 5 7 9 C8 220nF/16V MISO SDO STCK BUSY CP C11 1nF/6.3V 2 1 10 U1 VDD VREG VDD C10 100pF/6.3V CN3 N.M. STBY TP9 EXT_VDD CK nCS STBY_RESET FLAG 9 24 OSCOUT OSCIN 2 4 6 8 10 14 C9 100pF/6.3V R5 39K SPI_IN CN1 13 R4 39K VDD C1A 100uF/63V STCK 1 3 5 7 9 OUT2B OUT2B OUT1B OUT1B OUT2A OUT2A OUT1A OUT1A 20 21 17 18 35 36 2 3 C2 C5 47uF/6.3V C14 GND TP5 GND C15 TP6 100nF/50V C16 VS C6 100nF/6.3V JP1 + C1 VREG MISO EXT_VDD VREG 1 TP3 100nF/50V 100nF/50V VDD 100nF/50V C4 100nF/6.3V 1 EXT_VDD CK nCS STBY_RESET FLAG VDD TP2 VSB VSB VSB VSB VSA VSA VSA VSA R3 39K + VS OPTION TP8 MISO SDI STCK BUSY 23 22 16 15 34 33 5 4 STCK STBY_RESET FLAG BUSY R2 8K2 TR1 200k TP1 Application reference VS 1 R1 31K6 1 2 VS 1 VS GND VS M1 100uF/63V C7 10uF/6.3V JP3 VDD 2 1 1 2 M3 M2 SDO JP2 1B 2B 1A 2A VREG EVAL6472PD Board description Figure 2. EVAL6472PD schematic 1 1 1 1 AM14851v1 5/11 11 Board description EVAL6472PD Table 5. Bill of material Index Quantity Reference Value Package 1 1 CN1 Pol. IDC male header vertical 10 poles (black) CON-FLAT-5X2-180M 2 1 CN2 Pol. IDC male header vertical 10 poles (gray) CON-FLAT-5X2-180M 3 2 CN3, CN4 N.M STRIP254P-M-2 4 1 C1A 100 µF/63 V CAPE-R10HXX-P5 5 1 C1 100 µF/63 V CAPES-R10HXX 6 4 C2, C14, C15, C16 100 nF/50 V CAPC-0603 7 1 C3 10 nF/50 V CAPC-0603 8 2 C4, C6 100 nF/6.3 V CAPC-0603 9 1 C5 47 µF/6.3 V CAPC-1206 10 1 C7 10 µF/6.3 V CAPC-0805 11 1 C8 220 nF/16 V CAPC-0603 12 2 C9, C10 100 pF/6.3 V CAPC-0603 13 1 C11 1 nF/6.3 V CAPC-0603 14 1 C12 3.3 nF/6.3 V CAPC-0603 15 1 C13 10 nF/6.3 V CAPC-0603 16 1 JP1 LED red LEDC-0805 17 1 DL2 LED amber LEDC-0805 18 1 D1 BAV99 SOT23 19 1 D2 BZX585-B3V6 SOD523 20 1 JP1 Jumper OPEN JP2SO 21 2 JP2, JP3 Jumper CLOSED JP2SO 22 3 M1, M2, M3 Screw connector 2 poles MORSV-508-2P 23 1 R1 31.6 k RESC-0603 24 1 R2 8.2 k RESC-0603 25 3 R3, R4, R5 39 k RESC-0603 26 2 R6, R7 470 RESC-0603 27 1 R8 10 k RESC-0603 28 7 TP1, TP2, TP3, TP8, TP9, TP10, TP11 TPTH-ring-1 mm (red) TPTH-RING-1 MM 29 2 TP5, TP6 TPTH-ring-1 mm (black) TPTH-RING-1 MM 30 1 TR1 200 k TRIMM-100 x 50 x 110 - 64 W 31 1 U1 L6472 POWERSO065P-145X36-36-EP 6/11 DocID023463 Rev 2 EVAL6472PD Board description Figure 3. EVAL6472PD - layout (top layer) AM14853v1 Figure 4. EVAL6472PD - layout (inner layer2) AM14854v1 DocID023463 Rev 2 7/11 11 Board description EVAL6472PD Figure 5. EVAL6472PD - layout (inner layer3) AM14855v1 Figure 6. EVAL6472PD - layout (bottom layer3) AM14856v1 8/11 DocID023463 Rev 2 EVAL6472PD Board description Thermal data Figure 7. Thermal impedance graph Zth 12 10 Zth °C/W 8 6 4 2 0 1 10 100 1000 10000 Time (seconds) AM14857v1 DocID023463 Rev 2 9/11 11 Revision history EVAL6472PD Revision history Table 6. Document revision history 10/11 Date Revision Changes 30-Nov-2012 1 Initial release. 17-Mar-2015 2 Replaced “dSPIN” by “SPIN” in Section : Description on page 1. Removed Figure 3. EVAL6472PD - silkscreen from page 7. Minor modifications throughout document. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID023463 Rev 2 11/11 11