STA333ML Sound TerminalTM 2 channel microless high efficiency digital audio system Target Specification Features ■ Wide supply voltage range (4.5-18 V) ■ 2 x 20 W @ 8 Ω, Vcc = 18 V ■ 3 power output configurations; 2 channels of ternary PWM PowerSSO36 slug down ■ PowerSSO-36 exposed pad package ■ 2 channels of 24-Bit DDX® ■ 100 dB SNR and dynamic range ■ 32 kHz to 48 kHz input sample rates ■ Soft volume update ■ Automatic zero-detect mute ■ Automatic invalid input detect mute ■ 2-channel I2S input data interface ■ Selectable clock input ratio (256 / 364 Fs) ■ Max power correction for lower full power ■ 96 kHz internal processing sample rate, 24-bit precision ■ Thermal overload and short-circuit protection embedded Applications ■ LCD ■ DVD ■ Cradle ■ Digital speaker ■ Wireless speaker cradle Description STA333ML is a single die embedding digital audio processing and high efficiency power amplification, capable of operating without the aid of an external micro controller. The STA333ML is part of the Sound TerminalTM family that provides full digital audio streaming to the speaker offering cost effectiveness, low energy dissipation and sound enrichment. The STA333ML combines a unique 24-bit DDX® digital Class-D ternary modulator together with an extremely low RDSON stereo power Dmos stage. The latter is capable of a total output power of 2 x 20 W with outstanding performances in terms of efficiency (>90 %), THD, SNR and EMI. The microless feature allows the use in low cost applications (cradle, digital speakers, audio terminals) where no micro controller is needed. The serial audio data interface accepts the world wide used I2S format; basic features (for example, oversampling clock, gain, I2S format) can be set using a minimal number of selection pins. STA333ML is self-protected against thermal overload, overcurrent, short circuit and overvoltage conditions. The fault condition is also exported to an external pin (INT-LINE) for specific requirements. Order codes Part number Package Packing STA333ML PowerSSO36 (slug down) Tube STA333ML13TR PowerSSO36 (slug down) Tape and reel February 2007 Rev 1 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. 1/15 www.st.com 15 Contents STA333ML Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 STA333ML Block diagram 1 Block diagram Figure 1. Block diagram Protection current/thermal I2S interface Volume control Channel 1A Power control Logic Channel 1B DDX Channel 2A Regulators Channel 2B PLL Bias 3/15 Pin description 2 STA333ML Pin description Figure 2. Pin connection (Top view) GND_SUB 1 36 VDD_DIG FMT 2 35 GND_DIG TEST_MODE 3 34 GAIN VSS_REG 4 33 ONSEL VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 PLL_GND GND1 12 25 FILTER_PLL OUT1A 13 24 VDD_PLL GND_REG 14 23 PWRDN VDD_REG 15 22 GND_DIG CONFIG 16 21 VDD_DIG N.C. 17 20 N.C. N.C. 18 19 N.C. D05AU1638 Table 1. 4/15 Pin description Pin Type Name Description 1 Gnd GND_SUB 2 I FMT 3 I TEST_MODE 4 I/O VSS 5 I/O VSS_REG Internal Vcc reference 6 O OUT2B Output half bridge 2B 7 Gnd GND2 Power negative supply 8 Power VCC2 Power positive supply 9 O OUT2A Output half bridge 2A 10 O OUT1B Output half bridge 1B 11 Power VCC1 Power positive supply 12 Gnd GND1 Power negative supply Substrate ground 0: I2S format 1: left justified This pin must be connected to GROUND Internal reference at Vcc-3.3 V STA333ML Pin description Table 1. Pin description (continued) Pin Type Name Description 13 I/O OUT1A 14 GND GND_REG Internal ground reference 15 Power VDD_REG Internal 3.3 V reference voltage 16 I CONFIG Output half bridge 1A Paralleled mode command 17 N.C. Not connected 18 N.C. Not connected 19 N.C. Not connected 20 N.C. Not connected 21 Power VDD_DIG Positive supply digital 22 GND GND_DIG Digital ground 23 I PWDN 24 Power VDD_PLL Positive supply for PLL 25 I FILTER_PLL Connection to PLL filter 26 GND GND_PLL Negative supply for PLL 27 I XTI 28 I BICKI I2S serial clock 29 I LRCKI I2S left/right clock 30 I SDI 31 I RESET 32 O INT_LINE 33 I ONSEL 34 I GAIN Gain selector 0: 0 dBFs 1: 24 dBFs 35 GND GND_DIG Digital ground 36 Power VDD_DIG Digital supply Power down PLL input clock, 256 Fs, or 384 Fs I2S serial data channel Reset Fault interrupt Onersampling selector 0: 256 Fs 1: 384 Fs 5/15 Electrical specifications STA333ML 3 Electrical specifications 3.1 Thermal data Table 2. Thermal data Symbol Typ. Max. Unit Thermal resistance junction to case (thermal pad) 1.5 2 °C/W Tsd Thermal shut-down junction temperature 150 °C Tw Thermal warning temperature 130 °C Thsd Thermal shut-down hysteresis 20 °C RTh(j-case) Parameter 3.2 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol VCC Parameter Min. Min. Typ. Max. Unit 20 V 4 V 4 V 0 150 °C -40 150 °C Max. Unit 18.0 V Power supply voltage (VCCxA,VCCxB) VL Logic input interface VDD_DIG Positive supply digital -0.3 Top Operating junction temperature Tstg Storage temperature 3.3 Recommended operating condition Table 4. Recommended operating condition Symbol Parameter Min. Typ. VS Power supply voltage (VCCxA,VCCxB) 4.5 VL Logic Input Interface 2.7 3.3 3.6 V VDD_DIG Positive supply digital 2.7 3.3 3.6 V Tamb Ambient temperature 0 70 °C 6/15 STA333ML Electrical specifications 3.4 Electrical characteristics Table 5. Electrical characteristics (VCC = 18 V,VDD_DIG=3.3 V fsw = 384 kHz, Tamb = 25 °C, RL = 8 Ω unless otherwise specified) Symbol Po Parameter Conditions Min. Typ. THD = 1 % 16 THD = 10% 20 180 Max. Output power BTL Unit W RdsON Power Pchannel/Nchannel MOSFET (Total Bridge) ld=1A ldss Power Pchannel/Nchannel leakage Vcc = 18V gP Power Pchannel RdsON Matching ld=1A 95 % gN Power Nchannel RdsON Matching ld=1A 95 % ILDT Low current dead time (static) Resistive load Figure 3. 5 10 ns IHDT High current dead time (dynamic) @lload = 1.5 A (Figure 5) 10 20 ns tr Rise time Resistive load Figure 3. 8 10 ns tf Fall time Resistive load Figure 3. 8 10 ns 18 V VCC Icc Supply voltage operating voltage 4.5 250 mΩ 10 µA Supply current from Vcc in power down PWRDN = 0 0.1 mA Supply current from Vcc in operation PCM Input signal = -60 dBFS. Switching frequency = 384KHz No LC filters 30 mA 80 mA Supply current DDX processing Internal clock = 49.152 MHz (reference only) Ilim Overcurrent limit Nonlinear output 2.2 3.5 4.3 A Isc short circuit protection Hi-Z output 2.7 3.8 5.0 A 3.5 4.3 V 30 60 ns UVL Under voltage protection threshold tmin Output minimum pulse width DR Dynamic range SNR No load Signal to noise ratio A - weighted THD+N Total harmonic distortion + noise Po = 1 W, f = 1 kHz PSRR Power supply rejection ratio DDX stereo, <5 kHz Vripple = 1 VRMS Audio input = dither only 20 100 dB 94 dB 0.05 80 0.2 % dB 7/15 Electrical specifications Table 5. Electrical characteristics (continued) (VCC = 18 V,VDD_DIG=3.3 V fsw = 384 kHz, Tamb = 25 °C, RL = 8 Ω unless otherwise specified) Symbol XTALK η STA333ML Parameter Conditions Typ. Max. Unit Crosstalk DDX stereo, <5 kHz One CH driven @ 1 W other channel measured 80 dB Peak efficiency, DDX mode Po = 2 x 20 W, 8 Ω 90 % Table 6. Functional pin status Pin name 8/15 Min. Pin number Logic value IC status PWRDN 23 0 Low absorption PWRDN 23 1 Normal operation STA333ML 4 Testing Testing Figure 3. Resistive load OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd Figure 4. D03AU1458 Test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 OUTA INA L67 22µ Q3 C69 470nF M64 DTin(B) OUTB INB L68 22µ Iout=4A Lout = 1.5 A M57 DTout(B) Rload=8Ω Iout=4A Lout = 1.5 A C71 470nF C70 470nF Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure M63 D03AU1517 9/15 Functional description STA333ML 5 Functional description 5.1 Serial audio interface protocols Figure 5. I2S Lrclki Bicki Sdi Figure 6. 11 2 33 n-1 n 1 2 3 n-1 n Left justified Lrclki/ Lrclko Biclki/ Biclko Sdatai/ Sdatao 5.2 1 2 3 n-1 n 1 2 3 n-1 n Fault detect recovery bypass The on-chip STA333ML power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tristate output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This sequence is repeated for as long as the fault exists. 10/15 STA333ML 5.3 Functional description Zero-detect mute enable If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. If so the channel is muted. 11/15 Package thermal characteristics 6 STA333ML Package thermal characteristics A thermal resistance of 25 °C per Watt can be achieved using a ground copper area of 3 x 3 cm, and using 16 vias, on the PCB (see Figure 7). The amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA333ML is 3 W. This gives, with the suggested board copper area, a maximum ∆Tj of 75 °C. This gives a safety margin before the thermal protection intervention is invoked (Tj=150 °C) in consumer environments where a 50 °C is the maximum ambient temperature. Figure 7. 12/15 Thermal characteristic STA333ML Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 8. PowerSSO36 exposed pad mechanical data and package dimensions DIM. MIN. 2.15 2.15 0 0.18 0.23 10.10 A A2 a1 b c D (1) mm TYP. 7.4 E (1) e e3 F G G1 H h k L M N O Q S T U X Y MAX. 2.47 2.40 0.075 0.36 0.32 10.50 MIN. 0.084 0.084 0 0.007 0.009 0.398 7.6 0.291 0.5 8.5 2.3 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 OUTLINE AND MECHANICAL DATA 0.299 0.019 0.335 0.090 0.10 0.06 10.50 0.40 10.10 0.004 0.002 0.413 0.016 0.398 5˚ 5˚ 0.55 0.90 0.022 4.3 0.035 0.169 10˚ 10˚ 1.2 0.8 2.9 3.65 1.0 0.047 0.031 0.114 0.144 0.039 4.1 6.5 4.7 7.3 0.161 0.256 PowerSSO-36 (exposed pad) 0.185 0.287 A A2 (1) "D” and “E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006”) hx45 Gauge plane 0.25 c G LEAD COPLANARITY A D stand-off a1 Y k e T L E H X O S Q F 7 Package information U BOTTOM VIEW B 0.1 M A B b e3 7587131 A 13/15 Revision history 8 STA333ML Revision history Table 7. 14/15 Document revision history Date Revision 1-Feb-2007 1 Changes Initial release. STA333ML Please Read Carefully: Information in this document is provided solely in connection with ST products. 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