TDA7718B 3 band car audio processor Datasheet - production data Treble – 2nd order frequency response (10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) – Center frequency programmable in 4 steps (10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) – -15 dB to 15 dB with 1 dB resolution *$3*36 TSSOP28 Features Input multiplexer – QD1: quasi-differential stereo inputs – SE1: stereo single-ended input – SE2: stereo single-ended input – SE3: stereo single-ended input – FD full-differential or quasi-differential input Loudness – 2nd order frequency response – Programmable center frequency (400 Hz / 800 Hz / 2400 Hz) – 15 dB with 1 dB steps – Selectable high frequency boost – Selectable flat-mode (constant attenuation) Volume – +23 dB to -31 dB with 1 dB step resolution – Soft-step control with programmable blend times Bass – 2nd order frequency response – Center frequency programmable in 4 steps (60 Hz / 80 Hz / 100 Hz / 200 Hz) – Q programmable 1.0/1.25/1.5/2.0 – DC gain programmable – -15 dB to 15 dB range with 1 dB resolution Middle – 2nd order frequency response – Center frequency programmable in 4 steps (500 Hz / 1 kHz / 1.5 kHz / 2.5 kHz) – Q programmable 0.75/1.0/1.25 – -15 dB to 15 dB range with 1 dB resolution September 2013 This is information on a product in full production. Speaker – 4 independent soft-step speaker controls – +15 dB to -79 dB with 1 dB steps – Direct mute Subwoofer – 2nd order low pass filter with programmable cut off frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz) – 2 independent soft-step level control, +15 dB to –79 dB with 1 dB steps Mute functions – Direct mute – Digitally controlled soft-mute with 4 programmable mute-times (0.48 ms/0.96 ms/8 ms/16 ms) Offset detection – Offset voltage detection circuit for on-board power amplifier failure diagnosis Description The TDA7718B is a high performance signal processor specifically designed for car radio applications. The device includes a high performance audioprocessor with fully integrated audio filters and new soft-step architecture. The digital control allows programming in a wide range of filter characteristics. Table 1. Device summary Order code Package Packing TDA7718B TSSOP28 Tube TDA7718BTR TSSOP28 Tape and reel DocID18305 Rev 3 1/40 www.st.com 1 Contents TDA7718B Contents 1 Block circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin connection and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description of the audioprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.1.1 Quasi-differential stereo input (QD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2 Single-ended stereo input (SE1, SE2, SE3) . . . . . . . . . . . . . . . . . . . . . 13 4.1.3 Full-differential or quasi-differential stereo input (FD/QD2) . . . . . . . . . . 13 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.1 Loudness attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 Peak frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.3 High frequency boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.4 Flat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Soft-mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Soft-step volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 4.7 2/40 Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5.1 Bass attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5.2 Bass center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5.3 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5.4 DC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Middle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6.1 Middle attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.2 Middle center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.3 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DocID18305 Rev 3 TDA7718B 5 Contents 4.7.1 Treble attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7.2 Center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 Subwoofer filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 Soft-step control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.10 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.11 Audioprocessor testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.12 Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 I2C bus electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 5.2.1 Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.2 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID18305 Rev 3 3/40 List of tables TDA7718B List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/40 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C bus electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Main selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Soft-mute / others (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Soft-step I (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Soft-step II / DC detector (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loudness (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Volume / output gain (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Treble filter (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Middle filter (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bass filter (11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Subwoofer / middle / bass (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Testing audio processor 1 (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Testing audio processor 2 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Testing audio processor 3 (21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID18305 Rev 3 TDA7718B List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FD/QD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Loudness attenuation @ fP = 400 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness center frequencies @ attn. = 15 dB.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness attenuation, fc = 2.4 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Soft-mute timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bass control @ fC = 80 Hz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bass center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass quality factors @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Middle control @ fC = 1 kHz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle quality factors @ gain = 14 dB, fC = 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble control @ fC = 17.5 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble center frequencies @ gain = 14 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Subwoofer cut frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC offset detection circuit (simplified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C bus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TSSOP28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DocID18305 Rev 3 5/40 6/40 6(/ DocID18305 Rev 3 )'54'5 )'54'* )'/4'* )'/4'/ 4'5 4'* 4'/ 6(5 6(/ 6(5 6(/ 9&& *1' 6833/< &5() 62)7 087( 92/80( ',*,7$/ &21752/ 75(%/( %$66 6&/ 6'$ ,&%86 68%:22)(5 0,''/( :,1B,1 :,1B7& '&2IIVHW 'HWHFWRU '&B(55 0212)$'(5 0212)$'(5 2876:5 2876:/ 28755 287/5 0212)$'(5 0212)$'(5 2875) 287/) 0212)$'(5 0212)$'(5 1 6(5 /28'1(66 087( Block circuit diagram TDA7718B Block circuit diagram Figure 1. Block circuit diagram *$3*36 0$,1,138708/7,3/(;(5 TDA7718B Pin connection and pin description 2 Pin connection and pin description 2.1 Pin connection Figure 2. Pin connection (top view) 6(/ :LQLQ 6(5 '&(UU 6(/ 6'$ 6(5 6&/ 6(/ 9&& 6(5 087( 4'/ :,17& 4'* 287/) 4'5 287/5 )'/4'/ 28755 )'/4'* 2875) )'54'* 2876:/ )'54'5 2876:5 &5() *1' *$3*36 2.2 Pin description Table 2. Pin description No. Pin name Description 1 SE1L Single-end input left I 2 SE1R Single-end input right I 3 SE2L Single-end input left I 4 SE2R Single-end input right I 5 SE3L Single-end input left I 6 SE3R Single-end input right I 7 QD1L quasi-differential stereo inputs left I 8 QD1G quasi-differential stereo inputs common I 9 QD1R quasi-differential stereo inputs right I 10 FD1L+/QD2L Full differential + input left or quasi-differential left I DocID18305 Rev 3 I/O 7/40 Pin connection and pin description TDA7718B Table 2. Pin description (continued) No. Pin name Description I/O 11 FD1L-/QD2G Full differential - input left or quasi-differential ground I 12 FD1R-/QD2G Full differential - input right or quasi-differential ground I 13 FD1R+/QD2R Full differential + input right or quasi-differential right I 14 CREF Reference capacitor O 15 GND Ground S 16 OUTSWR Subwoofer right output O 17 OUTSWL Subwoofer left output O 18 OUTRF Front right output O 19 OUTRR Rear right output O 20 OUTLR Rear left output O 21 OUTLF Front left output O 22 WinTC DC offset detector filter output O 23 MUTE External mute pin I 24 VCC Supply S SCL 2C I bus clock I 26 SDA I2C bus data I/O 27 DC_ERR 28 WIN_IN 25 Note: 8/40 DC offset detector output O DC offset detector input I The L & R channels may be swapped as per the user's wishes making use of proper connections to the device pins, with no impact on electrical performance. Software control has to take into account the external routing and be designed accordingly. DocID18305 Rev 3 TDA7718B Electrical specifications 3 Electrical specifications 3.1 Thermal data Table 3. Thermal data Symbol Rth-j amb 3.2 Description Value Unit 114 °C/W Value Unit 10.5 V 7 V Thermal resistance junction-to-ambient Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Operating supply voltage VS Vin_max 3.3 Parameter Maximum voltage for signal input pins Tamb Operating ambient temperature -40 to 85 °C Tstg Storage temperature range -55 to 150 °C Electrical characteristics VS = 8.5 V; Tamb= 25 °C; RL= 10 k; all gains = 0 dB; f = 1 kHz; unless otherwise specified Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply Vs Supply voltage - 7.5 8.5 10 V Is Supply current - 23 29 35 mA Input selector Rin Input resistance All single ended inputs 70 100 130 k VCL Clipping level Input gain = 0 dB 2 - - VRMS SIN Input separation - - 95 - dB Differential stereo inputs Input resistance Differential 70 100 - k CMRR Common mode rejection ratio for main source VCM = 1 VRMS @ 1 kHz 44 60 - dB VCM = 1 VRMS @ 10 kHz 44 60 - dB eNo Output noise @ speaker outputs - 12 22 µV Rin 20 Hz - 20 kHz, A-weighted; all stages 0 dB DocID18305 Rev 3 9/40 Electrical specifications TDA7718B Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Loudness control AMAX Max attenuation - 14 15 16 dB ASTEP Step resolution - 0.5 1 1.5 dB fP1 - 400 - Hz fP2 - 800 - Hz fP3 - 2400 - Hz 22 23 24 dB fPeak Peak frequency Volume control GMAX Max gain - AMAX Max attenuation - - -31 -30 dB ASTEP Step resolution - 0.5 1 1.5 dB EA Attenuation set error - -0.75 0 +0.75 dB ET Tracking error - - - 2 dB Adjacent attenuation steps -3 0.1 3 mV From 0 dB to GMIN -5 0.5 5 mV - 80 100 - dB VDC DC steps Soft-mute AMUTE TD Mute attenuation Delay time T1 0.35 0.48 0.65 ms T2 0.7 0.96 1.3 ms T3 5.6 7.6 9.6 ms T4 12.3 15.3 18.3 ms Low threshold for SM pin - - - 1 V VTH High High threshold for SM pin - 2.5 - - V VTH Low RPU Internal pull-up resistor - 32 45 58 k VPU Internal pull-up voltage - 3 3.3 3.6 V fC1 - 60 - Hz fC2 - 80 - Hz fC3 - 100 - Hz Bass control Fc QBASS Center frequency Quality factor fC4 - 200 - Hz Q1 - 1 - - Q2 - 1.25 - - Q3 - 1.5 - - - 2 - - - ±14 ±15 ±16 dB - 0.5 1 1.5 dB DC = off -1 0 +1 dB ±4.3 ±4.7 ±5.1 dB Q4 CRANGE Control range ASTEP Step resolution DCGAIN Bass-DC-gain 10/40 DC = on, gain = ±15 dB DocID18305 Rev 3 TDA7718B Electrical specifications Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit - ±14 ±15 ±16 dB - 0.5 1 1.5 dB fC1 - 500 - Hz fC2 - 1 - kHz fC3 - 1.5 - kHz fC4 - 2.5 - kHz Q1 - 0.75 - - Q2 - 1 - - Q3 - 1.25 - - - ±14 ±15 ±16 dB - Middle control CRANGE Control range ASTEP fc Step resolution Center frequency QMIDDLE Quality factor Treble control CRANGE Clipping level ASTEP fc Step resolution Center frequency 0.5 1 1.5 dB fC1 - 10 - kHz fC2 - 12.5 - kHz fC3 - 15 - kHz fC4 - 17.5 - kHz Speaker attenuators GMAX Max gain - 14 15 16 dB AMAX Max attenuation - - -79 -74 dB ASTEP Step resolution - 0.5 1 1.5 dB AMUTE Mute attenuation - 80 90 - dB Attenuation set error - - - 2 dB DC steps Adjacent attenuation steps - 0.1 5 mV d = 0.3 %; byte8_D6=1 2 - - VRMS 2.2 - - VRMS - - 20 100 W EE VDC Audio outputs VCL ROUT Clipping level Output impedance d = 1 %; byte8_D6=0 RL Output load resistance - 2 - - k CL Output load capacitor - - - 10 nF DC voltage level - 3.8 4.0 4.2 V fLP1 - 55 - Hz fLP2 - 85 - Hz fLP3 - 120 - Hz fLP4 - 160 - Hz VDC Subwoofer lowpass fLP Lowpass corner frequency DocID18305 Rev 3 11/40 Electrical specifications TDA7718B Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit V1 ±10 ±25 ±40 mV V2 ±30 ±50 ±70 mV V3 ±50 ±75 ±100 mV V4 DC offset detection circuit Vth tsp Zero comp. window size Max rejected spike length ±70 ±100 ±130 mV - 2 11 30 µs - 5 22 50 µs - 10 33 70 µs - 15 44 90 µs ICHDCErr DCErr charge current - 2 5 8 µA IDISDCErr DCErr discharge current - 4 5 9 mA VOutH DCErr high voltage - 3 3.3 3.6 V VOutL DCErr low voltage - - 100 300 mV BW=20 Hz to 20 kHz AWeighted, all gain = 0 dB - 12 22 µV BW=20 Hz - 20 kHz AWeighted, Output muted - 7 12 µV 98 104 - dB General eNO Output noise Signal to noise ratio all gain = 0 dB, A-weighted; Vo = 2 VRMS D Distortion VIN =1 VRMS; all stages 0 dB - 0.01 0.1 % SC Channel separation left/right - - 90 - dB S/N 12/40 DocID18305 Rev 3 TDA7718B Description of the audioprocessor 4 Description of the audioprocessor 4.1 Input stages One quasi-differential stereo input, one full-differential/quasi-differential stereo input and three single-ended inputs are available. 4.1.1 Quasi-differential stereo input (QD1) The QD input is implemented as a buffered quasi-differential stereo stage with 100 k inputimpedance at each input. There is -3 dB attenuation at QD input stage. 4.1.2 Single-ended stereo input (SE1, SE2, SE3) The input-impedance at each input is 100 k and the attenuation is fixed to -3 dB for incoming signals. 4.1.3 Full-differential or quasi-differential stereo input (FD/QD2) This device provides a full-differential stereo input stage (FD) or 2nd quasi-differential stereo input stage. The full differential is a buffered full-differential stereo stage with 100 k inputimpedance at each input. When using as QD2 application, it needs to connect the two QD2G pins together from external and the input impedance at QDG becomes 50 k. There is -3 dB attenuation at the input stage. Figure 3 shows the block diagram of this input stage. DocID18305 Rev 3 13/40 Description of the audioprocessor TDA7718B Figure 3. FD/QD block diagram G% )'/B4'/ )' 4' )'/B4'/* )'5B4'5* 4'287/ G% )'5B4'5 4'2875 )' 4' *$3*36 4.2 Loudness There are four parameters programmable in the loudness stage. 14/40 DocID18305 Rev 3 TDA7718B 4.2.1 Description of the audioprocessor Loudness attenuation Figure 4 shows the attenuation as a function of frequency at fP = 400 Hz. Figure 4. Loudness attenuation @ fP = 400 Hz. -AGNITUDE;D"= *$3*36 Peak frequency Figure 5 shows the four possible peak-frequencies at 400, 800 and 2400 Hz. Figure 5. Loudness center frequencies @ attn. = 15 dB. -AGNITUDE;D"= 4.2.2 &REQUENCY;(Z= &REQUENCY;(Z= DocID18305 Rev 3 *$3*36 15/40 Description of the audioprocessor 4.2.3 TDA7718B High frequency boost Figure 6 shows the different Loudness shapes in low and high frequency boost. Figure 6. Loudness attenuation, fc = 2.4 kHz -AGNITUDE;D"= &REQUENCY;(Z= 4.2.4 *$3*36 Flat mode In flat mode the loudness stage works as a 0 dB to -15 dB attenuator. 4.3 Soft-mute The digitally controlled soft-mute stage allows muting/demuting the signal with a I2C bus programmable slope. The mute process can either be activated by the soft-mute pin or by the I2C bus. This slope is realized in a special S-shaped curve to mute slow in the critical regions (see Figure 7). For timing purposes the bit 0 of the I2C bus output register is set to 1 from the start of muting until the end of demuting. Figure 7. Soft-mute timing %84 -54% 3)'.!, 2%& 3)'.!, )#"53 /54 4IME Note: 16/40 *$3*36 Please notice that a started mute-action is always terminated and could not be interrupted by a change of the mute –signal. DocID18305 Rev 3 TDA7718B 4.4 Description of the audioprocessor Soft-step volume When the volume-level is changed audible clicks could appear at the output. The root cause of those clicks could either be a DC-offset before the volume-stage or the sudden change of the envelope of the audio signal. With the soft-step-feature both kinds of clicks could be reduced to a minimum and are no more audible. The blend-time from one step to the next is programmable as 5 ms or 10 ms. The soft-step control is described in detail in Chapter 4.9. 4.5 Bass There are four parameters programmable in the bass stage: Bass attenuation Figure 8 shows the attenuation as a function of frequency at a center frequency of 80 Hz. Figure 8. Bass control @ fC = 80 Hz, Q = 1 -AGNITUDE;D"= 4.5.1 &REQUENCY;(Z= *$3*36 DocID18305 Rev 3 17/40 Description of the audioprocessor 4.5.2 TDA7718B Bass center frequency Figure 9 shows the four possible center frequencies 60, 80, 100 and 200 Hz. Figure 9. Bass center frequencies @ gain = 14 dB, Q = 1 -AGNITUDE;D"= &REQUENCY;(Z= *$3*36 4.5.3 Quality factors Figure 10 shows the four possible quality factors 1, 1.25, 1.5 and 2. Figure 10. Bass quality factors @ gain = 14 dB, fC = 80 Hz -AGNITUDE;D"= &REQUENCY;(Z= *$3*36 18/40 DocID18305 Rev 3 TDA7718B 4.5.4 Description of the audioprocessor DC mode In this mode the DC-gain is increased by 4.4 dB. In addition the programmed center frequency and quality factor is decreased by 25 % which can be used to reach alternative center frequencies or quality factors. Figure 11. Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz -AGNITUDE;D"= &REQUENCY;(Z= *$3*36 1. The center frequency, Q and DC-mode can be set fully independently. 4.6 Middle There are three parameters programmable in the middle stage: DocID18305 Rev 3 19/40 Description of the audioprocessor 4.6.1 TDA7718B Middle attenuation Figure 12 shows the attenuation as a function of frequency at a center frequency of 1 kHz. Figure 12. Middle control @ fC = 1 kHz, Q = 1 -AGNITUDE;D"= &REQUENCY;(Z= 4.6.2 *$3*36 Middle center frequency Figure 13 shows the four possible center frequencies 500 Hz, 1 kHz, 1.5 kHz and 2.5 kHz. Figure 13. Middle center frequencies @ gain = 14 dB, Q = 1 -AGNITUDE;D"= &REQUENCY;(Z= 20/40 DocID18305 Rev 3 *$3*36 TDA7718B 4.6.3 Description of the audioprocessor Quality factors Figure 14 shows the three possible quality factors 0.75, 1 and 1.25. Figure 14. Middle quality factors @ gain = 14 dB, fC = 1 kHz -AGNITUDE;D"= &REQUENCY;(Z= 4.7 *$3*36 Treble There are two parameters programmable in the treble stage: Treble attenuation Figure 15 shows the attenuation as a function of frequency at a center frequency of 17.5 kHz. Figure 15. Treble control @ fC = 17.5 kHz. -AGNITUDE;D"= 4.7.1 &REQUENCY;(Z= *$3*36 DocID18305 Rev 3 21/40 Description of the audioprocessor 4.7.2 TDA7718B Center frequency Figure 16 shows the four possible center frequencies 10 k, 12.5 k, 15 k and 17.5 kHz. Figure 16. Treble center frequencies @ gain = 14 dB -AGNITUDE;D"= &REQUENCY;(Z= *$3*36 4.8 Subwoofer filter The subwoofer lowpass filter has Butterworth characteristics with programmable cut-off frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz). The output phase can be selected between 0 deg and 180 deg. The input of subwoofer takes signal from bass filter output or output of input mux. Figure 17. Subwoofer cut frequencies -AGNITUDE;D"= &REQUENCY;(Z= 22/40 DocID18305 Rev 3 *$3*36 TDA7718B 4.9 Description of the audioprocessor Soft-step control In this device, the soft-step function is available for volume, speaker, loudness, treble, middle and bass block. With soft-step function, the audible noise of DC offset or the sudden change of signal can be avoided when adjusting gain setting of the block. For each block, the soft-step function is controlled by soft-step soft-step on/off control bit in the control table. The soft-step transient time selection (5 ms or 10 ms) is common for all blocks and it is controlled by soft-step time control bit. The soft-step operation of all blocks has a common centralized control. In this case, a new soft-step operation can not be started before the completion previous soft-step. There are two different modes to activate the soft-step operation. The soft-step operation can be started right after I2C data sending, or the soft-step can be activated in parallel after data sending of several different blocks. The two modes are controlled by the ‘act bit’ (it is normally bit7 of the byte.) of each byte. When act bit is ‘0’, which means action, the soft-step is activated right after the date byte is sent. When the act bit is ‘1’, which means wait, the block goes to wait for soft-step status. In this case, the block will wait for some other block to activate the operation. The soft-step operation of all blocks in wait status will be done together with the block which activate the soft-step. With this mode, all specific blocks can do the soft-step in parallel. This avoids waiting when the soft-step is operated one by one. Chip Addr Sub Addr 0xxxxxxx | Soft-step start here Chip Addr Sub Addr 1xxxxxxx 1xxxxxxx ...... 0xxxxxxx | Soft-step start here for all DocID18305 Rev 3 23/40 Description of the audioprocessor 4.10 TDA7718B DC offset detector Using the DC offset detection circuit (Figure 18) an offset voltage difference between the audio power amplifier and the APR's Front and Rear outputs can be detected, preventing serious damage to the loudspeakers. The circuit compares whether the signal crosses the zero level inside the audio power at the same time as in the speaker cell. The output of the zero-window-comparator of the power amplifier must be connected with the WinIn-input of the APR. The WinIn-input has an 50k internal pull-up resistor connected to 3.3 V. It is recommended to drive this pin with open-collector outputs only. To compensate for errors at low frequencies the WinTC-pin are implemented, with external capacitors introducing the same delay = 7.5 k * Cext as the AC-coupling between the APR and the power amplifier introduces. For the zero window comparators, the time constant for spike rejection as well as the threshold are programmable. For electrical characteristics see Chapter 3 on page 9. A low-active DC-offset error signal appears at the DCErr output if the next conditions are both true: a) Front and rear outputs are inside zero crossing windows. b) The Input voltage VWinIn is logic low whenever at least one output of the power amplifier is outside the zero crossing windows. After power-on, the external attached capacitor is rapidly charged (fast-charge) to overcome a false indication. Figure 18. DC offset detection circuit (simplified) =HUR:LQGRZ&RPS 287/) 9WK ,Q=HUR 9WK± N =HUR:LQGRZ&RPS 9WK ,Q=HUR 9WK± 2875) N + DOOLQVLGH]HURZLQGRZ '&HUU WR3 :LQ7& N &H[W 9WK =HUR:LQGRZ&RPS P &H[W 287/5 9WK ,Q=HUR 9WK± 6SLNHUHMHFWLRQ N =HUR:LQGRZ&RPS 28755 :LQLQ 9WK ,Q=HUR 9WK± *$3*36 24/40 DocID18305 Rev 3 TDA7718B 4.11 Description of the audioprocessor Audioprocessor testing In the test mode, which can be activated by setting bit D7 of the I2C subaddress byte and bit D0 of the testing audioprocessor byte, several internal signals are available at the SE1L pin. In this mode, the input resistance of 100 k is disconnected from the pin. Internal signals available for testing are listed in the data-byte specification. Figure 19. Application schematic Q ) 6(/ :Q ,Q 6(5 '&(UU 6(/ 6'$ 6(5 6&/ 6(/ 9&& 6(5 087( Q ) Q ) $XGLR 3OD\HUV Q ) 0LFURSURFHVVRU Q ) Q) Q ) Q) N7 4'/ ) :,17& Q) N7 ) Q) ([WHUQDO 6LJQDO 6RXUFHV 76623 4'* 287/) 4'5 287/ 5 )'/4'/ 28755 Q) N7 N7 N7 N7 ) Q) Q) )'/ 4'* 2875) )'54'* 2876:/ )'54'5 2876:5 3RZHU $PSOLHUV Q) X Q) &5() *1' X) *$3*36 4.12 Application note Above application schematic shows a proposal typical application that QD1 and FD/QD2 is used as external signal sources. To limit the leakage current from signal source a 1 k resistor is recommended to put between de-coupling capacitor and pin if the output impedance of external signal source is less than 1 k. It's guaranteed that all input pins (pin 1~13) will not be broken even if 2Vrms input signal is applied to the pins when CSP is power off. DocID18305 Rev 3 25/40 I2C bus specification TDA7718B 5 I2C bus specification 5.1 Interface protocol The interface protocol comprises: a start condition (S) a chip address byte (the LSB determines read/write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P) the max. clock speed is 400 kbit/s 3.3 V logic compatible Figure 20. I2C bus interface protocol 6&/ 6'$ ' ' ' ' ' ' ' ' , 6$ 6$ 6$ 6$ 6$ 6 FKLSDGGUHVV $&. VXEDGGUHVV $&. ' ' ' ' ' ' ' ' GDWD GDWDQ *$3*36 S = Start ACK = Acknowledge 5.2 I2C bus electrical characteristics Table 6. I2C bus electrical characteristics Symbol 26/40 Parameter Min Max Unit - 400 kHz fSCL SCL clock frequency VIH High level input voltage 2.4 - V VIL Low level input voltage - 0.8 V tHD,STA Hold time for START 0.6 - µs tSU,STO Setup time for STOP 0.6 - µs tLOW Low period for SCL clock 1.3 - µs tHIGH High period for SCL clock 0.6 - µs tF Fall time for SCL/SDA - 300 ns tR Rise time for SCL/SDA - 300 ns tHD,DAT Data hold time 0 - ns tSU,DAT Data setup time 100 - ns DocID18305 Rev 3 I2C bus specification TDA7718B Figure 21. I2C bus data 3$! W /2: 3#, W +''$7 W5 W +,*+ W +'67$ W) W 68'$7 W 68672 *$3*36 5.2.1 S Receive mode 1 0 0 0 1 0 0 AC K R/W TS X AI A4 A3 A2 A1 A0 ACK DAT A ACK P S = Start R/W = "0" -> Receive Mode (Chip can be programmed by µP) "1" -> Transmission Mode (Data could be received by µP) ACK = Acknowledge P = Stop TS = Testing mode AI = Auto increment 5.2.2 S Transmission mode 1 0 0 0 1 0 0 R/W ACK X X X X X X BZ SM ACK P SM = Soft-mute activated for main channel BZ = Soft-step Busy (‘0’ = Busy) X = Not used The transmitted data is automatic updated after each ACK. Transmission can be repeated without new chip address. DocID18305 Rev 3 27/40 I2C bus specification 5.2.3 TDA7718B Reset condition A Power-On-Reset is invoked if the supply voltage is below than 3.5 V. After that the registers are initialized to the default data written in following tables. Table 7. Subaddress (receive mode) MSB LSB Function I2 I1 I0 A4 A3 A2 A1 A0 0 1 - - - - - - - Testing mode Off On - x - - - - - - Not used - - 0 1 - - - - - Auto increment mode Off On - - - 0 0 0 0 0 Main selector - - - 0 0 0 0 1 Not used - - - 0 0 0 1 0 Not used - - - 0 0 0 1 1 Not used - - - 0 0 1 0 0 Soft-mute / others - - - 0 0 1 0 1 Soft-step I - - - 0 0 1 1 0 Soft-step II / DC-detector - - - 0 0 1 1 1 Loudness - - - 0 1 0 0 0 Volume / output gain - - - 0 1 0 0 1 Treble - - - 0 1 0 1 0 Middle - - - 0 1 0 1 1 Bass - - - 0 1 1 0 0 Subwoofer / middle / bass - - - 0 1 1 0 1 Speaker attenuator left front - - - 0 1 1 1 0 Speaker attenuator right front - - - 0 1 1 1 1 Speaker attenuator left rear - - - 1 0 0 0 0 Speaker attenuator right rear - - - 1 0 0 0 1 Subwoofer attenuator left - - - 1 0 0 1 0 Subwoofer attenuator right - - - 1 0 0 1 1 Testing audio processor 1 - - - 1 0 1 0 0 Testing audio processor 2 - - - 1 0 1 0 1 Testing audio processor 3 28/40 DocID18305 Rev 3 I2C bus specification TDA7718B 5.3 Data byte specification Table 8. Main selector (0) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Main source selector SE1 SE3 QD1 FD/ QD2 SE2 Mute Mute Mute - - - - - - - - - 0 1 - - - FD / QD2 selection FD QD2 - - - 0 1 - - - - Main source input gain select 0 dB 3 dB - - 0 1 - - - - - Subwoofer flat Off On x x - - - - - - Not used Not used (1-3) DocID18305 Rev 3 29/40 I2C bus specification TDA7718B Table 9. Soft-mute / others (4) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Pin influence for mute Pin and IIC IIC 0 0 1 1 0 1 0 1 - - Soft-mute time 0.48 ms 0.96 ms 7.68 ms 15.36 ms Soft-mute On Off - - - - - - - 0 1 - - - - Subwoofer input source Input mux Bass output - - 0 1 - - - - - Subwoofer enable (OUTSWL & OUTSWR) On Off - 0 1 - - - - - - Fast charge On Off 0 1 - - - - - - - Anti-alias filter On Off (bypass) 30/40 DocID18305 Rev 3 I2C bus specification TDA7718B Table 10. Soft-step I (5) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Volume soft-step On Off - - - - - 0 1 - - Treble soft-step On Off Loudness soft-step On Off - - - - 0 1 - - - Middle soft-step On Off - - - 0 1 - - - - Bass soft-step On Off - - 0 1 - - - - - Speaker LF soft-step On Off - 0 1 - - - - - - Speaker RF soft-step On Off - Speaker LR soft-step On Off 0 1 - - - - - - DocID18305 Rev 3 31/40 I2C bus specification TDA7718B Table 11. Soft-step II / DC detector (6) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Subwoofer left soft-step On Off - - - - - 0 1 - - Subwoofer right soft-step On Off - Soft-step time 5 ms 10 ms - Zero-comparator window size ±100 mV ±75 mV ±50 mV ±25 mV - Spike rejection time constant 11 µs 22 µs 33 µs 44 µs - - 0 0 1 1 32/40 - - 0 1 0 1 - - 0 0 1 1 0 1 0 1 - - 0 1 - - - - - - - - DocID18305 Rev 3 Speaker RR soft-step On Off I2C bus specification TDA7718B Table 12. Loudness (7) MSB D7 - - - 0 1 LSB D6 - - 0 1 - D5 D4 - - 0 0 1 1 0 1 0 1 - - - - D3 D2 D1 D0 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 - - - - - - - - - Function Attenuation 0 dB -1 dB : -14 dB -15 dB - Center frequency Flat 400 Hz 800 Hz 2400 Hz - High boost On Off - Soft-step action Act Wait Table 13. Volume / output gain (8) MSB D7 - - 0 1 LSB D6 - D5 D4 D3 D2 D1 D0 0 0 : 0 0 : 0 0 : 0 1 : 1 : 1 0 0 : 0 1 : 1 1 : 1 0 : 0 : 1 0 0 : 1 0 : 0 1 : 1 0 : 1 : 1 0 0 : 1 0 : 1 0 : 1 0 : 1 : 1 0 0 : 1 0 : 1 0 : 1 0 : 1 : 1 0 1 : 1 0 : 1 0 : 1 0 : 1 : 1 Function Gain/attenuation +0 dB +1 dB : +15 dB +16 dB : +23 dB Not used : Not used -0 dB : -15 dB : -31 dB 0 1 - - - - - - Output gain 1 dB 0 dB - - - - - - - Soft-step action Act Wait DocID18305 Rev 3 33/40 I2C bus specification TDA7718B Table 14. Treble filter (9) MSB D7 - - 0 1 LSB D6 D5 - - 0 0 1 1 0 1 0 1 - - D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 Function Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB - - - - - Treble center frequency 10.0 kHz 12.5 kHz 15.0 kHz 17.5 kHz - - - - - Soft-step action Act Wait Table 15. Middle filter (10) MSB LSB Function D7 - - 0 1 34/40 D6 - D5 - 0 0 1 1 0 1 0 1 - - D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB - - - - - Middle Q factor 0.75 1 1.25 Reserved - - - - - Soft-step action Act Wait DocID18305 Rev 3 I2C bus specification TDA7718B Table 16. Bass filter (11) MSB D7 - - 0 1 LSB D6 D5 - - 0 0 1 1 0 1 0 1 - - D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 - - - - - - - - - - Function Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB Bass Q factor 1.0 1.25 1.5 2.0 Soft-step action Act Wait Table 17. Subwoofer / middle / bass (12) MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 1 0 1 - - - - - - - - - - - 0 1 - - - - - 0 0 1 1 0 1 0 1 - - - 0 0 1 1 0 1 0 1 - - - - - - - - - - - - - 0 1 DocID18305 Rev 3 Function Subwoofer cut-off frequency 55 Hz 85 Hz 120 Hz 160 Hz Subwoofer output phase 180 deg 0 deg Middle center frequency 500 Hz 1000 Hz 1500 Hz 2500 Hz Bass center frequency 60 Hz 80 Hz 100 Hz 200 Hz Bass DC mode On Off 35/40 I2C bus specification TDA7718B Table 18. Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) MSB D7 - 0 1 LSB D6 D5 D4 D3 D2 D1 D0 0 0 : 0 0 0 : 1 1 1 0 0 : 0 0 0 : 0 0 1 0 0 : 0 1 1 : 1 1 x 0 0 : 1 0 0 : 1 1 x 0 0 : 1 0 0 : 1 1 x 0 0 : 1 0 0 : 1 1 x 0 1 : 1 0 1 : 0 1 x - - - - - - - Function Gain/attenuation 0 dB 1 dB : +15 dB -0 dB -1 dB : -78 dB -79 dB mute Soft-step action Act Wait Table 19. Testing audio processor 1 (19) MSB D7 - LSB D6 - D5 - D4 D3 D2 D1 - - - - 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 D0 0 1 - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - - 1. The control bit needs both I2C test mode on & sub-address test mode on. 2. The control bit does not depend on test mode. 36/40 DocID18305 Rev 3 - Function Audio processor testing mode Off On Test multiplexer at SE1L (1) SSCLK REQ SMCLK DCDet Vth High DCDet Vth Low IntZeroErr Ref5V5 VGB1.95 Clock200k SDCLK VrefDCO Clock fast mode (2) On Off Clock source (2) External Internal (200 kHz) Attenuator gain clock control (2) On Off I2C bus specification TDA7718B Table 20. Testing audio processor 2 (20) MSB D7 - - - - - LSB D6 - - - - - D5 - - - - - D4 - - - 0 0 1 1 0 0 1 1 D3 - - - 0 1 0 1 0 1 0 1 D2 - - 0 1 - - D1 Function D0 - 0 1 0 1 - - - Test architecture (1) Normal Split - Oscillator clock (2) 400 kHz 800 kHz - Soft-step curve (2) S-Curve Linear curve - Manual set busy signal (1) Auto Auto 0 1 - Request for clk generator (1) Allow Allow Stopped Stopped - - 0 1 - - - - - No DCO spike rejection(1) On Off x x - - - - - - Not used 1. The control bit needs sub-address test mode on. 2. The control bit does not depend on test mode. Table 21. Testing audio processor 3 (21) MSB D7 - - - LSB D6 - - - D5 - - - D4 - - - D3 - - - D2 - - 0 1 D1 - 0 1 - Function D0 0 1 Enable clock for FL/FR/RL/RR/SWL/SWR On Off - Enable clock for volume On Off - Enable clock for treble and bass On Off - - - - 0 1 - - - Enable clock for loudness and middle On Off x x x x - - - - Not used DocID18305 Rev 3 37/40 Package information 6 TDA7718B Package information n order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 22. TSSOP28 mechanical data and package dimensions MM INCH $)- -). 490 -!8 ! ! -). 490 B C $ % % , , K AAA /54,).%!.$ -%#(!.)#!,$!4 ! ! E -!8 PLQPD[ .OTE $AND%DOESNOTINCLUDEMOLDFLASHORPROTRUSIONS -OLD FLASHORPO TRUSIONS SHALLNOT EXCEED MM INCHPERSIDE 433/0 4HIN3HRINK3MALL/UTLINE0ACKAGE *%$%#-/!# $ *$3*36 38/40 DocID18305 Rev 3 TDA7718B 7 Revision history Revision history Table 22. Document revision history Date Revision Changes 10-Dec-2010 1 Initial release. 26-Feb-2013 2 Added “Note” on page 8. 24-Sep-2013 3 Updated disclaimer. DocID18305 Rev 3 39/40 TDA7718B Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 40/40 DocID18305 Rev 3