M61113FP Coil-less VIF/SIF REJ03F0015-0100Z Rev.1.00 Aug.25.2003 Description The M61113FP is a semiconductor integrated circuit built-in the PLL inter-carrier method VIF/SIF dedicated to NTSC. The circuit includes the VIF amplifier, image waveform detection, APC detection, IF/RF, AGC, VCO, AFT, LOCK DET, EQ, AF amplifier, limitter, FM waveform detector circuits, and acts as a small tuner. Features • • • • • Built-in VCO coil for intermediate frequency signal processing AFT adjustment is not required and flat temperature characteristics is realized Reference frequency of 3.58 MHz/4.00 MHz Image intermediate frequency US (47.75 MHz)/JP (58 .75 MHz) VIF/SIF mute function Coil-Less VIF/SIF Recommended Operating Conditions • Power-supply voltage range: 4.75 to 5.25 V • Recommended power-supply voltage: 5.0 V Application • TV, VCR Pin Configuration 1 20 EQ AMP F/B Video in 2 19 IF AGC 2 Vcc 3 18 IF AGC 1 17 VIF in 2 16 VIF in 1 15 GND M61113FP Video out Video det ou 4 APC 5 VCO F/B (Defeat) 6 SIF in (Delay Point) 7 14 RF AGC SIF out (US / JP SW) 8 13 AFT Audio out 9 12 Logic Vcc Audio Level Cont. 10 11 Ref Signal (3.58/4.00) Rev.1.00, Aug.25.2003, page 1 of 16 M61113FP Block Diagram VIF in 1 GND Audio Level Cont. Audio out SIF out (US / JP SW) Video in Vcc Video det out APC VCO F/B (Defeat) SIF in (Delay Point) 6 Ref Signal (3.58/4.00) VIF in 2 5 Logic Vcc IF AGC 1 4 Video out Rev.1.00, Aug.25.2003, page 2 of 16 10 9 3 AF AMP SIF A MP Coil-less V CO 8 2 7 1 AFT IF AGC 2 15 RF AGC EQ AMP F/B 16 FM Det LIM A MP EQ A MP LPF A PC Video Det IF AGC Det AMP VIF A MP 11 17 12 18 13 19 14 20 RF A GC A FT M61113FP Absolute Maximum Ratings (25°C, unless otherwise noted) Parameter Symbol Ratings Unit Supply voltage Vcc 6.0 V Total power dissipation Operating temperature Storage temperature Pd Topr1 Tstg 969 −20 to 75 −40 to 150 mW °C °C Temperature Characteristics (Maximum Ratings) Mounting in standard circuit board Power Dissipation Pd [mW] 1200 969 1000 800 582 600 400 200 0 0 25 50 75 100 Ambient Temperature Ta [°C] 125 150 Recommended Operating Conditions (Ta = 25°C, unless otherwise noted) Parameter Terminal # Ratings Unit Supply voltage 3, 12 5.0 V Functional supply voltage range Reference Frequency GND 3, 12 11 15 4.75 to 5.25 3.579545 GND V MHz — Rev.1.00, Aug.25.2003, page 3 of 16 M61113FP Pin Function Pin No. Pin Name Function 1 Video out Video out terminal. Equivalent Circuit 3 1 1.4mA 2 3 4 5 Video in Vcc Video det out APC This terminal is input the video signal from Pin4 “Video det out” by SIF trap. Input this terminal to DC of Video det signal is necessary for IF AGC function. 3 Power supply terminal for VIF and SIF. Video detector output terminal. SIF trap and SIF BPF are connected to this terminal. It is necessary connecting external resistor for drive, because open emitter configuration. 3 APC filter terminal. 3 100 2 3 4 3.4V 5 21K 300 21K 300 20 200µA 6 VCO F/B VCO Feedback terminal. The feedback control is to keep the internal VCO of the uniform free-running frequency. This terminal has dual function, connecting to gnd select mode with VIF/SIF defeat. 3 To Defeat SW 1K 20K 6 Rev.1.00, Aug.25.2003, page 4 of 16 10K M61113FP Pin Function (cont) Pin No. Pin Name Function 7 SIF in (Delay Point) RF AGC Delay terminal. 4.5 MHz SIF signal “LIM IN” is input at this pin which has dual function. The RF AGC Delay Point is set up of DC component is FM signal. Equivalent Circuit 3 3.7V 7K 40 7 5.1K 40p 23K 160µA 8 SIF out (US/JP SW) SIF output terminal. FM signal which is converted to 4.5 MHz is output. This pin has dual function of being VIF VCO type selection terminal. Connect to GND with 1.5 kΩ; JPN “58.75 MHz” No connect; USA “45.75 MHz” 17.5K 3 600 3.8V 8 1.2mA 9 Audio out Sound output terminal. De-emphasis is achieved by external components. 3 9 0.8mA 10 11 Audio Level Cont. Ref Signal (3.58/4.00) AF Bypass terminal. It is connected to one of the input of a differential amplifier, external capacitor provides AC filtering. When resistor is connected in series with capacitor, it is possible to lower the amplitude of the audio output. when audio output terminal is not use, please connect this terminal to GND. Reference signal input terminal. It is input external signal with sinewave. In case of 4 MHz mode, connect to GND with 4.7 kΩ. 㪊 㪈㪇㪇 㪈㪇 㪊㪇㪢 㪈㪢 㪊㪇㪢 㪈㪢 3 4.0V 4K 11 1.3K 4.5K 200µA 12 Logic Vcc Power supply terminal for Logic and Ref amp. Rev.1.00, Aug.25.2003, page 5 of 16 12 20K M61113FP Pin Function (cont) Pin No. Pin Name Function 13 AFT AFT output terminal. Because of pulse-like signal output, Smoothing capacitor is connected externally. Equivalent Circuit 3 350K 50 13 350K 14 RF AGC RF AGC output terminal. It is current drive type. 3 50 14 500µA 15 16 17 GND VIF in 1 VIF in 2 Ground terminal for VIF and SIF. IF signal after SAW filter is input. It is balance-type input. 15 3 2.3V 2K 16 17 2K 14K 18 19 IF AGC 1 IF AGC 2 IF AGC filter terminal 1. External capacitor affects AGC speed. Where this terminal is grounded, the effect of VIF amp, becomes minimum gain. IF AGC filter terminal 2. 3 10K 50 2.5K 19 18 20 EQ AMP F/B Equalizer feedback terminal. It is possible to change the AC response of the video signal by attaching L, C, R to this terminal. 3 2.2K 500 20 Rev.1.00, Aug.25.2003, page 6 of 16 7K M61113FP Electrical Characteristics General (Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1) Parameter Symbol Test circuit Test point Input point Input signal SW condition Limits No. Min Typ Max Unit 1 VIF/SIF Vcc current Icc1 1 Pin3 — — — 44 63 82 mA 2 Logic Vcc Current Icc2 1 Pin12 — — — 3.2 4.7 6.1 mA 3 VIF/SIF Vcc current@Defeat Icc3 1 Pin3 Pin12 — — SW6=2 6.3 9.0 12.0 mA 4 Ref. signal input level Fref 1 Pin11 Pin11 — 50 100 600 mVpp Note# VIF Section 1 (Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1) No. Parameter Symbol Test circuit Test point Input point Input signal Min Typ Max Unit 5 Video out Vodet 1 TP1 Pin16, 17 SG1 0.95 1.20 1.45 Vpp 6 Sync Tip level Vsync 1 TP1 Pin16, 17 SG2 1.20 1.45 1.70 V 7 Video S/N VoS/N 1 TP1 Pin16, 17 SG2 48 50 — dB 1 8 Video Out Freq. response BW 1 TP1 Pin16, 17 SG3 6 7 — MHz 2 9 Input sensitivity VinMIN 1 TP1 Pin16, 17 SG4 — 45 52 dBuV 3 10 Max. IF input VinMAX 1 TP1 Pin16, 17 SG5 101 105 — dBuV 4 11 IF AGC Range GR 1 — — 49 60 — dB 5 12 IF AGC voltage @80 dBuV IFAGC 1 TP19 Pin16, 17 SG6 2.7 3.0 3.3 V 13 Capture range U CR-U 1 TP1 Pin16, 17 SG7 0.80 1.00 — MHz 6 14 Capture range L CR-L 1 TP1 Pin16, 17 SG7 1.38 1.75 — MHz 7 15 Inter modulation IM 1 TP1 Pin16, 17 SG8 32 38 — dB 8 16 D/G DG 1 TP4 Pin16, 17 SG9 — 3 5 % 17 D/P DP 1 TP4 Pin16, 17 SG9 — 3 5 deg 18 RF AGC High voltage RFagcH 1 TP14 Pin16, 17 SG10 SW7=3 4.4 4.7 5.0 V 19 RF AGC Low voltage RFagcL 1 TP14 Pin16, 17 SG11 SW7=3 0 0.3 0.6 V 20 RF AGC delay point RFDP 1 TP14 Pin16, 17 SG12 SW7=3 82 85 88 dBuV Rev.1.00, Aug.25.2003, page 7 of 16 SW condition SW10=2 Limits Note# 9 M61113FP VIF Section 2 (Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1) No. Parameter Symbol Test circuit Test point Input point Input signal SW condition Min Typ Max Unit Note# 21 AFT sensitivity µ 1 TP13 Pin16, 17 SG13 10 26 40 mV/ kHz 10 22 AFT High voltage AFTH 1 TP13 Pin16, 17 SG14 4.3 4.7 5 V 10 23 AFT Low voltage AFTL 1 TP13 Pin16, 17 SG15 0 0.3 0.7 V 10 24 AFT Mute voltage AFTM 1 TP13 Pin16, 17 SG16 2.4 2.5 2.6 V 25 AFT Center voltage @US mode VaftUS 1 TP13 Pin16, 17 SG2 2.40 2.65 2.90 V 26 AFT Center voltage @JP mode VaftJP 1 TP13 Pin16, 17 SG17 2.60 2.87 3.15 V SW8=2 Limits SIF Section (Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1) Symbol Test circuit Test point Input point Input signal SW condition Limits Parameter Min Typ Max Unit 27 AF output level VoAF 1 TP9 Pin7 SG18 SW7=2 400 700 1000 mVrms 28 AF output THD THDAF 1 TP9 Pin7 SG18 SW7=2 — 0.4 0.9 % 29 Audio S/N AF S/N 1 TP9 Pin7 SG19 SW7=2 SW19=2 50 55 — dB 11 30 Limiting sensitivity LIM 1 TP9 Pin7 SG20 SW7=2 SW19=2 — 50 55 dBuV 12 SG21 SIF output level SIFG SG19 SW7=2 90 96 102 dBuV No. 31 1 TP8 Pin7 Note# VCO Section (Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1) Parameter Symbol Test circuit Test point Input point Input signal SW condition Limits No. Min Typ Max Unit Note# 32 VIF VCO freerun @US mode FvcofUS 1 TP13 — — SW10=2 SW13,19=2 -500 0 +500 kHz 13 33 VIF VCO freerun @JP mode FvcofJP 1 TP13 — — SW8,10=2 SW13,19=2 -500 0 +500 kHz 13 Rev.1.00, Aug.25.2003, page 8 of 16 M61113FP Test Circuit 51 SW13 TP14 4.7K 2 0.01u 0.1u 0.1µ 0.22u 0.22µ SW19 1 0.1u 0.1u 0.1µ IF Sig nal 0.01u 0.01u 0.01µ 51 Ref. Sig nal 5V 1 0.0 1µ 1u TP13 SW11 TP19 20 19 18 17 16 15 14 33u 33µ 13 12 11 RF AGC V IF A MP A MP A FT EQ AMP 1 LPF APC LIM A MP Coil-less V CO 2 3 4 SIF AMP 5 6 7 9 SW8 10 SW10 1 JP 1.0K 0.01u 0.01µ 2 SW7 240 TP1 1 0.1u 0.1µ 0.47u 200 0.47µ 1000p 33u 33µ 0.01u 0.01µ US SW6 AF A MP 8 TP6 5V FM Det 0.47u 0.47µ V ideo Det 7.5K IF AGC Det TP8 TP9 15u 15µ 1 330 3 2 LIM IN Signal 51 1K TP4 Note; This test circuit is based on RENESAS board for evarution. Rev.1.00, Aug.25.2003, page 9 of 16 2 2 M61113FP Input Signal SG Termination with 50 ohm 1 2 3 fm = 20 kHz CW CW CW fm = 20 kHz fm = 20 kHz CW fm = 20 kHz CW CW CW 10 f0 = 45.75 MHz Vi = 90 dBuV f0 = 45.75 MHz Vi = 90 dBuV f1 = 45.75 MHz Vi = 90 dBuV f2 = Freq. Variable Vi = 70 dBuV f0 = 45.75 MHz Vi = Variable f0 = 45.75 MHz Vi = Variable f0 = 45.75 MHz Vi = 80 dBuV f0 = Freq. Variable Vi = 90 dBuV f1 = 45.75 MHz Vi = 90 dBuV f2 = 42.17 MHz Vi = 80 dBuV f3 = 41.25 MHz Vi = 80 dBuV f0 = 45.75 MHz Sync Tip Level = 90 dBuV 87.5% TV modulation 10 step waveform f0 = 45.75 MHz Vi = 70 dBuV 11 12 13 14 15 16 17 18 19 20 21 f0 = 45.75 MHz f0 = 45.75 MHz f0 = Freq. Variable f0 = 45.75-0.5 MHz f0 = 45.75+0.5 MHz f0 = 45.75+/-0.5 MHz f0 = 58.75 MHz f0 = 4.5 MHz f0 = 4.5 MHz f0 = 4.5 MHz f0 = 4.5 MHz CW CW CW CW CW CW CW fm = 1 kHz +/- 25 kHz dev CW fm = 1 kHz +/- 25 kHz dev CW 4 5 6 7 8 9 Rev.1.00, Aug.25.2003, page 10 of 16 Vi = 100 dBuV Vi = Variable Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = Variable Vi = Variable AM = 77.8% Mixed signal AM = 77.8% AM = 16.0% AM = 77.8% Mixed signal CW M61113FP Mode Select (Recommended Condition: Ta = 25°C Vcc = 5.0 V) IF Defeat select 6 pin condition Un defeat DC Open — Defeat 0 to 0.5 V GND US/JP select 8 pin condition Recommendation US JP None Pull down (1.0 kΩ +/–10%) No resistance 1 kΩ to GND Ref signal select 11 pin condition Recommendation 3.58 M 4.00 M None Pull down (4.7 kΩ +/–10%) No resistance 4.7 kΩ to GND SIF defeat select 10 pin condition Recommendation Un defeat DC Open — Defeat 0 to 0.3 V GND Rev.1.00, Aug.25.2003, page 11 of 16 Recommendation M61113FP Notes Note 1 Video S/N: VoS/N Input SG2 to VIF IN (Pin 16, 17) and measure the video out (TP1) noise in r.m.s. through a 5 MHz (–3 dB) L.P.F.. S/N=20log 0.7 × Vodet (Vpp) NOISE (rms) (dB) Note 2 Video Band Width: BW • Measure the 1 MHz component level of Video output TP4 with a spectrum analyzer when SG3 (f2 = 44.75 MHz) is input to VIF IN (Pin 16, 17). • Reduce f2 and measure the value of (f1-f2) when the (f1-f2) component level reaches –3 dB from the 1 MHz component level as shown below. TP4 -3dB 1MHz BW (f1-f2) Note 3 Input Sensitivity: VIN MIN Input SG4 (Vi = 90 dBu) to VIF IN (Pin 16, 17) and then gradually reduce Vi and measure the input level when the 20 kHz component of Video output TP1 reaches –3 dB from Vo det level. Note 4 Maximum Allowable Input: VIN MAX • Input SG5 (Vi = 90 dBu) to VIF IN (Pin 16, 17), and measure the level of the 20 kHz component of Video output (TP1). • Gradually increase the Vi of SG and measure the input level when the output reaches –3 dB. Note 5 AGC Control Range: GR GR = VinMAX – VinMIN (dB) Note 6 Capture Range: CR-U • Increase the frequency of SG7 until the VCO is out of locked-oscillation. • And decrease the frequency of SG7 and measure the frequency fU when the VCO is locked. CR – U = fU – 45.75 (MHz) Note 7 Capture Range: CR-L • Decrease the frequency of SG7 until the VCO is out of locked-oscillation. • And increase the frequency of SG7 and measure the frequency fL when the VCO is locked. CR – L = 45.75 – fL Rev.1.00, Aug.25.2003, page 12 of 16 (MHz) M61113FP Note 8 Inter Modulation: IM • Input SG8 to VIF IN (Pin 16, 17), and measure video output TP1 with an oscilloscope. • Adjust AGC filter voltage TP19 so that the minimum DC level of the output waveform is Vsync. • At that time, measure TP1 with a spectrum analyzer. The inter modulation is defined as a difference between 0.92 MHz and 3.58 MHz frequency components. Note 9 RF AGC Delay Point (TV Mode): RFDP • Input SG12 to VIF IN (Pin 16, 17) and gradually reduce level and then measure the input level when RF AGC output (TP14) reaches 1/2Vcc, as shown below. • At that time, the state of Pin 7 is DC open. TP14 Voltage RFagcH 1/2Vcc RFagcL RFDP SG12 Level (dBµV) Note 10 AFT sensitivity: µ, Maximum AFT Voltage: AFTH, Minimum AFT Voltage: AFTL • Input SG13 to VIF IN (Pin 16, 17) and set the frequency of SG13 so that the voltage of AFT output TP13 is 3 volt. The frequency is named f(3). • Set the frequency of SG13 so that the AFT output voltage is 2 volt. This frequency is named f(2). • In the graph shown below, maximum and minimum DC voltage are AFTH and AFTL, respectively. µ= 1000 f(2) - f(3) (mV) (KHz) (mV/kHz) TP13 Voltage AFTH 3V 2V AFTL f (3) Rev.1.00, Aug.25.2003, page 13 of 16 f (2) f (MHz) M61113FP Note 11 Audio S/N: AF S/N Input SG19 to SIF IN (Pin 7), and measure the output noise level of Audio output (TP9) with FLAT-r.m.s.. This level is named Vn1. VoAF1 (mVrms) Vn1 (mVrms) AF S/N = 20log (dB) Note 12 Limiting Sensitivity: LIM • Input SG20 to LIM IN, and measure the 1 kHz component level of AF output TP9 with FLAT-r.m.s.. • Input SG21 to LIM IN, and measure the noise level of AF output TP9 with FLAT-r.m.s.. • The input limiting sensitivity is defined as the input level when the difference between each 1 kHz components of audio output (TP9) is 30 dB, as shown below. TP9 (rms) SG20 while TP9 is input 30 dB SG21 while TP9 is input SIF IN (dBµV) LIM Note 13 VIF VCO Freerun Frequency: FvcofUS/FvcofJP • Input 3.579545 MHz to Ref IN (Pin 11), and set up SW as shown following. SW No. 20 8 10 11 13 19 US Mode Setting 3 1 2 1 2 2 Condition Add to 2.5 V No-Connecting R GND No-Connecting R No-Connecting C GND JP Mode Setting 3 2 2 1 2 2 Condition Add to 2.5 V Connecting 1 kΩ GND No-Connecting R No-Connecting C GND *VCO SW: US/JP #Fref SW • Measure the frequency of output signal at AFT out (TP13) each when be selected US or JP by SW10. • Measured frequency’s are defined FaftUS (US Mode), FaftJP (JP Mode). The VCO freerun frequency is calculated by following. <Fref = 3.579545 MHz> • US Mode FvcofUS = 52.915 (MHz) – 2 × FaftUS (MHz) – 45.75 (MHz) [MHz] • JP Mode FvcofJP = 65.925 (MHz) – 2 × FaftJP (MHz) – 58.75 (MHz) Rev.1.00, Aug.25.2003, page 14 of 16 [MHz] M61113FP Application IF Sig nal Ref. Signal 4.7K SAW 0.1µ 4.00 0.1µ 0.0 1µ 0.01µ 0.22µ 3.58 0.01µ 47µ 47u 20 19 18 17 16 15 14 13 12 11 RF AGC VIF A MP AMP A FT IF A GC Det Video Det EQ AMP 1 LPF A PC LIM A MP Coil-less V CO 2 3 4 5 SIF A MP 6 7 AF AMP 8 9 7.5K 0.01µ 0.1µ 1.0K 5V 10 JP 1000p 0.0 1µ 200 0.47µ US 33µ FM Det 0.47µ 240 15µ D e feat 330 1K N on-D efeat • By pass capacitance for Logic Vcc (Pin12) should be mounted close hard by Logic GND (Pin15) • In order to mitigate the surroundings lump by the VIF input, the balanced connection from a SAW filter to the VIF input pin of 16, 17 recommends a putter which serves as a 1t coil by Tip C or the jumper. Special components SAW:SAF45MA210Z TRP:TPSRA4M50B00 BPF:SFSH4.5MEB2 Rev.1.00, Aug.25.2003, page 15 of 16 Rev.1.00, Aug.25.2003, page 16 of 16 Z1 G E HE e 1 20 EIAJ Package Code SSOP20-P-255-0.65 z y Detail F D b JEDEC Code — 10 11 x M Weight(g) — A2 Detail F A Lead Material Cu Alloy L1 MMP A1 F c L A A1 A2 b c D E e HE L L1 z Z1 x y Symbol e1 b2 e1 I2 b2 Dimension in Millimeters Min Nom Max 1.45 — — 0 0.1 0.2 — — 1.15 0.32 0.17 0.22 0.13 0.15 0.2 6.6 6.4 6.5 4.3 4.5 4.4 0.65 — — 6.2 6.4 6.6 0.3 0.5 0.7 1.0 — — — 0.325 — — — 0.475 — — 0.13 — — 0.1 — 0° 10° — 0.35 — — 5.8 — 1.0 — — Recommended Mount Pad e Plastic 20pin 255mil SSOP I2 20P2F-A M61113FP Package Dimensions Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0