CMX869A - CML Microcircuits

CMX869A
CML Microcircuits Low Power V.32 bis Modem
COMMUNICATION SEMICONDUCTORS
with Auto / Manual Connect
D/869A/2 August 2005
Provisional Issue
Features
Applications
•
V.32 bis/V.32/V.22 bis/V.22 Automodem (14400,
•
EPOS Terminals
12000, 9600, 7200, 4800, 2400, 1200 bps Duplex)
•
Telephone Telemetry Systems
•
V.22 bis / V.22 Manual Modem (2400, 1200 bps)
•
Remote Utility Meter Reading
•
V.23 (1200/75, 1200/1200, 75, 1200 bps FSK)
•
Security Systems
•
Bell 202 (1200/150, 1200/1200, 150, 1200 bps FSK)
•
Industrial Control Systems
•
V.21 or Bell 103 (300/300 bps FSK)
•
Electronic Cash Terminals
•
DTMF/Tones Transmit and Receive
•
Pay-Phones
•
‘Powersave’ Standby Mode
•
Cable TV Set-Top Boxes
•
Asynchronous, Synchronous and HDLC Modes
1.
Brief Description
The CMX869A is a multi-standard modem for use in EPOS terminals, telephone based information and
telemetry systems. It can transmit and detect standard DTMF and modem calling and answer signals or
user-specific programmed single or dual tone signals. A general purpose Call Progress signal detector is
also included. Flexible line driver and receive hybrid circuits are integrated on chip, requiring only passive
external components to build a 2 or 4-wire line interface.
The device features a software controlled hook switch Relay Drive output and a Ring Detector circuit,
which continue to function when the device is in Powersave mode. When a line voltage reversal or ringing
signal is detected, the Ring Detector Circuit can provide an interrupt which can be used to wake up the
host µController.
Control of the device is via a simple, high-speed serial bus that operates in normal and Powersave
modes, which is compatible with most types of µC serial interface. The data transmitted and received by
the modem is also transferred over the same serial bus. On-chip programmable Tx and Rx USARTs,
compatible with V.14, are provided for use with asynchronous data and to allow unformatted synchronous
data to be received or transmitted as 8-bit words or received as an HDLC packet.
The CMX869A operates from a single 3.3V supply over a temperature range of -40°C to +85°C and is
available in 24-pin TSSOP (E2), SOIC (D2) and DIL (P4) packages.
© 2005 CML Microsystems Plc
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
CONTENTS
Section
Page
1.
Brief Description ..................................................................................... 1
2.
Block Diagram ......................................................................................... 3
3.
Signal List ................................................................................................ 4
4.
External Components............................................................................. 6
4.1
Power Supply Connections ...................................................... 7
4.2
Ring Detector Interface ............................................................. 8
4.3
Line Interface.............................................................................. 9
5.
General Description.............................................................................. 11
5.1
Tx USART.................................................................................. 11
5.2
FSK and QAM Modulators....................................................... 13
5.3
Tx Filter and Equaliser ............................................................ 13
5.4
DTMF/Tone Generator ............................................................. 13
5.5
Tx Level Control and Output Buffer....................................... 13
5.6
Rx Level Control ...................................................................... 14
5.7
Rx DTMF/Tones Detectors ...................................................... 14
5.8
Rx Modem Filterering and Demodulation.............................. 15
5.9
Rx Modem Pattern Detectors.................................................. 15
5.10
Rx USART ................................................................................. 15
6.
C-BUS Interface and Software Description........................................ 17
6.1
General Reset Command ........................................................ 19
6.2
General Control Register ........................................................ 19
6.3
Transmit Mode Register .......................................................... 21
6.4
Receive Mode Register............................................................ 25
6.5
QAM Modem Command Register........................................... 27
6.6
Tx Data Register....................................................................... 28
6.7
Rx Data Register ...................................................................... 29
6.8
Status Register......................................................................... 29
6.9
QAM Modem Status Register ................................................. 33
6.10
Programming Register ............................................................ 35
7.
Application Notes ................................................................................. 38
8.
Performance Specification................................................................... 39
8.1
Electrical Performance ............................................................ 39
8.1.2 Operating Limits ......................................................... 39
8.1.3 Operating Characteristics.......................................... 40
It is always recommended that you check for the latest product datasheet
version from the Datasheets page of the CML website: [www.cmlmicro.com].
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2.
CMX869A
Block Diagram
Figure 1 Block Diagram
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3.
CMX869A
Signal List
CMX869A
D2/E2/P4
Signal
Description
Pin No.
Name
Type
1
REPLY DATA
TS
2
RDRVN
OP
4
SERIAL
CLOCK
IP
A 3-state C-BUS serial data output to the µC. This
output is high impedance when not sending data to the
µC.
Relay Drive output, low resistance pull down to VSS
when active and medium resistance pull up to VDD
when inactive.
The C-BUS serial clock input from the µC.
5
COMMAND
DATA
IP
The C-BUS serial data input from the µC.
6
CSN
IP
The C-BUS chip select input from the µC.
8
RXA
IP
The non-inverting input to the Rx Input Amplifier
9
RXBN
IP
10
RXAN
IP
A second, switched inverting input to the Rx Input
Amplifier. Used to increase the input stage gain. If not
required, leave this pin unconnected.
The inverting input to the Rx Input Amplifier
11
RXAFB
OP
The output of the Rx Input Amplifier.
13
VBIAS
OP
14
TXAN
OP
Internally generated bias voltage of approximately
AVDD/2, except when the device is in ‘Powersave’
mode when VBIAS will discharge to AVSS. Must be
decoupled to AVSS by a capacitor mounted close to the
device pins.
The inverted output of the Tx Output Buffer.
15
TXA
OP
The non-inverted output of the Tx Output Buffer.
17
RDN
IP
18
-
NC
Schmitt trigger input to the (inverting) Ring signal
detector. Connect to DVDD if Ring Detector is not used.
Reserved for future use. Do not connect to this pin.
20
VDEC
PWR/
OP
21
XTAL/CLOCK
IP
22
XTALN
OP
24
IRQN
OP
© 2005 CML Microsystems Plc
Internally generated 2.5V supply voltage. Must be
decoupled to DVSS by capacitors mounted close to the
device pins. No other connections allowed.
The input to the oscillator inverter from the Xtal circuit
or external clock source.
The output of the on-chip Xtal oscillator inverter.
A ‘wire-ORable’ output for connection to a µC Interrupt
Request input. This output is pulled down to DVSS
when active and is high impedance when inactive. An
external pullup resistor is required ie R1 of Figure 2
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CMX869A
Signal list (cont.)
CMX869A
D2/E2/P4
Signal
Pin No.
Notes:
Name
Description
Type
3, 19
DVSS
PWR
7, 16
AVSS
PWR
12
AVDD
PWR
23
DVDD
PWR
IP
OP
TS
PWR
NC
=
=
=
=
=
© 2005 CML Microsystems Plc
The negative supply rail (ground) for the digital on-chip
circuits.
The negative supply rail (ground) for the analogue onchip circuits.
The positive supply rail for the analogue on-chip
circuits. Levels and thresholds within the device are
proportional to this voltage.
The positive supply rail for the digital on-chip circuits.
Input
Output
3-state Output
Power
No Connection
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4.
CMX869A
External Components
R1
X1
C1, C3, C8
C2, C4, C7, C9
C5, C6
100kΩ
6.144MHz
10uF
100nF
47pF (see text)
Resistors ±5%, capacitors ±20% unless otherwise stated.
Figure 2a Recommended External Components for a Typical Application
This device is capable of detecting and decoding small amplitude signals. To achieve this DVDD, AVDD
and VBIAS should be decoupled and the receive path protected from extraneous in-band signals. It is
recommended that the printed circuit board is laid out with both AVSS and DVSS ground planes in the
CMX869A area, as shown in Figure 2b, with provision to make a link between them close to the
CMX869A. To provide a low impedance connection to ground, the decoupling capacitors (C1 – C4, C7,
C8) must be mounted as close to the CMX869A as possible and connected directly to their respective
ground plane. This will be achieved more easily by using surface mounted capacitors.
VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must
be carefully decoupled, to ensure its integrity. If VBIAS needs to be used (other than as shown in figures
4a or 4b) to set external analogue levels, it must be buffered with a high input impedance buffer.
The values for capacitors C5 and C6 are suggestions for use with many typical crystals. However, the
values of these capacitors must be chosen to comply with the crystal manufacturer’s specification to
ensure that the clock accuracy is within 50ppm. The DVSS connections to the Xtal oscillator capacitors C5
and C6 should also be of low impedance and preferably be part of the DVSS ground plane to ensure
reliable start up of the oscillator.
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4.1
CMX869A
Power Supply Connections
ANALOGUE
C2, C9
C1
L2
DIGITAL
100nF
10uF
100nH (optional)
C4, C7
C3, C8
L1
100nF
10uF
100nH (optional)
Figure 2b Recommended Power Supply Connections and De-coupling
The inductors L1 and L2 can be omitted but this may degrade system performance.
Ensure that the length of the tracks between capacitors C2, C4, C7 and C9 and their corresponding
CMX869A device pins (pins 12, 23, 20 and 13) are kept as short as possible.
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4.2
CMX869A
Ring Detector Interface
R20
R21
R22
C20
C21
D1, D2
D3
D4
10kΩ, 0.5W
470kΩ
100Ω
0.33µF, 250V
0.33µF
18V zener
Opto isolator (NEC PS2701-1)
1N4004
Resistors ±5%, capacitors ±20%. Typical circuit, component types and values.
Figure 3 Ring Signal Detector Interface Circuit
Figure 3 shows how the CMX869A may be used to detect the large amplitude Ringing signal voltage
present on the 2-wire line at the start of an incoming telephone call. The ring signal is usually applied at
the subscriber's exchange as an ac voltage inserted in series with one of the telephone wires and will
pass through C20, R20, D1 and D2, and appear at the terminals of D3. When the signal reaches the
zeners’ (D1, D2) turn-on voltage, current will flow into the opto-isolator diode, turning on its output
transistor and discharging capacitor C21. Resistor R22 limits the current drawn by the opto-isolator output
to ~30mA peak. Whilst the ring tone is active and exceeds the zener voltage, the RDN node will be taken
low and the output of the Schmitt trigger will go high. The state of bit 14 (Ring Detect) of the Status
Register directly corresponds to the state of the Ring Detect Schmitt trigger output. If the corresponding
interrupt mask bit is set to 1, a C-BUS interrupt will be initiated (see the Status Register description in
section 6.8). Note that the opto-coupler diode (D3) must be protected by a reverse voltage diode. If this is
not available in the package, then an external 1N4148 (D5) may be fitted (as shown).
The minimum amplitude ringing signal that is certain to be detected is: Vzener + Vdiode + Vopto + 2V.
This requirement is met (with margin) by ringing signals of 40Vrms or above, for DVdd over the range 3.0
to 3.6V.
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4.3
CMX869A
Line Interface
A line interface circuit is needed to provide dc isolation and to terminate the line. The CMX869A is
connected to the line when the line relay is closed. The relay may be driven from the RDRVN output, as
shown in figure 4a. Control of the output level of the RDRVN pin is described in section 6.2. The diagrams
of Figure 4a and Figure 4b are functional representations only and should not be used in product designs.
A reference design will be available separately.
2-Wire Line Interface
Figure 4a shows a simplified interface for use with a 600Ω 2-wire line. The line termination impedance is
provided by the transformer, R13 and C10, high frequency noise is attenuated by C10 and C11, while
R11 and R12 set the receive signal level into the modem. For clarity the 2-wire line protection circuits
have not been shown.
R11
R12
R13
R14
C3
130kΩ (see text)
C10
100kΩ
C11
600Ω
C12
15kΩ (see text)
Resistors ±5%, capacitors ±20%
See Figure 2
33nF
100pF
100nF, 250V (see text)
Figure 4a 2-Wire Line Interface Circuit
The transmit line signal level is determined by the voltage swing between the TXA and TXAN pins, less
6dB due to the line termination resistor R13, and less the loss in the line coupling transformer. Allowing
for 1dB loss in the transformer, with the Tx Mode Register set for a Tx Level Control gain of 0dB the
nominal transmit line levels will be:
VDD = 3.3V
-7.5 dBm
-7.5 dBm
-3.5 and -5.5 dBm
QAM and FSK Tx modes (no guard tone)
Single tone transmit mode
DTMF transmit mode
For a line impedance of 600Ω, 0dBm = 775mVrms. See also section 8.1.3
In the receive direction, the signal detection thresholds within the CMX869A are proportional to AVDD and
are affected by the Rx Gain Control gain setting in the Rx Mode Register. The signal level into the
CMX869A is affected by the line coupling transformer loss and the values of R11 and R12 of Figure 4a.
The value of R11 should be chosen so that the received signal level at the RXAFB pin is 3.6dB lower than
that on the 2-wire line. For example if the transformer loss is 1dB then R11 should be 130kΩ. The value of
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CMX869A
R14 (15kΩ) is chosen to apply approximately 20dB of extra gain, when required by Type 1 Caller Line
Identification.
For best Rx performance, it is recommended that the transformer coupling arrangement should provide at
least 7dB trans-hybrid loss.
The RXBN input can be selected by setting bit 14 of the General Control Register to 1, which internally
connects RXBN to RXAN. With the components shown in Figures 4a and 4b, this will add approximately
20dB to the Rx gain, by connecting R14 in parallel with R11. This facilitates detection of certain signals
whilst on-hook, such as may be required for Type 1 Caller Line Identification reception. For the 2-wire line
interface shown in Figure 4a, capacitor C12 is required to provide an AC path through to the device when
the relay is open. If this facility is not required, R14 and C12 can be omitted.
4-Wire Line Interface
Figure 4b shows a simplified interface for use with a 600Ω 4-wire line. The line terminations are provided
by R10 and R13, high frequency noise is attenuated by C11 while R11 and R12 set the receive signal
level into the modem. Transmit and receive line level settings and the values of R11 and R14 are as for
the 2-wire circuit.
R10, 13
R11
R12
R14
C3
600Ω
C11
130kΩ (see text)
C12
100kΩ
15kΩ (see text)
Resistors ±5%, capacitors ±20%
See Figure 2
100pF
33nF
Figure 4b 4-Wire Line Interface Circuit
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5.
CMX869A
General Description
The CMX869A can operate as a full duplex QAM (Quadrature Amplitude Modulation) or DPSK
(Differential Phase Shift Keying) Automodem, using the following modulation schemes:
• V.32bis
• V.32
• V.22bis
• V.22
with data rates of 14400, 12000, 9600, 7200, 4800, 2400 or 1200bps.
Note: reference to QAM elsewhere in the datasheet implies QAM or DPSK, according to selected
operating mode.
It can also be set to operate under host control of the connection sequence in the following low speed
modem modes:
• V.22bis
• V.22
• V.21 or Bell 103. 300/300bps duplex FSK (Frequency Shift Keying).
• V.23 modem. 1200 or 75 bps FSK.
• Bell 202 modem. 1200 or 150 bps FSK.
The transmit circuits can also be set to any one of the following:
• DTMF transmit.
• Single tone transmit (from a range of modem calling, answer and other tone frequencies)
• User programmed tone or tone pair transmit (programmable frequencies and levels)
• Disabled.
The receive circuits can also be set to:
• DTMF detect.
• 2100Hz and 2225Hz answer tone detect.
• Call progress signal detect.
• User programmed tone or tone pair detect.
• Disabled.
The Ring Detect, Tone Decoder and FSK modem circuits can be configured to facilitate Type 1 (OnHook) Caller Identification. This facility is the subject of separate application notes.
When not in use, the CMX869A may be set into a Powersave mode, which disables all circuitry except for
the on-chip regulator, the C-BUS interface and the Ring Detector.
5.1
Tx USART
A flexible Tx USART is provided for all modem modes, designed to meet the requirements of V.14. It can
be programmed to transmit continuous patterns, Start-Stop characters or Synchronous unformatted data.
The data to be transmitted is written by the µC into the C-BUS Tx Data Register ($E3). The Tx and Rx
Data Register can be set to operate in 8 or 16-bit mode by setting the General Control Register b10
appropriately at power-on.
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CMX869A
Synchronous mode
If Synchronous Data mode has been selected the 8 data bits of each octet in the Tx Data Buffer are
transmitted serially, the lsb being sent first. The last transmitted byte will be re-transmitted if there is no
new data in the Transmit Data Register
Stop-Start (Asynchronous) mode
In Start-Stop mode an asynchronous character is transmitted for each octet in the Tx Data Register. Each
character consists of a single Start bit followed by 5, 6, 7 or 8 data bits from the Tx Data Buffer - lsb first followed by an optional Parity bit then - normally - one or two Stop bits. The Start, Parity and Stop bits are
generated by the USART as determined by the Tx Mode Register settings and are not taken from the Tx
Data Register. A continuous Stop signal (1) will be transmitted if there is no new data in the Transmit Data
Register.
Figure 5a Tx USART Output: Start-Stop mode, 8 Data Bits + Parity
16 bit (2-Character mode)
In 16-bit (2 character) mode data written to the Tx Data Register at C-BUS address $E3 will be treated as
two octets, b15-8 which will be transmitted first and b7-0 which will be transmitted second. If there is a
need to transmit a single octet when the Tx Data Register has been set to 16-bit mode this can be
achieved by writing the 8-bit data to C-BUS address $E4 instead of $E3.
If the Tx Data Register has been set to operate in 8-bit (1 character) mode, data should be written to CBUS address $E3, address $E4 being used to provide for Start-Stop transmit data overspeed as
described later.
Figure 5c Tx USART (in 16 Bit Mode)
Status Register, Tx Data Ready and Tx Data Underflow bits
Every time the contents of the C-BUS Tx Data Register have been transferred to the Tx Data Buffer the
Tx Data Ready flag bit of the Status Register is set to 1 to indicate that new data should be loaded into
the C-BUS Tx Data Register. This flag bit will be cleared to 0 when a new value is loaded into the Tx Data
Register.
If a new value is not loaded into the Tx Data Register in time for the next Tx Data Register to Tx Data
Buffer transfer then the Status Register Tx Data Underflow bit will be set to 1
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CMX869A
V.14 and Overspeed operation
In all modes the transmitted bit and baud rates are the nominal rates for the selected modem type, with an
accuracy determined by the XTAL frequency accuracy, however V.14 requires that Start-Stop characters
can be transmitted at up to 1% overspeed (basic signalling rate range) or 2.3% overspeed (extended
signalling rate range) by deleting a Stop bit from no more than one out of every 8 (basic range) or 4
(extended range) consecutive transmitted characters.
To accommodate this V.14 requirement the CMX869A allows the controlling µC to reduce the number of
transmitted Stop bits by one for selected characters in QAM Start-Stop modes. To do this, the device
must be set to operate in 1 character mode for the entire transmission by clearing General Control
Register b10 to 0 (note: the bit is only actioned following a reset or power-on). Characters written to thc CBUS Tx Data Register at address $E3 will then be transmitted with the programmed number of Stop bits,
but a character written to $E4 will be transmitted with one less Stop bit than the number programmed in
the Tx Mode Register.
In FSK Start-Stop modes, if the device is set for 1 character mode (General Control Register b10 = 0)
data written to $E4 will be transmitted with a 12.5% reduction in the length of the Stop bit at the end of
that character. In all 8 bit Synchronous Data modes data, written to $E4 will be treated as though it had
been written to $E3. The behaviour is not defined for 16 bit data mode.
The underspeed transmission requirement of V.14 is automatically met by the CMX869A, as in Start-Stop
mode it will insert extra Stop bit(s) if it has to wait for new data to be loaded into the C-BUS Tx Data
Register.
Data Scramblers
The QAM (V.32bis/V.32/V.22bis/V.22) modulators include compatible data scrambler functions that are
automatically enabled as required in AutoModem modes or may be manually controlled in V.22 bis and
V.22 manual operation from the Tx and Rx mode registers.
5.2
FSK and QAM Modulators
Serial data from the USART is fed to the FSK modulator if V.21, V.23, Bell 103 or Bell 202 mode has
been selected, or to the QAM modulator for V.22bis, V.22, V.32bis and V.32 modes.
The FSK modulator generates one of two frequencies according to the transmit mode and the value of
current transmit data bit.
In V.22bis and V.22 modes, QAM modulation is applied to a carrier of 1200Hz (Low Band, Calling
modem) or 2400Hz (High Band, Answering modem).
In V.32bis and V.32 modes, QAM modulation is applied to a carrier of 1800Hz, using Trellis encoding for
most bit rates.
5.3
Tx Filter and Equaliser
The FSK or QAM/DPSK modulator output signal is fed through the Transmit Filter and Equaliser block
which limits the out-of-band signal energy to acceptable limits. In 1200 and 2400 bps, DPSK and QAM
manual modes this block includes a fixed compromise line equaliser which is automatically set for the
particular modulation type and frequency band being employed. This fixed compromise line equaliser may
be enabled or disabled by bit 15 of the General Control Register. The amount of Tx equalisation provided
compensates for one quarter of the relative amplitude and delay distortion of ETS Test Line 1 over the
frequency band used.
In Auto Modem modes, the appropriate equalisation for the particular operating mode is determined and
selected automatically by the device.
5.4
DTMF/Tone Generator
In DTMF/Tones mode this block generates DTMF signals or single or dual frequency tones. In V.22 bis
modem mode it is used to generate the optional 550Hz or 1800Hz guard tone.
5.5
Tx Level Control and Output Buffer
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CMX869A
The outputs (if present) of the Transmit Filter and DTMF/Tone Generator are summed then passed
through the programmable Tx Level Control (provides the ability to attenuate the transmitted signal by up
to 10.5dB) and Tx Output Buffer to the pins TXA and TXAN. The Tx Output Buffer has symmetrical
outputs to provide sufficient line voltage swing and to reduce harmonic distortion of the signal.
5.6
Rx Level Control
In normal (non loopback) mode, the output from the Rx Input Amplifier is fed to the Rx Gain Control
block. This provides the ability to attenuate the received signal by up to 10.5dB, depending on the value
programmed into the Receive Mode Register. The output from the Rx Gain Control block is routed either
to the Modem functions or to the Tone Detectors.
5.7
Rx DTMF/Tones Detectors
In Rx Tones Detect mode the received signal, after passing through the Rx Gain Control block, is fed to
the DTMF / Tones / Call Progress / Answer Tone Detector. The user may select any of four separate
detectors:
The DTMF Detector detects standard DTMF signals and identifies the transmitted character in the Status
Register. A valid DTMF signal will set bit 5 of the Status Register to 1 for as long as the signal is detected.
The Programmable Tone Pair Detector includes two separate tone detectors (see Figure 10). The first
detector will set bit 6 of the Status Register for as long as a valid signal is detected, the second detector
sets bit 7, and bit 10 of the Status Register will be set when both tones are detected.
The Call Progress Detector measures the amplitude of the signal at the output of a 275Hz - 665Hz
bandpass filter and sets bit 10 of the Status Register to 1 when the signal level exceeds the measurement
threshold. The response of the Call Progress filter, including the effect of external components of figures
4a and 4b, is shown in Figure 6.
10
0
-10
-20
dB
-30
-40
-50
-60
0
0.5
1
1.5
2
kHz
2.5
3
3.5
4
Figure 6 Response of Call Progress Filter
The Answer Tone Detector measures both amplitude and frequency of the received signal and sets bit 6
or bit 7 of the Status Register when a valid 2225Hz or 2100Hz signal is received.
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5.8
CMX869A
Rx Modem Filtering and Demodulation
When the receive part of the CMX869A is operating as a modem, the received signal is fed through a
bandpass filter to attenuate unwanted signals. The characteristics of the filter are determined by the
chosen receive modem type and frequency band.
The output of the filter is fed to the appropriate FSK or QAM demodulator depending on the selected
modem type:
In manual modem modes the signal level at the output of the Filter is also measured, compared
to a threshold value, and the result controls bit 10 of the Status Register.
In QAM Auto Modem modes, a V.32 bis/V.32 echo canceller is included, which will work with a
round trip delay of up to 1.25 seconds.
5.9
Rx Modem Pattern Detectors
In manual modem modes the received bit stream is monitored for continuous 1’s, for continuous 0’s, and
for continuous alternating 1’s and 0’s. Bit 7, 8 or 9 of the Status Register will be set to 1 whenever 32 bits
of the appropriate pattern has been received and will then remain at 1 for 12 bit times after the end of the
detected pattern unless the receive operating mode is changed, in which case the pattern detectors are
reset within 2 milliseconds.
In all modem modes a V.14 ‘Break’ signal detector is implemented in Start-Stop mode by monitoring the
received data and setting bit 8 of the Status Register when 2N + 4 consecutive 0’s have been received, N
being the total number of bits per character including the Start, Stop and any Parity bits.
The demodulated data is passed through a de-scrambler according to the requirements of the receiver
operating mode. This function is enabled automatically, as required.
5.10
Rx USART
A flexible Rx USART is provided for all modem modes, meeting the requirements of V.14 for all modem
speeds. Depending on the setting of the Rx Mode Register, it will treat the received data bit stream as
Synchronous data, as Start-Stop characters or as HDLC Frames.
Synchronous mode
In Synchronous mode the received data bits are all fed into an internal Rx Data Buffer which is copied into
the C-BUS Rx Data Register after every 8 or 16 bits, depending on the setting of the General Control
Register ‘2 character mode’ bit, b10.
Start-Stop (Asynchronous) mode
In Start-Stop mode the USART Control logic looks for the start of each character, then feeds only the
required number of data bits (not parity) into an internal Rx Data Buffer. If the parity bit is used, both
parity and the presence of a Stop bit are checked. Depending on the setting of b10 of the General
Control Register, the data bits from 1 or 2 received characters are placed into the C-BUS Rx Data
Register. If parity has been enabled the C-BUS Status Register ‘Even Parity’ bit(s) are set or cleared
according to the received parity.
HDLC mode
In HDLC mode (algorithm based on BS 5397 Part 1 1985) the CMX869A recognises the start and end of
an HDLC Frame by monitoring the received bit stream for the presence of the flag byte (01111110
binary). The received data and FCS octets within the Frame are then passed to the C-BUS Rx Data
Register (one or two octets at a time depending on the setting of the ’2-character’ bit) after removal of any
‘stuffed’ 0’s. A 16-bit Frame Check Sequence is calculated (as defined in RFC 1331) from the received
data octets and compared to the received FCS at the end of the Frame, bit 4 of the Status Register being
set to 1 if the two FCSs do not match. The 16 bit FCS data is output to the C-Bus Rx Data Register
following the last data received.
16 bit (2-character mode)
If 2-character mode has been selected, received characters will normally be transferred to the C-BUS Rx
Data Register two at a time and the Status Register b1 set to 1. However, the USART includes a time-out
© 2005 CML Microsystems Plc
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CMX869A
function so that if a message contains an odd number of characters the final character will be transferred
to the Rx Data Register and b1 of the Status Register will be cleared to ‘0’. This indicates that the next
data to be read from the Rx Data Register holds the single last character in the least significant byte.
Figure 7 Rx USART (in 16 Bit Mode)
Status Register, Rx Data Ready and Rx Data Overflow bits
Whenever a new character or characters is copied into the C-BUS Rx Data Register, the Rx Data Ready
flag bit b6 of the Status Register is set to ‘1’ to prompt the µC to read the new data.
If the µC has not read the previous data from the Rx Data Register by the time that the CMX869A places
fresh data into it, the Rx Data Overflow flag bit, b5 of the Status Register, will be set to 1.
The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read by
the µC.
V.14 operation and Overspeed (in Asynchronous mode)
If the Stop bit is missing at the end of a character (a ‘0’ received instead of a ‘1’) the received character
will still be placed into the C-BUS Rx Data Register, but unless allowed by the V.14 overspeed option (see
below), the Status Register Rx Framing Error bit (b4) will be set to ‘1’ and the USART will re-synchronise
onto the next ‘1’ – ‘0’ (Stop – Start) transition. 1
The receive USART is able to cope with missing Stop bits; up to 1 missing Stop bit in every 8 consecutive
received characters being allowed for the +1% overspeed (basic signalling rate) V.14 mode and 1 in 4 for
the +2.3% overspeed (extended signalling rate) mode.
The CMX869A Rx Mode Register can be set for 0, +1% or +2.3% overspeed operation. Missing Stop bits
beyond those allowed by the selected overspeed option will set the Rx Framing Error flag bit of the Status
Register.
1
In overspeed mode, the parity detect function can report incorrect parity for the character following a
missing stop bit.
© 2005 CML Microsystems Plc
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6.
CMX869A
C-BUS Interface and Software Description
This block provides for the transfer of data and control or status information between the CMX869A’s
internal registers and the µC over the C-BUS serial bus. Each transaction consists of a single Register
Address byte sent from the µC which may be followed by one or more data bytes sent from the µC to be
written into one of the CMX869A’s Write Only Registers, or one or more bytes of data read out from one
of the CMX869A’s Read Only Registers, as illustrated in Figure 8.
Data sent from the µC on the Command Data line is clocked into the CMX869A on the rising edge of the
Serial Clock input. Reply Data sent from the CMX869A to the µC is valid when the Serial Clock is high.
The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS
interface is compatible with most common µC serial interfaces and may also be easily implemented with
general purpose µC I/O pins controlled by a simple software routine. Figure 13 gives detailed C-BUS
timing requirements.
The following C-BUS addresses and registers are used by the CMX869A:
General Reset Command (address only, no data).
General Control Register, 16-bit write only.
Transmit Mode Register, 16-bit write-only.
Receive Mode Register, 16-bit write-only.
Transmit Data Register, 8 or 16-bit write only.
Alternate Transmit Data Register, 8-bit write only.
Receive Data Register, 8 or 16-bit read-only.
Status Register, 16-bit read-only.
Programming Register, 16-bit write-only.
QAM Modem Command Register, 16-bit write-only.
QAM Modem Status Register, 16-bit read-only.
Address $01
Address $E0
Address $E1
Address $E2
Address $E3
Address $E4
Address $E5
Address $E6
Address $E8
Address $EA
Address $EB
Note: The C-BUS addresses $E7, $E9, $EC, $ED, $EE and $EF are allocated for production testing and
should not be accessed in normal operation.
Interrupt Operation
The CMX869A will issue an interrupt, by taking the IRQN line low, when the IRQ bit 15 of the Status
Register and the IRQ Enable bit 6 in the General Control Register are both set = 1. The IRQ bit operation
is described in section 6.8.
© 2005 CML Microsystems Plc
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CMX869A
Figure 8 C-BUS Transactions
© 2005 CML Microsystems Plc
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6.1
CMX869A
General Reset Command
General Reset Command
(no data)
C-BUS address $01
This command resets the device, clears all bits of the General Control, Transmit Mode and Receive Mode
Registers as well as bits 15 and 13-0 of the Status Register and places the device into Powersave mode.
Whenever power is applied to the CMX869A, a built in power-on-reset circuit ensures that the device
powers up into the same state as follows a General Reset command. Nevertheless, it is recommended
that a General Reset command be sent to the device on power-up, after which the General Control
Register should be set as required.
6.2
General Control Register
General Control Register: 16-bit write-only.
C-BUS address $E0
This register controls general features of the CMX869A, such as the Powersave and Loopback modes,
the IRQ mask bits and the Relay Drive output.
All bits of this register are cleared to 0 by a General Reset command. Note that the 2-character (2C)
mode flag is only read following a reset or power-on.
Bit:
15
14
13
12
11
10
9
8
7
6
Equ
Hi
Gain
0
0
LB
2C
Rly
drv
Pwr
Rst
Irqn
en
5
4
3
2
1
0
IRQ Mask Bits
General Control Register b15: Tx and Rx Fixed Compromise Equalisers
This bit allows the Tx and Rx fixed compromise equalisers in the modem transmit and receive
filter blocks to be disabled in FSK/DPSK/QAM manual modem modes.
b15 = 1
Disable equalisers
b15 = 0
Enable equalisers (1200 or 2400bps modem modes)
General Control Register b14: Select high input gain
This bit selects the RXBN input pin and is used to increase the input stage gain.
b14 = 1
RXBN internally connected to RXAN
b14 = 0
RXBN open circuit
General Control Register b13,12: Reserved, set to 00
General Control Register b11: Analogue Loopback test mode
This bit controls the analogue loopback test mode. In loopback test mode both Transmit and
Receive Mode Registers should be set to the same modem type, band and bit rate. The line
interface relay must be open, as the test transmission that is fed back into the Rx path will
appear at the Tx pins. Analogue loopback is not available in QAM Auto modem modes.
b11 = 1
Local analogue loopback mode enabled
b11 = 0
No loopback (normal modem operation)
General Control Register b10: Modem 2-Character mode
Selects whether the Tx Data and Rx Data Registers operate in 1 or 2 character mode.
b10 = 1
2 character mode
b10 = 0
1 character mode
The character mode is only updated on exit from a General Control initated reset, so General
Control Register b7 (Power-up) must be set (written = 1) then cleared (written = 0), in conjunction
with setting the desired character mode. Note that V.14 overspeed operation is NOT available in
2 character mode.
© 2005 CML Microsystems Plc
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CMX869A
General Control Register b9: Relay Drive
This bit directly controls the RDRVN output pin.
b9 = 1
RDRVN output pin pulled to VSS
b9 = 0
RDRVN output pin pulled to VDD
General Control Register b8: Power-up
This bit controls the internal power supply to most of the internal circuits, including the Xtal
oscillator, internal clock synthesizer and VBIAS supply. Note that the General Reset command
clears this bit, putting the device into Powersave mode.
b8 = 1
Device powered up normally
b8 = 0
Powersave mode (all circuits disabled, except the on-chip regulator,
Ring Detect, RDRVN and C-BUS interface)
When power is first applied to the device, the following power-up procedure should be followed
to ensure correct operation.
i.
ii.
iii.
iv.
(Power is applied to the device)
Issue a General Reset command.
Write to the General Control Register (address $E0 setting both the Power-up bit
(b8) and the reset bit (b7) to 1 – leave in this state for a minimum of about 20ms –
this is required to ensure that the crystal oscillator, on-chip regulator and the VBIAS
supply are all operating prior to running any transmit or receive functions
The device is now ready to be programmed as and when required. Examples:
• A General Reset command could be issued to clear all the registers and
therefore powersave the device.
• The Reset bit in the General Control Register could be set to 0 as part of a
routine to program all the relevant registers for setting up a particular operating
mode.
When the device is switched from Powersave mode to normal operation by setting the Powerup bit to 1, the Reset bit should also be set to 1 and should be held at 1 for about 20ms while
the on-chip regulator, crystal oscillator, clock synthesizer and VBIAS stabilise before starting to
use the transmitter or receiver.
General Control Register b7: Reset
Setting this bit to 1 resets the CMX869A's internal circuitry, clearing all bits of the Transmit
Mode, Receive Mode, QAM Modem Control and Programming Registers and b13-0 of the
Status Register.
b7 = 1
Internal circuitry in a reset condition.
b7 = 0
Normal operation
General Control Register b6: IRQNEN (IRQN O/P Enable)
Setting this bit to 1 enables the IRQN output pin.
b6 = 1
IRQN pin driven low (to VSS) if the IRQ bit of the Status Register = 1
b6 = 0
IRQN pin disabled (high impedance)
General Control Register b5-0: IRQ Mask bits
These bits affect the operation of the IRQ bit of the Status Register as described in section 6.8
© 2005 CML Microsystems Plc
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6.3
CMX869A
Transmit Mode Register
Transmit Mode Register: 16-bit write-only.
C-BUS address $E1
This register controls the CMX869A transmit signal type and level. All bits of this register are cleared to 0
by a General Reset command or when b7 (Reset) of the General Control Register is 1.
Bit:
15
14
13
12
11
10
Tx mode = modem
Tx level
Tx mode = DTMF/Tones
Tx mode = Disabled
Tx level
9
8
7
Guard tone
6
5
Scrambler
0
DTMF twist
Set to 0000 0000 0000
4
3
2
1
0
Start-stop /
# data bits /
synch data
synch data source
DTMF or Tone select
Tx Mode Register b15-12: Tx mode
These 4 bits select the transmit operating mode.
b15
b14
b13
b12
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V.22, V.22 bis, V.32, V.32 bis
Reserved, do not use
V.22 bis 2400
V.22bis 2400
V.22 1200
V.22 1200
V.21 300 bps FSK
“
Bell 103 300 bps FSK
“
V.23 FSK
“
Bell 202 FSK
“
DTMF / Tones
Transmitter disabled
QAM AUTO modem
High band (Answering modem)
Low band (Calling modem)
High band (Answering modem)
Low band (Calling modem)
High band (Answering modem)
Low band (Calling modem)
High band (Answering modem)
Low band (Calling modem)
1200 bps
75 bps
1200 bps
150 bps
Tx Mode Register b11-9: Tx level
These 3 bits set the gain of the Tx Level Control block.
b11
b10
b9
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
© 2005 CML Microsystems Plc
0dB
-1.5dB
-3.0dB
-4.5dB
-6.0dB
-7.5dB
-9.0dB
-10.5dB
21
D/869A/2
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CMX869A
Tx Mode Register b8-7: Tx Guard tone (V.22 bis mode)
These 2 bits select the guard tone to be transmitted together with the highband (answer)
V.22 bis signal. Ignored in all other modes.
b8
b7
1
1
Tx 550Hz guard tone
1
0
Tx 1800Hz guard tone
0
x
No Tx guard tone
Tx Mode Register b6-5: Tx Scrambler (QAM, DPSK manual modes)
These 2 bits control the operation of the Tx scrambler used in QAM and DPSK modes.
Set both bits to 0 in FSK modes.
b6
b5
1
1
Scrambler enabled, 64 ones detect circuit enabled (normal use)
1
0
Scrambler enabled, 64 ones detect circuit disabled
0
1
Reserved, do not use
0
0
Scrambler disabled
Tx Mode Register b4-3: Tx Modem Data format
These two bits select Special or Start-stop mode and the addition of a parity bit to transmitted
characters in Start-stop mode.
b4
b3
1
1
Special modes (see below)
1
0
Start-stop mode, no parity
0
1
Start-stop mode, even parity bit added to data bits
0
0
Start-stop mode, odd parity bit added to data bits
Tx Mode Register b2-0: Tx Modem Data and Stop bits (Start-Stop modes)
In Start-stop mode these three bits select the number of Tx data and stop bits.
b2
b1
b0
1
1
1
8 data bits, 2 stop bits
1
1
0
8 data bits, 1 stop bit
1
0
1
7 data bits, 2 stop bits
1
0
0
7 data bits, 1 stop bit
0
1
1
6 data bits, 2 stop bits
0
1
0
6 data bits, 1 stop bit
0
0
1
5 data bits, 2 stop bits
0
0
0
5 data bits, 1 stop bit
Tx Mode Register b2-0: Tx Modem Data source (Special modes)
When b4-3 = 11 bits 2-0 select the source of the Transmitted data as below:
b2
b1
b0
1
1
1
Synchronous , data bytes taken directly from the Tx Data Buffer
1
1
0
Reserved, do not use.
1
0
1
Reserved, do not use.
1
0
0
Reserved, do not use.
0
1
1
Continuous 1s
0
1
0
Continuous 0s
0
0
1
Continuous alternating 1s and 0s (or 11, 00 in V22 modes)
0
0
0
Reserved, do not use.
Tx Mode Register b8: DTMF/Tones Mode - Reserved, set to 0
© 2005 CML Microsystems Plc
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D/869A/2
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CMX869A
Tx Mode Register b7-5: DTMF Twist (DTMF mode)
These 3 bits allow for adjustment of the DTMF twist to compensate for the frequency response of
different external circuits. The device varies the twist by making changes to the upper tone
group levels. Note that the twist cannot be adjusted mid-tone.
b7
b6
b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+2.0dB twist – normal setting when external response is flat
+1.0dB twist
+1.5dB twist
+2.5dB twist
+3.0dB twist
+3.5dB twist
+4.0dB twist
+4.5dB twist – do not use in conjunction with the 0dB Tx level setting
Tx Mode Register b4-0: DTMF/Tones mode
When DTMF/Tones transmit mode is selected (Tx Mode Register b15-12 = 0001), bits 4-0
select a DTMF signal or a fixed tone or one of four programmed tones or tone pairs for
transmission.
b4 = 0: Tx fixed tone or programmed tone pair
b3
b2
b1
b0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
© 2005 CML Microsystems Plc
Tone frequency (Hz)
No tone
697
770
852
941
1209
1336
1477
1633
1300
2100
2225
Tone pair TA
Tone pair TB
Tone pair TC
Tone pair TD
(Calling tone)
(Answer tone)
(Answer tone)
Programmed Tx tone or tone pair, see 6.10
“
“
“
23
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CMX869A
b4 = 1: Tx DTMF
b3
b2
b1
b0
Low frequency (Hz)
High frequency (Hz)
Keypad symbol
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
941
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
1633
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
D
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
© 2005 CML Microsystems Plc
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6.4
CMX869A
Receive Mode Register
Receive Mode Register: 16-bit write-only.
C-BUS address $E2
This register controls the CMX869A receive signal type and level.
All bits of this register are cleared to 0 by a General Reset command or when b7 (Reset) of the General
Control Register is 1.
Bit:
15
14
13
12
11
Rx mode = modem
10
9
8
0
Equaliser / De
srambler
0
0
0
0
0
0
Rx level
Rx mode = Tones detect
Rx mode = Disabled
0
Rx level
0
7
6
5
4
3
Start-stop/Synch
0
0
0
0
0
0
2
1
0
No. of bits and
parity
DTMF/Tones
0
0
0
Rx Mode Register b15-12: Rx mode
These 4 bits select the receive operating mode.
b15
b14
b13
b12
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V.22, V.22 bis, V.32, V.32 bis
QAM AUTO modem
Reserved, do not use
V.22 bis 2400
High band (Calling modem)
V.22bis 2400
Low band (Answering modem)
V.22 1200
High band (Calling modem)
V.22 1200
Low band (Answer modem)
V.21 300 bps FSK
High band (Calling modem)
“
Low band (Answering modem)
Bell 103 300 bps FSK
High band (Calling modem)
“
Low band (Answering modem)
V.23 FSK
1200 bps
“
75 bps
Bell 202 FSK
1200 bps
“
150 bps
DTMF, Programmed tone pair, Answer Tone, Call Progress detect
Receiver disabled
Rx Mode Register b11-9: Rx level
These three bits set the internal gain of the Rx Gain Control block.
b11
b10
b9
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
© 2005 CML Microsystems Plc
0dB
-1.5dB
-3.0dB
-4.5dB
-6.0dB
-7.5dB
-9.0dB
-10.5dB
25
D/869A/2
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CMX869A
Rx Mode Register b8: Rx Auto-equalise (DPSK/QAM manual modem modes)
This bit controls the operation of the receive DPSK/QAM auto-equaliser. Set to 0 in FSK modes.
Set to 1 in 2400bps QAM mode. No effect in Auto Modem modes.
b8 = 1
b8 = 0
Enable auto-equaliser
DPSK mode: Auto-equaliser disabled
QAM mode : Auto-equaliser settings frozen
Rx Mode Register b7-6: Rx Scrambler (DPSK/QAM manual modem modes)
These 2 bits control the operation of the Rx descrambler used in QAM and DPSK modes.
Set both bits to 0 in FSK modes. No effect in Auto Modem modes.
b7
b6
1
1
Descrambler enabled, 64 ones detect circuit enabled (normal use)
1
0
Descrambler enabled, 64 ones detect circuit disabled
0
1
Reserved, do not use
0
0
Descrambler disabled
Rx Mode Register b5-3: Rx Modem Data format
These three bits select the Rx modem USART operating mode. The 1% and 2.3% overspeed
options apply to QAM modes only.
b5
b4
b3
1
1
1
Rx Special modes
1
1
0
Rx Start-stop mode, no overspeed
1
0
1
Rx Start-stop mode, +1% overspeed (1 in 8 missing Stop bits allowed)
1
0
0
Rx Start-stop mode, +2.3% overspeed (1 in 4 missing Stop bits allowed)
0
1
1
Reserved, do not use
0
1
0
Reserved, do not use
0
0
1
Reserved, do not use
0
0
0
Rx USART function disabled
Rx Mode Register b2-0: Rx Modem Data bits and Parity (Start-Stop modes)
In Start-stop mode these three bits select the number of data bits (plus any parity bit) in each
received character.
b2
b1
b0
1
1
1
8 data bits + parity
1
1
0
8 data bits
1
0
1
7 data bits + parity
1
0
0
7 data bits
0
1
1
6 data bits + parity
0
1
0
6 data bits
0
0
1
5 data bits + parity
0
0
0
5 data bits
© 2005 CML Microsystems Plc
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CMX869A
Rx Mode Register b2-0: Rx Modem Data bits and Parity (Special modes)
When b5-3 = 111 bits 2-0 select special receive modes as below:
b2
b1
b0
1
1
1
Synchronous, received bits transferred directly to Rx Data Register
1
1
0
HDLC mode
1
0
1
Reserved, do not use.
1
0
0
Reserved, do not use.
0
1
1
Reserved, do not use.
0
1
0
Reserved, do not use.
0
0
1
Reserved, do not use.
0
0
0
Reserved, do not use.
Rx Mode Register b2-0: Tones Detect mode
In Tones Detect Mode (Rx Mode Register b15-12 = 0001) b8-3 should be set to 000000.
Bits 2-0 select the detector type.
b2
b1
b0
1
1
1
Reserved, do not use.
1
1
0
Reserved, do not use.
1
0
1
Reserved, do not use.
1
0
0
Programmable Tone Pair Detect
0
1
1
Call Progress Detect
0
1
0
2100, 2225Hz Answer Tone Detect
0
0
1
DTMF Detect
0
0
0
Disabled
6.5
QAM AUTO Modem Command Register
QAM AUTO Modem Command Register: 16-bit write-only.
Bit:
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
C-BUS address $EA
5
4
3
2
1
0
Command
Protocol/Bit Rate
The V.22, V.22 bis, V.32, V.32 bis QAM AUTO modem is controlled by writing the commands listed below
to this register. B15-6 should all be cleared to 0. These commands will not take effect unless both Tx and
Rx Mode Registers have both been set to QAM AUTO modem mode. This register should only be written
to when b13 (Programming Flag bit) of the Status Register is 1.
Bit:
b5
0
F
F
F
1
b4
0
0
1
1
0
b3
0
1
0
1
0
b2 b1 b0
0
0
0
Max bitrate
Max bitrate
Max bitrate
Max bitrate
Command
Stop modem
Initiate retrain
Start automodem in calling mode
Start automodem in answer mode
Initiate rate re-negotiation
F is the fast training flag bit:
In V.22 or V.22 bis AUTO modes: If F is set to 1 in a ‘start automodem in answer mode’
command the 2100Hz answer tone will not be transmitted. The F bit has no effect in other
commands.
In V.32 or V.32 bis AUTO modes: If F is set to 1 a faster but less accurate echo cancellation
training algorithm is used.
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CMX869A
The ‘Max bitrate’ field defines the maximum bitrate that will be allowed by the modem during rate
negotiations.
Bit:
Max bitrate
b2 b1 b0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
bps
14400
12000
9600
9600
7200
4800
2400
1200
Protocol
V.32 bis
V.32 bis
V.32 / V.32 bis (with Trellis coding)
V.32 (no Trellis coding)
V.32 bis
V.32 / V.32 bis
V.22 bis
V.22 / V.22 bis
For most applications a connection can be established by ensuring that the Tx and Rx Mode registers
have been set to QAM AUTO modem mode and that the Status Register b13 = 1 then writing a ‘Start
automodem (calling or answer mode)’ command with the Max bitrate field set to 14400bps. The
CMX869A will automatically attempt to execute the entire start-up procedure as described in V.32 bis,
including the V.25 automatic answering sequence, receiver training and rate negotiation. Significant
events occurring during this process will be reported in the QAM AUTO Modem Status Register.
When a data connection has been established b3-0 of the QAM AUTO Modem Status Register will show
a value of between 1000 and 1111, indicating the negotiated bit rate. Following a sucessful connection,
the SNR value should be monitored by the host to determine if a re-train or rate re-negotiation is required,
should the line conditions deteriorate.
The CMX869A will automatically respond to V.32/V.32 bis retrain and rate re-negotiation requests from
the distant modem; alternatively the ‘Initiate retrain’ and ‘Initiate rate re-negotiation’ commands can be
used to initiate such requests. In both cases the progress of the retrain or rate re-negotiation will be
reported in the QAM Modem Status Register. If the rate re-negotiation is unsuccessful with the maximum
bit rate set to 4800 baud or above, re-initiate the rate re-negotiation with the maximum bit rate set to 2400
baud (V.22bis) or less.
6.6
Tx Data Register
Tx Data Register: 8 or 16-bit write-only.
C-BUS addresses $E3 and $E4
This register may be set to operate in 8 or 16-bit mode by b10 of the General Control Register. This
setting should not be changed once data transmission has started.
1-character mode (General Control Register b10 = 0). C-Bus addresses $E3 and $E4
Bit:
7
6
5
4
3
2
1
0
Byte to be transmitted
2-character mode (General Control Register b10 = 1). C-Bus address $E3 only
Bit:
15
14
13
12
11
10
9
8
7
First byte to be transmitted
6
5
4
3
2
1
0
Second byte to be transmitted
This register should only be written to when the Tx Data Ready bit of the Status Register is set to 1.
In Synchronous Tx data mode all 8 bits of a byte are transmitted, bit 0 of each byte being transmitted first.
In Tx Start-Stop modes the specified number of data bits will be taken from the byte in the Tx Data
Register (b0 of the byte first). A Start bit, a Parity bit (if required) and Stop bit(s) will be added
automatically.
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CMX869A
C-BUS address $E3 should normally be used, $E4 has special functions depending on the setting of b10
of the General Control Register:
If General Control Register b10 = 0 (1-character mode) then address $E4 is used to implement
the V.14 overspeed transmission requirement in Start-Stop mode, see section 5.1.
If General Control Register b10 = 1 (2-character mode) then a single character can be
transmitted, say at the end of a message, by writing it as a single byte to address $E4. V.14
operation is not supported in this mode.
6.7
Rx Data Register
Rx Data Register: 8 or 16-bit read-only.
C-BUS address $E5
This register may be set to operate in 8 or 16-bit mode by b10 of the General Control Register (note: this
setting is only actioned following a reset or power-on).
1-character mode (General Control Register b10 = 0).
Bit:
7
6
5
4
3
2
1
0
Received byte/character
2-character mode (General Control Register b10 = 1).
Bit:
15
14
13
12
11
10
9
8
7
6
First received byte/character
5
4
3
2
1
0
Second received byte/character
In Synchronous and HDLC Rx data modes each byte contains 8 received data bits, b0 of the byte holding
the earliest received bit, b7 the latest.
In Start-Stop modes each byte contains the specified number of data bits from a received character, b0 of
the byte holding the first received bit. Unused bits are set to 0.
In HDLC mode, the FCS will be output in this register following the last received data character.
6.8
Status Register
Status Register: 16-bit read-only.
C-BUS address $E6
Bits 13-0 of this register are cleared to 0 by a General Reset command or when b7 (Reset) of the General
Control Register is 1, or while b8 (Power-Up) of the General Control Register is 0.
Bit:
15
14
13
12
11
IRQ
RD
PF
TxD
TxU
10
9
8
7
6
5
4
3
2
1
0
See below for uses of these bits
The meanings of the Status Register bits 10-0 depend on the receive mode.
Status Register bits 15-11: All modes
b15
b14
b13
b12
b11
IRQ.
Set to 1 on Ring Detect
Programming Flag bit. See 6.10
Set to 1 on Tx data ready. Cleared by write to Tx Data Register
Set to 1 on Tx data underflow. Cleared by write to Tx Data Register
© 2005 CML Microsystems Plc
29
IRQ
Mask bit
b6
b5
b4
b3
b3
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
Status Register bits 10-0: Rx Tones Detect modes
b10
Set to 1 when energy is detected in Call Progress band or when both
programmable tones are detected
0
0
Set to 1 when 2100Hz answer tone or when the second programmable
tone is detected
Set to 1 when 2225Hz answer tone or when the first programmable tone
is detected
Set to 1 when DTMF code is detected
0
Rx DTMF code b3, see table following
Rx DTMF code b2
Rx DTMF code b1
Rx DTMF code b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Status Register bits 10-7: Rx FSK Modem modes
b10
b9
b8
b7
1 while energy is detected in Rx modem signal band
1 while ‘1010..’ or ‘11001100..’ S1 pattern is detected
See following table
See following table
b8
b7
Descrambler disabled
1
1
-
1
0
0
1
Continuous unscrambled 0s
Continuous unscrambled 1s
0
0
-
b8
b7
0
Set to 1 by modem event. Cleared by read of QAM modem Status
Register
Set to 1 when V.14 ‘break’ signal detected in Start-Stop mode
0
Status Register bits 6-0: All Rx Modem modes
b6
b5
b4
b3
b2
b1
b0
Set to 1 on Rx data ready. Cleared by read from Rx Data Register
Set to 1 on Rx data overflow. Cleared by read from Rx Data Register
Set to 1 on Rx UART framing error or HDLC FCS error
Start-Stop mode: set to 1 if Rx character has even parity (first character if
in 2-character mode)
HDLC mode: set to 1 when last byte (FCS) of HDLC packet is received
Start-Stop mode: 1 if second Rx character has even parity (2-character
mode)
Set to 1 if Rx Data Register contains 2 characters (2-character mode)
FSK frequency demodulator output (0 in QAM modes)
© 2005 CML Microsystems Plc
b1
b1
b1
b0
b0
IRQ
Mask bit
b2
b1
b1
b1
Descrambler enabled
(DPSK/QAM MANUAL
modes only)
Continuous scrambled 1s
(see note)
Continuous scrambled 0s
Continuous unscrambled
1s
-
Status Register bits 10-7: QAM AUTO MODEM modes
b10
b9
IRQ
Mask bit
b2
30
IRQ
Mask bit
b2
b1
b1
b1
IRQ
Mask bit
b0
b0
-
-
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
Notes:
When the descrambler is enabled then detection of continuous unscrambled 1s will inhibit the
continuous scrambled 1s detector.
The IRQ Mask Bit column shows the corresponding IRQ Mask bits in the General Control
Register. A 0 to 1 transition on any of the Status Register bits 14-5 will cause the IRQ bit 15 to be
set to 1 if the corresponding IRQ Mask bit is 1. The IRQ bit is cleared by a read of the Status
Register or a General Reset command or by setting b7 or b8 of the General Control Register to 1.
The IRQN output pin will be pulled low (to VSS) when the IRQ bit of the Status Register and the
IRQNEN bit (b6) of the General Control Register are both set to 1.
The operation of the FSK data demodulator and pattern detector circuits within the CMX869A do
NOT depend on the state of the Rx energy detect function.
Figure 9a Operation of Status Register bits 5-10
Changes to Status Register bits caused by a change of Tx or Rx operating mode can take up to
150µs to take effect.
The Ring Detect bit (b14) continues to operate in Powersave mode or when the Reset bit (b7) of
the General Control Register is 1. The Ring Detect bit follows the inverted state of the RDN input
pin. An interrupt is only generated as a result of a negative transition on the RDN pin, if General
Control Register bits 5 and 6 are set to 1.
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CMX869A
In Rx FSK modem modes bit 0 will show the output of the frequency demodulator, updated at 8
times the nominal data rate.
Figure 9b Operation of Status Register in DTMF Rx Mode
b3
b2
b1
b0
Low frequency (Hz)
High frequency
(Hz)
Keypad symbol
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
941
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
1633
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
D
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
Received DTMF Code: b3-0 of Status Register
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6.9
CMX869A
QAM AUTO Modem Status Register
QAM AUTO Modem Status Register: 16-bit read-only.
C-BUS address $EB
This register should only be read from when b13 (Programming Flag bit) of the Status Register is 1.
Bit:
15
14
13
12
Messages
11
10
9
8
7
0
0
0
6
5
4
3
SNR
2
1
0
Mode
QAM AUTO Modem Status Register b15-10: Messages
b15 b14 b13 b12 b11 b10
1
1
1
Bit Rate
R5 received
1
1
0
Bit Rate
R4 received
1
0
1
Bit Rate
R3 received
1
0
0
Bit Rate
R2 received
0
1
1
Bit Rate
R1 received
0
1
0
1
1
1
Rate negotiation request detected
0
1
0
1
1
0
Retrain request detected
0
1
0
1
0
1
Emergency retrain started
0
1
0
1
0
0
Carrier lost
0
1
0
0
1
1
V.32 preamble detected
0
1
0
0
1
0
S1 detected
0
1
0
0
0
1
SB1 detected
0
1
0
0
0
0
USB1 detected
0
0
1
1
1
1
2100Hz detected
Other combinations of b15-10
unused
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CMX869A
Bit Rate field of Messages (see above)
b12
b11
b10
1
1
1
14400
V.32 bis
1
1
0
12000
V.32 bis
1
0
1
9600
V.32 / V.32 bis (with Trellis coding)
1
0
0
9600
V.32 (no Trellis coding)
0
1
1
7200
V.32 bis
0
1
0
4800
V.32 / V.32 bis
0
0
1
2400
V.22 bis
0
0
0
1200
V.22 / V.22 bis
QAM AUTO Modem Status Register b9-7: Unused (000)
QAM AUTO Modem Status Register b6-4: Signal to Noise
b6
b5
b4
1
1
1
Very good; could increase rate or retrain
1
1
0
Good
1
0
1
Normal
1
0
0
Poor
0
1
1
Bad; receiver will have a high error rate
0
1
0
Really bad; should decrease data rate or retrain
0
0
1
Unused
0
0
0
SNR not yet determined
QAM AUTO Modem Status Register b3-0: Operating Mode
b3
b2
b1
b0
1
1
1
1
14400 bps V.32 bis
1
1
1
0
12000 bps V.32 bis
1
1
0
1
9600 bps V.32 / V.32 bis (with Trellis coding)
1
1
0
0
9600 bps V.32 (no Trellis coding)
1
0
1
1
7200 bps V.32 bis
1
0
1
0
4800 bps V.32 / V.32 bis
1
0
0
1
2400 bps V.22 bis
1
0
0
0
1200 bps V.22 / V.22 bis
0
1
1
1
Unused
0
1
1
0
Unused
0
1
0
1
Unused
0
1
0
0
Training / Rate negotiation
0
0
1
1
Transmitting 2100Hz answer tone
0
0
1
0
Tx silence, Rx idle
0
0
0
1
Tx idle, Rx waiting
0
0
0
0
Idle
An update to the Messages status (b15 – b10) or any change in SNR or Mode status (b6 – b0) will cause
b9 of the main Status Register to be set to 1.
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6.10
CMX869A
Programming Register
Programming Register : 16-bit write-only.
C-BUS address $E8
This register is used to program the transmit and receive programmed tone pairs by writing appropriate
values to RAM locations within the CMX869A. Note that these RAM locations are cleared by Powersave
or Reset.
The Programming Register should only be written to when the Programming Flag bit (b13) of the Status
Register is 1. The act of writing to the Programming Register clears the Programming Flag bit. When the
programming action has been completed (normally within 150µs) the CMX869A will set the bit back to 1.
When programming Transmit or Receive Tone Pairs, do not change the Transmit or Receive Mode
Registers until programming is complete and the Programming Flag bit has returned to 1.
Transmit Tone Pair Programming
4 transmit tone pairs (TA to TD) can be programmed.
The frequency (max 3.4kHz) and level must be entered for each tone to be used.
Single tones are programmed by setting both level and frequency values to zero for one of the pair.
Programming is done by writing a sequence of seventeen 16-bit words to the Programming Register. The
first word should be 32768 (8000 hex), the following 16-bit words set the frequencies and levels and are
in the range 0 to 16383 (0-3FFF hex)
Word
1
2
3
4
5
6
7
----16
17
Tone Pair
TA
TA
TA
TA
TB
TB
----TD
TD
Value written
32768
Tone 1 frequency
Tone 1 level
Tone 2 frequency
Tone 2 level
Tone 1 frequency
Tone 1 level
------------------Tone 2 frequency
Tone 2 level
The Frequency values to be entered are calculated from the formula:
Value to be entered = desired frequency (Hz) * 3.414
i.e. for 1kHz the value to be entered is 3414 (or 0D56 in Hex).
The Level values to be entered are calculated from the formula:
Value to be entered = desired Vrms * 93780 / AVDD
i.e. for 0.5Vrms at AVDD = 3.3V, the value to be entered is 14209 (3781 in Hex)
Programming a notone pair is done by writing zero to all four tone pair words. On power-up or after a
reset, the tone pairs TA-TC are set to notone, and TD is set to generate 2130Hz + 2750Hz at
approximately –18dBm (100mVrms) each. Unprogrammed tone pairs retain their previous values.
Allowance should be made for the transmit signal filtering in the CMX869A which attenuates the output
signal for frequencies above 2kHz, by 0.25dB at 2.5kHz, by 1dB at 3kHz, and by 2.2dB at 3.4kHz.
© 2005 CML Microsystems Plc
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D/869A/2
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CMX869A
Receive Tone Pair Programming
The Programmable Tone Pair Detector is implemented as shown in Figure 10a. The filters are 4th order
IIR sections. The frequency detectors measure the time taken for a programmable number of complete
input signal cycles and compare this time against programmable upper and lower limits.
Figure 10a Programmable Tone Pair Detector
Figure 10b Filter Implementation
Programming is done by writing a sequence of twenty-seven 16-bit words to the Programming Register.
The first word should be 32769 (8001 hex), the following twenty-six 16-bit words set the frequencies and
levels and are in the range 0 to 32767 (0000-7FFF hex).
Word Value written
Word Value written
1
32769
2
Filter #1 coefficient b21
15
Filter #2 coefficient b21
3
Filter #1 coefficient b11
16
Filter #2 coefficient b11
4
Filter #1 coefficient b01
17
Filter #2 coefficient b01
5
Filter #1 coefficient a21
18
Filter #2 coefficient a21
6
Filter #1 coefficient a11
19
Filter #2 coefficient a11
7
Filter #1 coefficient b22
20
Filter #2 coefficient b22
8
Filter #1 coefficient b12
21
Filter #2 coefficient b12
9
Filter #1 coefficient b02
22
Filter #2 coefficient b02
10
Filter #1 coefficient a22
23
Filter #2 coefficient a22
11
Filter #1 coefficient a12
24
Filter #2 coefficient a12
12
Freq measurement #1 ncycles
25
Freq measurement #2 ncycles
13
Freq measurement #1 mintime
26
Freq measurement #2 mintime
14
Freq measurement #1 maxtime
27
Freq measurement #2 maxtime
The coefficients are entered as 15-bit signed (two’s complement) integer values (the most significant bit of
the 16-bit word entered should be zero) calculated as 8192 * coefficient value from the user’s filter design
program (i.e. this allows for filter design values of -1.9999 to +1.9999).
© 2005 CML Microsystems Plc
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CMX869A
The design of the IIR filters should make allowance for the fixed receive signal filtering in the CMX869A
which has a low pass characteristic above 1.5kHz, of 0.4dB at 2kHz, 1.2dB at 2.5kHz, 2.6dB at 3kHz and
4.1dB at 3.4kHz.
‘ncycles’ is the number of signal cycles for the frequency measurement.
‘mintime’ is the smallest acceptable time for ncycles of the input signal expressed as the number of
9.6kHz timer clocks. i.e. ‘mintime’ = 9600 * ncycles / high frequency limit
‘maxtime’ is the highest acceptable time for ncycles of the input signal expressed as the number of
9.6kHz timer clocks. i.e. ‘maxtime’ = 9600 * ncycles / low frequency limit
The level detectors include hysteresis. The threshold levels - measured at the 2 or 4-wire line with unity
gain filters, using the line interface circuits described in section 4.3, 1.0 dB line coupling transformer loss
and with the Rx Gain Control block set to 0dB - are nominally:
‘Off’ to ‘On’
-42.0dBm
‘On’ to ‘Off’
-44.5dBm
Note that if any changes are made to the programmed values while the CMX869A is running in
Programmed Tone Detect mode they will not take effect until the CMX869A is next switched into
Programmed Tone Detect mode.
On power-up or after a reset, the programmable tone pair detector is set to act as a simple 2130Hz +
2750Hz detector.
© 2005 CML Microsystems Plc
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D/869A/2
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7.
CMX869A
Application Notes
Simple Auto-modem connect sequence
This sequence will set up a V32bis Automodem call between two directly connected CMX869A’s (ie: NOT
routing through a telephone line. This is used to demonstrate the Automodem capability).
wr
wr
wr
wr
wr
rd
wr
rd
CBUS value(dec) value(hex) value(dec) value(hex)
address
calling modem
answering modem
01
reset
E0
320
140
320
140 power up relevant sections
E1
61462
F016
61462
F016 set tx mode and level to QAM, -10dB
E3
61494
F036
61494
F036 set rx mode and level to QAM, -10dB
offhook
offhook
If needed
EA
23
17
31
1F Start auto modem mode
Connect in progress
...wait a bit
EB?
48239
BC6F
19460
4C04 read back the QAM status
Now send some data
E4
66
42
66
42 send ASCII char 'B'
E5?
66
42
66
42 should receive ASCII char 'B'
V22bis Manual connect sequence
See Application Notes on the CML website.
© 2005 CML Microsystems Plc
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D/869A/2
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8.
Performance Specification
8.1
Electrical Performance
CMX869A
8.1.1 Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Supply (AVDD - AVSS) or (DVDD - DVSS)
Voltage on any pin (except VDEC) to AVSS or DVSS
Voltage between AVSS and DVSS
Voltage between AVDD and DVDD
Current into or out of AVSS, DVSS, AVDD or DVDD pins
Current into RDRVN pin (RDRVN pin low)
Current into or out of any other pin
Min.
-0.3
-0.3
-50
-300
-50
-20
D2 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
E2 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
P4 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
8.1.2
-55
-40
-55
-40
-55
-40
Max.
+4.0
VDD + 0.3
+50
+300
+50
+50
+20
Units
V
V
mV
mV
mA
mA
mA
Max.
1000
13
+125
+85
Units
mW
mW/°C
°C
°C
Max.
400
5.3
+125
+85
Units
mW
mW/°C
°C
°C
Max.
1000
13
+125
+85
Units
mW
mW/°C
°C
°C
Max.
3.6
25
+85
Units
V
ms
°C
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Supply (AVDD - AVSS) and (DVDD - DVSS)
Supply rise time (10% to 90%)
Operating Temperature
© 2005 CML Microsystems Plc
Min.
3.0
-40
39
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
8.1.3
CMX869A
Operating Characteristics
For the following conditions unless otherwise specified:
VDD = AVDD = DVDD = 3.0V to 3.6V at Tamb = -40 to +85°C; VSS = AVSS = DVSS;
Xtal Frequency = 6.144MHz ± 0.005% (50ppm);
0dBm corresponds to 775mVrms. General Control Register bit 14 = 0 (High Rx Gain turned off).
DC Parameters
IDD (Powersave mode)
(Reset but not powersave)
(Running, AVDD = DVDD = 3.3V)
Logic '1' Input Level
Logic '0' Input Level
Logic Input Leakage Current (Vin = 0 to DVDD),
(excluding XTAL/CLOCK input)
Output Logic '1' Level (lOH = 0.6 mA)
Output Logic '0' Level (lOL = -1.0 mA)
IRQN O/P 'Off' State Current (Vout = VDD)
RDN pin Schmitt trigger input high-going
threshold (Vthi) (see Figure 11)
RDN pin Schmitt trigger input low-going
threshold (Vtlo) (see Figure 11)
RDRVN ‘ON’ resistance to DVSS (DVDD= 3.3V)
RDRVN ‘OFF’ resistance to DVDD (DVDD= 3.3V)
Notes:
Notes
1, 2
1, 3
1
4
4
Min.
70%
-1.0
Typ.
20
3.0
8.6
-
Max.
100
5.0
13.0
30%
+1.0
Units
µA
mA
mA
DVDD
DVDD
µA
80%
-1.0
0.56 VDD
-
VDD
V
µA
V
0.44 VDD
-0.6
-
-
+0.4
+1.0
0.56 VDD
+0.6
0.44 VDD
50
1170
70
3000
Ω
Ω
V
1. At 25°C, not including any current drawn from the CMX869A pins by external circuitry
other than X1, C5 and C6.
2. All logic inputs at DVSS except CSN input which is at DVDD.
3. General Control Register b8 and b7 both set to 1.
4. Excluding RDN pin.
2.5
2
Vthi
Vtlo
1.5
Vin
1
0.5
0
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Vdd
Figure 11 Typical Schmitt Trigger Input Voltage Thresholds vs. VDD
© 2005 CML Microsystems Plc
40
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
XTAL/CLOCK Input
(timings for an external clock input)
'High' Pulse Width
'Low' Pulse Width
Notes
Transmit Output Level
Modem and Single Tone modes
DTMF mode, Low Group tones
DTMF: level of High Group tones wrt Low Group
Tx output buffer gain control accuracy
Tx output impedance (TXA or TXAN)
Notes
5
5
5
5
Notes:
Min.
Typ.
Max.
Units
60
60
-
-
ns
ns
Min.
-1.5
0.5
+1.0
-0.25
Typ.
-0.5
1.5
+2.0
6.0
Max.
0.5
2.5
+3.0
+0.25
Units
dBm
dBm
dB
dB
ohm
5. Measured between TXA and TXAN pins with Tx Level Control gain set to 0dB, 1.2kΩ load
between TXA and TXAN, at AVDD = 3.3V (levels are proportional to AVDD - see section
4.3). Level measurements for all modem modes are performed with random transmitted
data and without any guard tone. 0dBm = 775mVrms. DTMF twist set to +2.0dB.
0
-10
Bell 202
-20
-30
dBm
-40
-50
-60
-70
10
100
1000
10000
100000
Hz
Figure 12 Maximum Out of Band Tx Line Energy Limits (see note 6)
Notes:
6. Measured on the 2 or 4-wire line using the line interface circuits described in section 4.3
with the Tx line signal level set to -10dBm for any modem mode or single tones, -6dBm
and -8dBm for DTMF tones. Excludes any distortion due to external components such as
the line coupling transformer.
© 2005 CML Microsystems Plc
41
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
Rx Modem Energy Detector (FSK modes)
Detect threshold (‘Off’ to ‘On)
Undetect threshold (‘On’ to ‘Off’)
Hysteresis
Detect (‘Off’ to ‘On’) response time
300 and 1200 baud FSK modes
150 and 75 baud FSK modes
Undetect (‘On’ to ‘Off’) response time
300 and 1200 baud FSK modes
150 and 75 baud FSK modes
Notes
7, 8
7, 8
7, 8
Min.
-48.0
2.0
Typ.
-
Max.
-43.0
-
Units
dBm
dBm
dB
7, 8
7, 8
8.0
16.0
-
30.0
60.0
ms
ms
7, 8
7, 8
10.0
20.0
-
40.0
80.0
ms
ms
Rx Answer Tone Detectors
Detect threshold (‘Off’ to ‘On)
Undetect threshold (‘On’ to ‘Off’)
Detect (‘Off’ to ‘On’) response time
Undetect (‘On’ to ‘Off’) response time
2100Hz detector
‘Will detect’ frequency
‘Will not detect’ frequency
2225Hz detector
‘Will detect’ frequency
‘Will not detect’ frequency
Notes
7,9
7,9
7,9
7,9
Min.
-48.0
30.0
7.0
Typ.
33.0
18.0
Max.
-43.0
45.0
25.0
Units
dBm
dBm
ms
ms
2050
-
-
2160
2000
Hz
Hz
2160
2335
-
2285
-
Hz
Hz
Rx Call Progress Energy Detector
Bandwidth (-3dB points) See Figure 6
Detect threshold (‘Off’ to ‘On)
Undetect threshold (‘On’ to ‘Off’)
Detect (‘Off’ to ‘On’) response time
Undetect (‘On’ to ‘Off’) response time
Notes
Min.
275
-42.0
30.0
6.0
Typ.
36.0
8.0
Max.
665
-37.0
45.0
50.0
Units
Hz
dBm
dBm
ms
ms
7,10
7,10
7,10
7,10
Notes: 7. Rx 2 or 4-wire line signal level with Rx Gain Control block set to 0dB and external components
of section 4.3 set so that level at RXAFB pin is 3.6dB below the line signal level. Measured at
AVDD = 3.3V.
8. Thresholds and times measured with continuous binary ‘1’ for all FSK modes. Times measured
with signal switched between off and -33dBm
9. ‘Typical’ value refers to 2100Hz or 2225Hz signal switched between off and -33dBm. Times
measured wrt. received line signal.
10. ‘Typical’ values refers to 400Hz signal switched between off and -33dBm.
© 2005 CML Microsystems Plc
42
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
DTMF Decoder
Valid input signal levels
(each tone of composite signal)
Not decode level
(either tone of composite signal)
Twist = High Tone/Low Tone
Frequency Detect Bandwidth
Frequency Not Detect Bandwidth
Max level of low frequency noise (i.e dial tone)
Interfering signal frequency <= 550Hz
Interfering signal frequency <= 450Hz
Interfering signal frequency <= 200Hz
Max. noise level wrt. signal
DTMF detect response time
DTMF de-response time
Status Register b5 high time
‘Will Detect’ DTMF signal duration
‘Will Not Detect’ DTMF signal duration
Pause length detected
Pause length ignored
Notes:
Notes
Min.
Typ.
Max.
Unit
7
-30.0
-
0.0
dBm
7
-11.0
±1.8
-
-
-36.0
16.0
±3.5
dBm
dB
%
%
14.0
40.0
30.0
-
25.0
-
0.0
10.0
20.0
-10.0
40.0
30.0
15.0
dB
dB
dB
dB
ms
ms
ms
ms
ms
ms
ms
Min.
10.0
Typ.
12
12
11
11
11
11,14
13
13
11. Referenced to DTMF tone of lower amplitude
12. Under conditions of the Mitel CM7291 test tape
13. See figure 9b for timing information
14. Flat Gaussian Noise in 300-3400Hz band.
Receive Input Amplifier
Input impedance (at 100Hz)
Notes
Open loop gain (at 100Hz)
Rx Gain Control Block accuracy
© 2005 CML Microsystems Plc
Max.
10000
-0.25
43
+0.25
Units
Moh
m
V/V
dB
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
C-BUS Timings (See Figure 13)
tCSE
CSN-Enable to Clock-High time
tCSH
Last Clock-High to CSN-High time
tLOZ
Clock-Low to Reply Output enable
time
tHIZ
CSN-High to Reply Output 3-state time
tCSOFF
CSN-High Time between transactions
tNXT
Inter-Byte Time
tCK
Clock-Cycle time
tCH
Serial Clock-High time
tCL
Serial Clock-Low time
tCDS
Command Data Set-Up time
tCDH
Command Data Hold time
Reply Data Set-Up time
tRDS
tRDH
Reply Data Hold time
Notes
Min.
100
100
0.0
Typ.
-
Max.
-
Units
ns
ns
ns
1.0
200
200
100
100
75.0
25.0
50.0
0.0
-
1.0
-
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Maximum 30pF load on each C-BUS interface line.
Figure 13 C-BUS Timing
© 2005 CML Microsystems Plc
44
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
8.2
CMX869A
Packaging
Figure 14a 24-pin SOIC (D2) Mechanical Outline: Order as part no. CMX869AD2
Figure 14b 24-pin TSSOP (E2) Mechanical Outline: Order as part no. CMX869AE2
© 2005 CML Microsystems Plc
45
D/869A/2
Low Power V.32 bis Modem with Auto / Manual Connect
CMX869A
Figure 14c 24-pin DIL (P4) Mechanical Outline: Order as part no. CMX869AP4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device
damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No
IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and
this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure
compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
www.cmlmicro.com
For FAQs see: www.cmlmicro.com/products/faqs/
For a full data sheet listing see: www.cmlmicro.com/products/datasheets/download.htm
For detailed application notes: www.cmlmicro.com/products/applications/
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