GSA MIXED-SIGNAL/RF PDK CHECKLIST Checklist Form Version 3.0 Foundry and Support Contact Information Foundry ams AG Process 0.35µm CMOS - C35xx – hitkit 4.10 Date 09/2012 SPICE Model Support Contact Name Thomas Moerth Phone +43 3136/500 31587 Email [email protected] EDA Tools Supported and Verified for Use with this PDK Type Vendor and Tool Version Schematic Cadence Composer IC6.1.5.500.10 Simulation Control Cadence Analog Design Environment IC6.1.5.500.10 Circuit Simulator (A) Cadence Spectre Cadence Ultrasim Synopsys HSPICE MMSIM 10.1.1.279.isr17 MMSIM 10.1.1.279.isr17 2009.09 Layout Editor Cadence Virtuoso-XL Cadence Chip Assembly Router IC6.1.5.500.10 ICC 11.241 DRC Checker Cadence Assura Mentor Calibre 4.1_USR2_HF14 2012.2 LVS Checker Cadence Assura Mentor Calibre 4.1_USR2_HF14 2012.2 Parasitic Extractor Cadence Assura Mentor Calibre 4.1_USR2_HF14 2012.2 Checklist Form Version 3.0 Page 1 PDK Details Option Data Database OpenAccess PCell Language Skill Callback Language Skill Layout Transfer Format GDSII If Database is OpenAccess Reference PDK Version hitkit 3.80 C35 Foundry Process Documents Document Document Number & Title Design Manual (Devices) - See individual documents below Electrical Parameters ENG-182: C35 CMOS Process Parameters ENG-327: C35 30V CMOS Module Process Parameters ENG-364: C35 CMOS Schottky Barrier Diode PP Design Layout Rules ENG-183: C35 CMOS Design Rules ENG-326: C35 30V CMOS Module Design Rules ENG-365: C35 CMOS Schottky Barrier Diode DR SPICE Model Library ENG-182: C35 CMOS Process Parameters ENG-327: C35 30V CMOS Module Process Parameters ENG-364: C35 CMOS Schottky Barrier Diode PP SPICE Model Checklist GSA Spice Model Checklist C35 RF Parameters/Modeling ENG-188: C35 CMOS RF SPICE Models Noise Model Revision Date 6.0 2.0 1.0 Dec 2008 Aug 2009 Nov 2009 all 9.0 6.0 2.0 May 2011 Oct 2012 Nov 2009 4 6.0 2.0 1.0 Dec 2008 Aug 2009 Nov 2009 1.2 Jun 2012 All 5.0 Nov 2009 ENG-189: C35 CMOS Noise Parameters All 6.0 Jun 2011 Matching Models ENG-228: C35 CMOS Matching Parameters ENG-339: C35 30V CMOS Matching Parameters All 3.0 1.0 Nov 2009 Apr 2009 ESD Guidelines ENG-236: 0.35u ESD Design Rules 3.0 Oct 2012 DRC Runset ENG-183: C35 CMOS Design Rules ENG-326: C35 30V CMOS Module Design Rules ENG-365: C35 CMOS Schottky Barrier Diode DR 4 9.0 6.0 2.0 May 2011 Oct 2012 Nov 2009 LVS Runset ENG-183: C35 CMOS Design Rules ENG-326: C35 30V CMOS Module Design Rules ENG-365: C35 CMOS Schottky Barrier Diode DR 5 9.0 6.0 2.0 May 2011 Oct 2012 Nov 2009 Parasitic Extract Runset ENG-182: C35 CMOS Process Parameters ENG-327: C35 30V CMOS Module Process Parameters ENG-364: C35 CMOS Schottky Barrier Diode PP 6.0 2.0 1.0 Dec 2008 Aug 2009 Nov 2009 DFM Runset ENG-301: C35 CMOS DFM Rules 5.0 Jan 2012 Layer Map ENG-183: C35 CMOS Design Rules ENG-326: C35 30V CMOS Module Design Rules ENG-365: C35 CMOS Schottky Barrier Diode DR 9.0 6.0 2.0 May 2011 Oct 2012 Nov 2009 Checklist Form Version 3.0 Section 3 Page 2 modelFile cellName modelName symbol sym_term cdfParam spectre hspiceD layout pcell auCdl auLvs C35 Device Table bip.scs lat2 lat2 y 5 1 y y y n y y bip.scs vert10_4 vert10 y 4 1 y y y n y y cap.scs cpoly cpoly y 2 11 y y y y y y cap.scs cpolyc cpoly y 3 6 n n y y n n cmos53.scs ncapfet modn y 4 7 y y n n n y cmos53.scs nmos4 modn y 4 14 y y y y y y cmos53.scs nmosh4 modnh y 4 3 y y n n y y cmos53.scs nmosm4 modnm y 4 13 y y y y y y cmos53.scs nmosmh4 modnmh y 4 3 y y n n y y cmos53.scs pcapfet modp y 3 7 y y n n y y cmos53.scs pmos4 modp y 4 13 y y y y y y cmos53.scs pmosm4 modpm y 4 13 y y y y y y cmos53.scs subdiode nd y 2 2 y y n n y y cmos53.scs welldiode pd y 2 2 y y n n y y esddiode.scs esdfdn5 esdfdn5 y 2 3 y y y y y y esddiode.scs esdfdp5 esdfdp5 y 3 3 y y y y y y esddiode.scs esdgcn5 esdgcn5 y 2 3 y y y y y y esddiode.scs esdgcp5 esdgcp5 y 3 3 y y y y y y res.scs nwd nwd y 2 2 y y n n y y res.scs pfuse rpoly1 y 2 11 y y n n y y res.scs pnwd nwd y 2 2 y y n n y y res.scs rdiffn3 rdiffn3 y 3 4 y y y y y y res.scs rdiffp3 rdiffp3 y 3 4 y y y y y y res.scs rnwell rnwell y 3 4 y y y y y y res.scs rpoly1 rpoly1 y 2 11 y y y y y y res.scs rpoly2 rpoly2 y 2 11 y y y y y y res.scs rpoly2p rpoly2p y 2 11 y y y y y y res.scs rpoly2ph rpoly2ph y 2 11 y y y y y y res.scs rpolyh rpolyh y 2 10 y y y y y y Important Disclosures Copyright© 2008 by GSA. All rights reserved. GSA grants a worldwide license to all PDK developers to add their data, contact information and logo to a copy of the GSA Mixed-Signal/RF PDK Checklist and distribute it to their partners, prospects and customers; however, all references to GSA, including GSA logo and GSA references may not be altered in any way. GSA makes no claims to the accuracy of the data entered on a GSA Mixed-Signal/RF PDK Checklist. Checklist Form Version 3.0 Page 3