GD25Q128C GD25Q128 DATASHEET 73 - 1 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Contents 1. FEATURES ................................................................................................................................................................ 44 2. GENERAL DESCRIPTION...................................................................................................................................... 5 3. MEMORY ORGANIZATION .................................................................................................................................... 77 4. DEVICE OPERATION .............................................................................................................................................. 8 5. DATA PROTECTION.............................................................................................................................................. 10 9 6. STATUS REGISTER............................................................................................................................................... 13 7. COMMANDS DESCRIPTION ............................................................................................................................... 15 7.1. WRITE ENABLE (WREN) (06H) ......................................................................................................................... 19 19 7.2. WRITE DISABLE (WRDI) (04H) ......................................................................................................................... 19 19 7.3. WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) .................................................................................. 20 20 7.4. READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .................................................................................. 21 21 7.5. WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H)................................................................................ 22 22 7.6. READ DATA BYTES (READ) (03H).................................................................................................................... 23 23 7.7. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................. 23 23 7.8. DUAL OUTPUT FAST READ (3BH)...................................................................................................................... 24 24 7.9. QUAD OUTPUT FAST READ (6BH) ..................................................................................................................... 24 24 7.10. DUAL I/O FAST READ (BBH) ............................................................................................................................. 25 25 7.11. QUAD I/O FAST READ (EBH)............................................................................................................................. 27 27 7.12. QUAD I/O WORD FAST READ (E7H) .................................................................................................................. 28 29 7.13. SET BURST WITH WRAP (77H) ........................................................................................................................... 30 31 7.14. PAGE PROGRAM (PP) (02H) ............................................................................................................................... 31 31 7.15. QUAD PAGE PROGRAM (32H)............................................................................................................................. 32 32 7.16. SECTOR ERASE (SE) (20H)................................................................................................................................. 33 33 7.17. 32KB BLOCK ERASE (BE) (52H) ....................................................................................................................... 34 34 7.18. 64KB BLOCK ERASE (BE) (D8H) ...................................................................................................................... 35 35 7.19. CHIP ERASE (CE) (60/C7H) ............................................................................................................................... 36 36 7.20. DEEP POWER-DOWN (DP) (B9H) ....................................................................................................................... 37 37 7.21. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH)........................................................ 38 38 7.22. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H)........................................................................................ 40 40 7.23. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H)...................................................................................... 41 41 7.24. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H) ..................................................................................... 41 41 7.25. READ IDENTIFICATION (RDID) (9FH)................................................................................................................ 42 42 7.26. PROGRAM/ERASE SUSPEND (PES) (75H) ........................................................................................................... 43 43 7.27. PROGRAM/ERASE RESUME (PER) (7AH) ........................................................................................................... 44 44 7.28. ERASE SECURITY REGISTERS (44H) ................................................................................................................... 45 45 7.29. PROGRAM SECURITY REGISTERS (42H).............................................................................................................. 46 46 7.30. READ SECURITY REGISTERS (48H)..................................................................................................................... 46 46 7.31. INDIVIDUAL BLOCK/SECTOR LOCK (36H)/UNLOCK (39H)/READ (3DH) ........................................................... 47 47 7.32. GLOBAL BLOCK/SECTOR LOCK (7EH) OR UNLOCK (98H) ................................................................................. 49 49 2 73 - 2 Rev.1.0 GD25Q128CxIGx 3.3V Uniform sector dual and quad serial flash 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C 7.33. SET READ PARAMETERS (C0H).......................................................................................................................... 51 51 7.34. BURST READ WITH WRAP (0CH)........................................................................................................................ 52 52 7.35. 52 ENABLE QPI (38H)............................................................................................................................................. 52 7.36. DISABLE QPI (FFH) ........................................................................................................................................... 53 53 7.37. ENABLE RESET (66H) AND RESET (99H)............................................................................................................ 53 53 7.38. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ................................................................................. 54 54 ELECTRICAL CHARACTERISTICS ................................................................................................................... 60 56 8. 8.1. POWER-ON TIMING....................................................................................................................................... 60 60 8.2. INITIAL DELIVERY STATE........................................................................................................................... 60 60 8.3. DATA RETENTION AND ENDURANCE ...................................................................................................... 60 60 8.4. LATCH UP CHARACTERISTICS ................................................................................................................... 60 60 8.5. ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 61 61 8.6. CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 61 61 8.7. DC CHARACTERISTICS................................................................................................................................. 62 62 8.8. AC CHARACTERISTICS................................................................................................................................. 63 63 ORDERING INFORMATION .................................................................................................................................66 66 9. 10. PACKAGE INFORMATION...............................................................................................................................67 67 10.1. 67 PACKAGE SOP8 208MIL ................................................................................................................................... 67 10.2. 68 PACKAGE VSOP8 208MIL................................................................................................................................. 68 10.3. PACKAGE SOP16 300MIL.................................................................................................................................. 69 69 10.4. PACKAGE DIP8 300MIL .................................................................................................................................... 70 70 10.5. PACKAGE WSON 8 (6*5MM) ............................................................................................................................. 71 71 10.6. PACKAGE WSON 8 (8*6MM) ............................................................................................................................. 72 72 10.7. PACKAGE TFBGA-24BALL (6*4 BALL ARRAY)................................................................................................ 73 73 73 -3 3 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 1. FEATURES � 128M-bit Serial Flash � Program/Erase Speed -16384K-byte -Page Program time: 0.6ms typical -256 bytes per programmable page -Sector Erase time: 50ms typical -Block Erase time: 0.2/0.3s typical � Standard, Dual, Quad SPI -Chip Erase time: 60s typical -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET# -Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET# � Flexible -Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Sector of 4K-byte -QPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Block of 32/64k-byte � Low � Architecture Power Consumption High Speed Clock Frequency -20mA maximum active current -104MHz for Standard and Dual SPI fast read with 30PF load -5uA maximum power down current -80MHz for Quad SPI and QPI fast read with 30PF load -Dual I/O Data transfer up to 208Mbits/s � (1) Advanced Security Features -Quad I/O Data transfer up to 320Mbits/s -3*256-Byte Security Registers With OTP Locks -QPI Mode Data transfer up to 320Mbits/s -Discoverable parameters(SFDP) register -Continuous Read With 8/16/32/64-byte Wrap � Software/Hardware Write Protection � -Write protect all/portion of memory via software Single Power Supply Voltage -Full voltage range:2.7~3.6V -Enable/Disable protection with WP# Pin -Top or Bottom, Sector or Block selection � Package Information -SOP8 (208mil) -VSOP8 (208mil) � Cycling endurance -SOP16 (300mil) -Minimum 100,000 Program/Erase Cycles -DIP8 (300mil) -WSON8 (6*8mm) � Data retention -WSON8 (6*5mm) -20-year data retention typical -TFBGA-24(6*4 ball array) 4 73 - 4 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 2. GENERAL DESCRIPTION The GD25Q128C (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#). The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of 320Mbits/s. CONNECTION DIAGRAM CS# 1 8 VCC CS# 1 8 SO 2 7 HOLD#/ RESET# SO 2 7 HOLD#/ RESET# WP# 3 6 SCLK WP# 3 6 SCLK VSS 4 5 SI VSS 4 5 Top View Top View VCC SI 8–LEAD WSON 8–LEAD SOP/VSOP/DIP Top View 4 NC VCC WP# HOLD#/ NC RESET# NC NC VSS NC SI NC NC NC SCLK CS# SO NC NC 3 2 1 NC NC NC NC NC NC A B C D E F 24-BALL TFBGA 5 73 - 5 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash HOLD# 1 16 SCLK VCC 2 15 SI RESET# 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC CS# 7 10 VSS SO 8 9 WP# Top View GD25Q128C 16-LEAD SOP PIN DESCRIPTION Pin Name I/O Description CS# I Chip Select Input SO (IO1) I/O Data Output (Data Input Output 1) WP# (IO2) I/O Write Protect Input (Data Input Output 2) Ground VSS SI (IO0) I/O Data Input (Data Input Output 0) SCLK I Serial Clock Input HOLD#/RESET# (IO3) I/O Hold or Reset Input (Data Input Output 3) Power Supply VCC BLOCK DIAGRAM WP#(IO2) Write Control Logic HOLD# RESET#(IO3) SCLK CS# SI(IO0) SO(IO1) SPI Command & Control Logic Write Protect Logic and Row Decode Status Register High Voltage Generators Page Address Latch/Counter Flash Memory Column Decode And 256-Byte Page Buffer Byte Address Latch/Counter 6 73 - 6 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 3. MEMORY ORGANIZATION GD25Q128C Each device has Each block has Each sector has Each page has 16M 64/32K 4K 256 bytes 64K 256/128 16 - pages 4096 16/8 - - sectors 256/512 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25Q128C 64K Bytes Block Sector Architecture Block 255 254 …… …… 2 1 0 Sector Address range 4095 FFF000H FFFFFFH …… …… …… 4080 FF0000H FF0FFFH 4079 FEF000H FEFFFFH …… …… …… 4064 FE0000H FE0FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 7 73 - 7 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 4. DEVICE OPERATION SPI Mode Standard SPI The GD25Q128C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q128C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q128C supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. QPI The GD25Q128C supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between these two modes. Upon power-up and after software reset using “”Reset (99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin. The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. 8 73 - 8 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Figure1. Hold Condition CS# SCLK HOLD# HOLD HOLD RESET The RESET# pin allows the device to be reset by the control. For the WSON8 package, the pin7 can be configured as a RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. On the SOP16 package, a dedicated RESET# pin is provided and it is independent of QE bit setting. The RESET# pin goes low for a period of tRLRH or longer will reset the flash. After reset cycle, the flash is at the following states: -Standby mode -All the volatile bits will return to the default status as power on. Figure2. RESET Condition CS# RESET# RESET 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C 5. DATA PROTECTION The GD25Q128C provide the following data protection methods: � Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) � Software Protection Mode: -The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. -Individual Block Protection bit provides the protection selection of each individual block and sectors in the top and Rev.1.0 9 - 9 73 bottom block. � Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. � Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. � Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) � Software Protection Mode: -The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. -Individual Block Protection bit provides the protection selection of each individual block and sectors in the top and bottom block. � Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. � Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Table 5.1. GD25Q128C Protected area size (WPS=0, CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 to 255 FC0000H-FFFFFFH 256KB Upper 1/64 0 0 0 1 0 248 to 255 F80000H-FFFFFFH 512KB Upper 1/32 0 0 0 1 1 240 to 255 F00000H-FFFFFFH 1MB Upper 1/16 0 0 1 0 0 224 to 255 E00000H-FFFFFFH 2MB Upper 1/8 0 0 1 0 1 192 to 255 C00000H-FFFFFFH 4MB Upper 1/4 0 0 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2 0 1 0 0 1 0 to 3 000000H-03FFFFH 256KB Lower 1/64 0 1 0 1 0 0 to 7 000000H-07FFFFH 512KB Lower 1/32 0 1 0 1 1 0 to 15 000000H-0FFFFFH 1MB Lower 1/16 0 1 1 0 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/8 0 1 1 0 1 0 to 63 000000H-3FFFFFH 4MB Lower 1/4 0 1 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 X X 1 1 1 0 to 255 000000H-FFFFFFH 16MB ALL 1 0 0 0 1 255 FFF000H-FFFFFFH 4KB Top Block 1 0 0 1 0 255 FFE000H-FFFFFFH 8KB Top Block 1 0 0 1 1 255 FFC000H-FFFFFFH 16KB Top Block 1 0 1 0 X 255 FF8000H-FFFFFFH 32KB Top Block 1 0 1 1 0 255 FF8000H-FFFFFFH 32KB Top Block 1 1 4KB Bottom Block 1 1 1 1 0 0 1 0 000000H-000FFFH 3.3V Uniform Sector 0 1 0 0 000000H-001FFFH Dual and Quad Serial Flash 1 1 8KB Bottom Block GD25Q128C 0 1 1 0 000000H-003FFFH 16KB Bottom Block 1 1 0 X 0 10000000H-007FFFH 32KB Bottom Block 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block Table 5.2. GD25Q128C Protected area size (WPS=0, CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 0 to 255 000000H-FFFFFFH ALL ALL 0 0 0 0 1 0 to 251 000000H-FBFFFFH 16128KB Lower 63/64 0 0 0 1 0 0 to 247 000000H-F7FFFFH 15872KB Lower 31/32 0 0 0 1 1 0 to 239 000000H-EFFFFFH 15MB Lower 15/16 0 0 1 0 0 0 to 223 73000000H-DFFFFFH - 10 14MB Lower 7/8 Rev.1.0 0 0 1 0 1 0 to 191 000000H-BFFFFFH 12MB Lower 3/4 0 0 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 0 1 0 0 1 4 to 255 040000H-FFFFFFH 16128KB Upper 63/64 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C 1 1 1 0 X 3.3V0 Uniform000000H-007FFFH 32KB serial Bottom Block sector dual and quad flash GD25Q128CxIGx 1 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block Table 5.2. GD25Q128C Protected area size (WPS=0, CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 0 to 255 000000H-FFFFFFH ALL ALL 0 0 0 0 1 0 to 251 000000H-FBFFFFH 16128KB Lower 63/64 0 0 0 1 0 0 to 247 000000H-F7FFFFH 15872KB Lower 31/32 0 0 0 1 1 0 to 239 000000H-EFFFFFH 15MB Lower 15/16 0 0 1 0 0 0 to 223 000000H-DFFFFFH 14MB Lower 7/8 0 0 1 0 1 0 to 191 000000H-BFFFFFH 12MB Lower 3/4 0 0 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 0 1 0 0 1 4 to 255 040000H-FFFFFFH 16128KB Upper 63/64 0 1 0 1 0 8 to 255 080000H-FFFFFFH 15872KB Upper 31/32 0 1 0 1 1 16 to 255 100000H-FFFFFFH 15MB Upper 15/16 0 1 1 0 0 32 to 255 200000H-FFFFFFH 14MB Upper 7/8 0 1 1 0 1 64 to 255 400000H-FFFFFFH 12MB Upper 3/4 0 1 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 to 255 000000H-FFEFFFH 16380KB L-4095/4096 1 0 0 1 0 0 to 255 000000H-FFDFFFH 16376KB L-2047/2048 1 0 0 1 1 0 to 255 000000H-FFBFFFH 16368KB L-1023/1024 1 0 1 0 X 0 to 255 000000H-FF7FFFH 16352KB L-511/512 1 0 1 1 0 0 to 255 000000H-FF7FFFH 16352KB L-511/512 1 1 0 0 1 0 to 255 001000H-FFFFFFH 16380KB U-4095/4096 1 1 0 1 0 0 to 255 002000H-FFFFFFH 16376KB U-2047/2048 1 1 0 1 1 0 to 255 004000H-FFFFFFH 16368KB U-1023/1024 1 1 1 0 X 0 to 255 008000H-FFFFFFH 16352KB U-511/512 1 1 1 1 0 0 to 255 008000H-FFFFFFH 16352KB U-511/512 11 73 - 11 Rev.1.0 GD25Q128CxIGx 3.3V Uniform sector dual and quad serial flash 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Table 5.3. GD25Q128C Individual Block Protection (WPS=1) Block 255 Sector Address range Individual Block Lock Operation 4095 FFF000H FFFFFFH …… …… …… 4080 FF0000H FF0FFFH FE0000H FEFFFFH 32 Sectors(Top/Bottom)/254 Blocks 254 …… …… …… …… Block Lock: 36H+Address …… …… …… …… Block Unlock: 39H+Address …… …… …… …… Read Block Lock: 3DH+Address 2 020000H 02FFFFH Global Block Lock: 7EH 1 010000H 01FFFFH Global Block Unlock: 98H 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 0 7312- 12 Rev.1.0 3.3V Uniform Sector Uniform serial flash GD25Q128CxIGx Dual and Quad3.3V Serial Flash sector dual and quadGD25Q128C 6. STATUS REGISTER S23 S22 S21 S20 S19 S18 S17 S16 HOLD/RST DRV1 DRV0 Reserved Reserved WPS Reserved Reserved S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. SRP1 SRP0 #WP Status Register 0 0 X Software Protected 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X Power Supply Lock-Down(1) 1 1 X One Time Program(2) Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) WP#=0, the Status Register locked and can not be written to. WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and can not be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available on special order. Please contact GigaDevice for details. 13 73 - 13 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# / RESET# pins are tied directly to the power supply or ground) LB3, LB2, LB1, bits. The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS1, SUS2 bit The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command as well as a power-down, power-up cycle. WPS The WPS Bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, BP (4:0) bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset. DRV1/DRV0 The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations. DRV1,DRV0 Driver Strength 00 100% 01 75% 10 50% (default) 11 25% HOLD/RST The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#. However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are disabled, the pin acts as dedicated data I/O pin. 14 73 - 14 Rev.1.0 3.3V Uniform Sector Dual and Quad Serial Flashsector dual and quad serial GD25Q128C 3.3V Uniform flash GD25Q128CxIGx 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 7.1., every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table 7.1. Commands (Standard/Dual/Quad SPI) Command Name Byte 1 Write Enable Write Disable Volatile SR Write Enable Read Status Register-1 Read Status Register-2 Read Status Register-3 Write Status Register-1 Write Status Register-2 Write Status Register-3 Read Data Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Fast Read Quad I/O Word (7) Fast Read Page Program Quad Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase 06H 04H 50H Enable QPI Enable Reset Reset Set Burst with Wrap Byte 2 Byte 3 05H 35H 15H 01H 31H 11H 03H 0BH 3BH (S7-S0) (S15-S8) (S23-S16) (S7-S0) (S15-S8) (S23-S16) A23-A16 A23-A16 A23-A16 BBH A23-A8 6BH A23-A16 EBH A23-A0 (4) M7-M0 A23-A0 (4) M7-M0 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 E7H 02H 32H 20H 52H D8H C7/60 H 38H 66H 99H 77H (2) Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 (2) M7-M0 A15-A8 (D7-D0) (5) (D7-D0) (3) (continuous) dummy (6) (D7-D0) (3) (continuous) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 dummy (D7-D0) dummy dummy (Next byte) (D7-D0) (1) (D7-D0) (1) A7-A0 (continuous) (continuous) (continuous) (continuous) dummy (D7-D0) (3) (D7-D0) (3) (D7-D0) (continuous) Next byte (10) dummy W7-W0 15 73 - 15 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash Program/Erase Suspend Program/Erase Resume Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Deep Power-Down Manufacturer/ Device ID Manufacturer/ Device ID by Dual I/O 75H 7AH ABH B9H 90H 92H dummy dummy (DID7-DID 0) dummy dummy 00H (MID7-MI D0) A23-A8 A7-A0, M7-M0 (MID7-MID 0) (DID7-DID 0) (11) 5AH (MID7-MID 0) A23-A16 dummy (MID7-MI D0) (DID7-DID 0) (JDID15-J DID8) A15-A8 (JDID7-JD ID0) A7-A0 44H A23-A16 A15-A8 A7-A0 42H A23-A16 A15-A8 48H A23-A16 36H 39H 3DH 7EH 98H A23-A16 A23-A16 A23-A16 94H Read Serial Flash Discoverable Parameter Erase Security (8) Registers Program Security (8) Registers Read Security (8) Registers Individual Block Lock Individual Block Unlock Read Block Lock Global Block Lock Global Block Unlock dummy (continuous) ABH Manufacturer/ Device ID by Quad I/O Read Identification GD25Q128C 9FH A23-A0, M7-M0 (DID7-DID 0) (continuous) (continuous) (continuous) (continuous) dummy (D7-D0) A7-A0 (D7-D0) (D7-D0) A15-A8 A7-A0 dummy (D7-D0) A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 (continuous) Table 7.2. Commands (QPI) Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Clock Number Write Enable Volatile SR Write Enable Write Disable Read Status Register-1 Read Status Register-2 Read Status Register-3 Write Status Register-1 Write Status Register-2 Write Status Register-3 Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Program/Erase Suspend Program/Erase Resume (0,1) 06H 50H 04H 05H 35H 15H 01H 31H 11H 02H 20H 52H D8H C7/60H 75H 7AH (2,3) (4,5) (6,7) (8,9) (10,11) (S7-S0) (S15-S8) (S23-S16) (S7-S0) (S15-S8) (S23-S16) A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) Next byte 16 73 - 16 Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash Deep Power-Down Set Read Parameters Fast Read Burst Read with Wrap Quad I/O Fast Read Release From Deep Power-Down, And Read Device ID Manufacturer/ Device ID Read Identification Read Serial Flash Discoverable Parameter Disable QPI Enable Reset Reset Individual Block Lock Individual Block Unlock Read Block Lock Global Block Lock Global Block Unlock GD25Q128C B9H C0H 0BH 0CH EBH ABH P7-P0 A23-A16 A23-A16 A23-A16 dummy A15-A8 A15-A8 A15-A8 dummy A7-A0 A7-A0 A7-A0 dummy dummy dummy M7-M0 (DID7-DID0 ) (D7-D0) (D7-D0) (D7-D0) 90H dummy dummy 00H (MID7-MID0 ) (DID7-DID0) (MID7-MID0 ) A23-A16 (JDID15-JDI D8) A15-A8 (JDID7-JDID 0) A7-A0 dummy (D7-D0) A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 9FH 5AH FFH 66H 99H 36H 39H 3DH 7EH 98H NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) 17 73 - 17 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C IO3 = (x, x, D7, D3,…) 7. Fast Word Read Quad I/O Data: the lowest address bit must be 0. 8. Security Registers Address: Security Register1: A23-A16=00H, A15-A8=10H, A7-A0= Byte Address; Security Register2: A23-A16=00H, A15-A8=20H, A7-A0= Byte Address; Security Register3: A23-A16=00H, A15-A8=30H, A7-A0= Byte Address. 9. QPI Command, Address, Data input/output format: CLK #0 1 2 3 4 5 6 7 8 9 10 11 IO0= C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0, IO1= C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1 IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2 IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3 10. Dummy bits and Wrap Bits IO0 = (x, x, x, x, x, x, W4,x) IO1 = (x, x, x, x, x, x, W5, x) IO2 = (x, x, x, x, x, x, W6, x) IO3 = (x, x, x, x, x, x, W7, x) 11. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …) Table 7.3. Table of ID Definitions for GD25Q128C Operation Code MID7-MID0 ID15-ID8 ID7-ID0 9FH C8 40 18 90H/92H/94H C8 17 ABH 17 18 73 - 18 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low � sending the Write Enable command � CS# goes high. Figure3. Write Enable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 06H High-Z SO Figure3a. Write Enable Sequence Diagram (QPI) CS# 0 SCLK 1 Command 06H IO0 IO1 IO2 IO3 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low �Sending the Write Disable command �CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. 19 73 - 19 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C Figure4. Write Disable Sequence Diagram CS# SCLK 1 0 2 3 4 5 6 7 Command SI 04H High-Z SO Figure4a. Write Disable Sequence Diagram (QPI) CS# 0 SCLK 1 Command 04H IO0 IO1 IO2 IO3 7.3. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. Figure5. Write Enable for Volatile Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command(50H) SI SO High-Z 20 73 - 20 Rev.1.0 3.3V Uniform Sector 3.3V Uniform flash GD25Q128CxIGx Dual and Quad Serial Flashsector dual and quad serial GD25Q128C Figure5a. Write Enable for Volatile Status Register Sequence Diagram (QPI) CS# 0 SCLK 1 Command 50H IO0 IO1 IO2 IO3 7.4. Read Status Register (RDSR) (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H” / “35H” / “15H”, the SO will output Status Register bits S7~S0 / S15-S8 / S16-S23. Figure6. Read Status Register Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 Register0/1/2 6 5 4 3 2 1 Command 05H or 35H or 15H High-Z Register0/1/2 7 0 MSB 6 5 4 3 2 1 0 7 MSB Figure6a. Read Status Register Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 Command 05H/35H/15H IO0 4 0 4 0 4 IO1 5 1 5 1 5 IO2 6 2 6 2 6 IO3 7 3 7 3 7 Register0/1/2 21 73 - 21 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash 7.5. Write Status Register (WRSR) (01H or 31H or 11H) GD25Q128C The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure7. Write Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 Command SI 01H/31H/11H Status Register in 5 MSB SO 4 3 2 1 0 High-Z Figure7a. Write Status Register Sequence Diagram (QPI) CS# SCLK 0 1 2 3 Command 01H/31H/11H IO0 4 0 IO1 5 1 IO2 6 2 IO3 7 3 Status Register in 22 73 - 22 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C 7.6. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure8. Read Data Bytes Sequence Diagram CS# SCLK 1 0 2 3 4 5 6 7 8 9 10 Command SI 24-bit address 03H 3 23 22 21 2 1 0 MSB High-Z SO 28 29 30 31 32 33 34 35 36 37 38 39 MSB 7 Data Out1 5 4 3 2 1 6 Data Out2 0 7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure9. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 28 29 30 31 24-bit address Command SI 9 10 0BH 3 23 22 21 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI Dummy Byte 7 6 SO 5 4 3 2 1 0 7 6 MSB Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Fast Read (0BH) in QPI mode The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either 23 73 - 23 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8/8. Figure9a. Read Data Bytes at Higher Speed Sequence Diagram (QPI) CS# 0 SCLK 1 2 3 4 6 5 7 Command 0BH IO0 A23-16 A15-8 20 16 12 8 A7-0 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 11 8 9 10 11 12 13 IOs switch from Input to output Dummy* 4 0 4 0 4 0 4 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte1 Byte2 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.8. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure10. Dual Output Fast Read Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 8 7 9 10 28 29 30 31 24-bit address Command 23 22 21 3BH 1 2 3 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI Dummy Clocks SO 0 6 Data Out2 Data Out1 7 5 3 1 7 5 3 1 MSB MSB 7 6 4 2 0 6 4 2 7.9. Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 24 73 - 24 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C and IO0. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure11. Quad Output Fast Read Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 7 9 10 24-bit address Command SI(IO0) 23 22 21 6BH SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z CS# SCLK 28 29 30 31 1 2 3 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy Clocks 7.10. SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. 25 73 - 25 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Figure12. Dual I/O Fast Read Sequence Diagram (M5-4� (1, 0)) CS# 1 0 SCLK 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 7 Command SI(IO0) BBH SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 5 3 1 A7-0 6 4 7 5 M7-4 Dummy CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure12a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0)) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 5 3 1 7 5 3 1 7 5 3 1 7 5 7 A23-16 A15-8 A7-0 M7-4 Dummy CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 7326- 26 Byte4 Rev.1.0 3.3V Uniform Sector 3.3V Uniform flash GD25Q128CxIGx Dual and Quad Serial Flashsector dual and quad serial GD25Q128C 7.11. Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure13. Quad I/O Fast Read Sequence Diagram (M5-4� (1, 0)) CS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 0 SCLK Command SI(IO0) EBH HOLD#(IO3) 3.3V Uniform Sector 7 3 7 3 A15-8 Dual and Quad SerialA23-16 Flash A7-0 M7-0 Dummy Byte1 Byte2 GD25Q128C Figure13a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0)) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with 27 Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap 73 - 27 Rev.1.0 Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 3 7 3 7 7 3 7 3 7 3 7 3 3.3V Uniform sector dual7 and quad serial flash GD25Q128CxIGx A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. Quad I/O Fast Read (EBH) in QPI mode The Quad I/O Fast Read command is also supported in QPI mode. See Figure13b. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8/8. In QPI mode, the “Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O 3.3V Uniform Sector Dual and Quad Serial Flash Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst GD25Q128C Read with Wrap” (0CH) command must be used. Figure13b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 IOs switch from Input to output Command EBH IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 A23-16 A15-8 7.12. 14 7 3 28 4 4 0 4 0 4 5 5 1 5 1 5 6 6 2 6 2 6 7 7 3 Dummy A7-0 M7-4* Byte1 7 3 7 Byte2 Byte3 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Rev.1.0 73 - 28If the “Continuous Read Mode” bits (M5-4) = (1, 0), then Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure14. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” 7.12. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each GD25Q128CxIGx 3.3V Uniform sector and serial flash byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9)dual must be set toquad enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O 3.3V Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command Uniform Sector code. The command sequence is shown in followed Figure14. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, Dual and Quad Serial Flash GD25Q128C 3.3V Uniform Sector Dual and Quad Quad Serial Flash Reset command can be Figure14. used to reset (M5-4) beforeFast issuing normal command. I/O Word Read Sequence Diagram (M5-4� (1, 0)) 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” GD25Q128C Figure14. Quad I/O Word Fast Read Sequence Diagram (M5-4� (1, 0)) CS# CS# SCLK SCLK 0 1 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 Command 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SI(IO0) 3 4 4 0 0 4 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 4 0 4 0 4 0 5 1 5 1 5 1 4 5 SO(IO1) WP#(IO2) 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 5 1 5 1 5 1 6 2 6 2 6 2 5 6 WP#(IO2) HOLD#(IO3) 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 6 2 6 2 6 2 7 3 7 3 7 3 6 7 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 E7H Command SI(IO0) SO(IO1) E7H HOLD#(IO3) 0 4 0 4 4 0 4 0 4 0 4 Byte1 A23-16 A7-0 Diagram M7-0 Dummy Figure14a. Quad I/O Word Fast ReadA15-8 Sequence (M5-4= (1, 0))Byte2 Byte3 CS# Figure14a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0)) CS# SCLK 0 1 2 3 4 5 29 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 8 9 10 11 12 13 14 15 SCLK SI(IO0) 4 SI(IO0) SO(IO1) 6 7 4 0 0 4 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 4 0 4 0 4 0 5 1 5 1 5 1 4 5 SO(IO1) WP#(IO2) 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 5 1 5 1 5 1 6 2 6 2 6 2 5 6 WP#(IO2) HOLD#(IO3) 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 6 2 6 2 6 2 7 3 7 3 7 3 6 7 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 HOLD#(IO3) 0 4 0 4 0 4 0 4 0 4 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the boundary automatically until CS# is pulled high to terminate the command. command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the boundary automatically until CS# is pulled high to terminate the command. cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” cache afterwards within a fixed length (8/16/32/64-byte) 73 of data Burst - 29without issuing multiple read commands. The “SetRev.1.0 operation while W6-W5 is used to specify the length of the wrap around section within a page. with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be GD25Q128CxIGx 3.3V Uniform sector dual and quad serial flash limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” 3.3V Uniform operation while W6-W5 is used to specify Sector the length of the wrap around section within a page. 7.13. Dual and Quad Serial Flash GD25Q128C Set Burst with Wrap (77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode. 30 low � Send Set Burst with Wrap command � Send 24 The Set Burst with Wrap command sequence: CS# goes dummy bits � Send 8 bits “Wrap bits” � CS# goes high. W6,W5 W4=0 W4=1 (default) Wrap Around Wrap Length Wrap Around Wrap Length 0, 0 Yes 8-byte No N/A 0, 1 Yes 16-byte No N/A 1, 0 Yes 32-byte No N/A 1, 1 Yes 64-byte No N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with “Wrap Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0H) command. Figure15. Set Burst with Wrap Sequence Diagram CS# 8 9 10 11 12 13 14 15 x x x x x x 4 x SO(IO1) x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x SCLK 0 1 2 3 4 5 6 7 Command SI(IO0) 77H W6-W4 7.14. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Rev.1.0 Page Program command sequence: CS# goes low � sending least 73 - Page 30 Program command � 3-byte address on SI � at 1 byte data on SI � CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x quad serial flash GD25Q128CxIGx 3.3V Uniform sector dual andW6-W4 7.14. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI � at least 1 byte data on SI � CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the Sector device, previously 3.3V latched Uniform data are discarded and the last 256 data bytes are guaranteed to be programmed correctly Dual and GD25Q128C within the same page. If less thanQuad 256 dataSerial bytes areFlash sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of 31 the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. Figure16. Page Program Sequence Diagram CS# 5 6 8 7 24-bit address 23 22 21 02H Data Byte 1 2 3 6 5 4 3 2 1 2078 Command SI 28 29 30 31 32 33 34 35 36 37 38 39 9 10 2079 4 2076 3 2077 2 2075 1 2074 0 SCLK 1 0 0 7 1 MSB 0 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 7 6 SCLK SI Data Byte 3 Data Byte 2 7 6 5 4 1 2 3 0 7 6 5 Data Byte 256 0 1 2 3 4 MSB MSB 5 3 4 2 MSB Figure16a. Page Program Sequence Diagram (QPI) 2 3 4 5 6 7 8 9 10 11 12 13 519 1 518 0 517 SCLK 516 CS# Command A23-16 A15-8 20 16 12 8 A7-0 4 0 Byte1 Byte2 Byte3 IO0 4 0 4 0 4 0 4 0 4 0 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 IO3 23 19 15 11 7 3 7 3 7 3 7 3 02H Byte255 Byte256 73 - 31 7 3 7 3 Rev.1.0 2079 2078 2076 2077 2075 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 3 Data Byte 2 Data Byte 256 7 6 and 0 3 2 1serial 5 4 quad 2 1 0 dual 6 5 4 3 sector 7 6 5 4 3 2 1 3.3V 0 7 Uniform flash GD25Q128CxIGx SI MSB MSB MSB Figure16a. Page Program Sequence Diagram (QPI) 3 4 5 6 7 8 9 10 11 12 13 519 2 518 1 517 0 SCLK 516 CS# Command A23-16 A15-8 20 16 12 8 A7-0 4 0 Byte1 Byte2 Byte3 IO0 4 0 4 0 4 0 4 0 4 0 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 02H 7.15. Byte255 Byte256 Quad Page Program (32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The 3.3V Uniform quad Page Program command is enteredSector by driving CS# Low, followed by the command code (32H), three address bytes Dual and Quad and at least one data byte on IO pins. Serial Flash GD25Q128C The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data 32be programmed correctly within the same page. If less than are discarded and the last 256 data bytes are guaranteed to 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. Figure17.Quad Page Program Sequence Diagram CS# 6 7 8 Command SI(IO0) SO(IO1) 32H 9 10 28 29 30 31 32 33 34 35 36 37 38 39 24-bit address 23 22 21 3 2 Byte1 Byte2 1 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 543 5 542 4 541 3 540 2 539 1 538 0 537 SCLK MSB WP#(IO2) HOLD#(IO3) 73 - 32 SCLK 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 536 CS# Rev.1.0 otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. Figure17.Quad Page Program Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 Command SI(IO0) 28 29 30 31 32 33 34 35 36 37 38 39 24-bit address 3 Byte1 Byte2 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 539 540 541 542 543 1 538 2 537 32H 0 4 0 23 22 21 MSB SO(IO1) 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Byte11Byte12 536 CS# Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7.16. 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 0 Sector Erase (SE) (20H) The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid 3.3V Uniform Sector address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. Dual and sequence: Quad Serial GD25Q128C The Sector Erase command CS# goes Flash low � sending Sector Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last 33 address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit is not executed. Figure18. Sector Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 Command 20H 6 7 8 73 - 33 9 29 30 31 Rev.1.0 24 Bits Address 23 22 MSB 2 1 0 Figure18a. Sector Erase Sequence Diagram (QPI) address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is GD25Q128CxIGx Uniform sector dual and quad serial flash completed, the Write Enable Latch (WEL)3.3V bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit is not executed. Figure18. Sector Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB 20H 2 1 0 Figure18a. Sector Erase Sequence Diagram (QPI) CS# 0 SCLK 1 2 3 4 6 5 7 Command 20H 7.17. A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low � sending 32KB Block Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,3.3V the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which Uniform Sector is protected by the Block BP3, BP2, BP1,Flash and BP0) bits is not executed. DualProtect and(BP4, Quad Serial GD25Q128C Figure19. 32KB Block Erase Sequence Diagram 34 CS# 0 SCLK 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB 52H 1 2 0 Figure19a. 32KB Block Erase Sequence Diagram (QPI) CS# SCLK Rev.1.0 73 - 34 0 1 2 3 4 5 6 7 CS# 0 SCLK 1 2 3 4 5 6 8 7 9 29 30 31 24 Bits Address Command SI 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 23 22 2 1 0 52H MSB Figure19a. 32KB Block Erase Sequence Diagram (QPI) CS# 0 SCLK 1 2 3 4 5 6 7 Command 52H 7.18. A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low � sending 64KB Block Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed. Figure20. 64KB Block Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 8 29 30 31 24 Bits Address Command D8H 9 23 22 MSB 2 1 0 35 73 - 35 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Figure20a. 64KB Block Erase Sequence Diagram (QPI) CS# 0 SCLK 1 2 3 4 6 5 7 Command A23-16 A15-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 D8H 7.19. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low � sending Chip Erase command � CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure21. Chip Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 60H or C7H 36 73 - 36 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure21a. Chip Erase Sequence Diagram (QPI) CS# 0 SCLK 1 Command C7H/60H IO0 IO1 IO2 IO3 7.20. Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low � sending Deep Power-Down command � CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure22. Deep Power-Down Sequence Diagram CS# SCLK SI tDP 0 1 2 3 4 5 6 7 Command Stand-by mode Deep Power-down mode B9H 37 73 - 37 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C Figure22a. Deep Power-Down Sequence Diagram (QPI) CS# 0 SCLK tDP 1 Command B9H IO0 IO1 IO2 IO3 Stand-by mode 7.21. Deep Power-down mode Release from Deep Power-Down and Read Device ID (RDI) (ABH) The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. The Device ID value for the GD25Q128C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure24, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure23. Release Power-Down Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 t RES1 Command ABH Deep Power-down mode 38 73 - 38 Stand-by mode Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C Figure23a. Release Power-Down Sequence Diagram (QPI) CS# 0 SCLK tRES1 1 Command ABH IO0 IO1 IO2 IO3 Stand-by mode Deep Power-down mode Figure24. Release Power-Down/Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 29 30 31 32 33 34 35 36 37 38 9 SCLK SI 2 23 22 ABH 1 0 MSB High-Z SO t RES2 3 Dummy Bytes Command MSB 7 Device ID 5 4 3 2 6 1 0 Deep Power-down Mode Stand-by Mode Figure24a. Release Power-Down/Read Device ID Sequence Diagram (QPI) CS# SCLK 0 1 Command ABH 2 3 4 5 6 7 tRES2 8 IOs switch from Input to Output 3 Dummy Bytes IO0 4 0 IO1 5 1 IO2 6 2 IO3 7 3 Device ID Deep Power-down mode 39 73 - 39 Stand-by mode Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector 7.22. Dual and Quad Serial Flash GD25Q128C Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure25. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 10 Command SI 24-bit address 90H 23 22 21 3 2 1 0 High-Z SO CS# 28 29 30 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 32 SCLK SI SO 7 Manufacturer ID 6 5 4 3 2 1 MSB Device ID 0 7 6 5 4 3 2 1 0 MSB Figure25a. Read Manufacture ID/ Device ID Sequence Diagram (QPI) CS# SCLK 0 1 Command 2 3 4 5 6 7 IO0 A7-0 A23-16 A15-8 (00H) 20 16 12 8 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 90H 11 8 9 10 IOs switch from Input to Output 4 0 4 0 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 MID 40 73 - 40 Device ID Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector 7.23. Dual and Quad Serial Flash GD25Q128C Read Manufacture ID/ Device ID Dual I/O (92H) The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure26. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Command SI(IO0) 92H SO(IO1) A23-16 A15-8 A7-0 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 MFR ID 7.24. Device ID MFR ID (Repeat) Device ID (Repeat) MFR ID (Repeat) Device ID (Repeat) Read Manufacture ID/ Device ID Quad I/O (94H) The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. If the 24-bit address is initially set to 000001H, the Device ID will be read first. 41 73 - 41 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Figure27. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 SCLK Command SI(IO0) 94H A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID CS# SCLK 24 25 26 27 28 29 30 31 SI(IO0) 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 MFR ID DID MFR ID DID (Repeat)(Repeat)(Repeat)(Repeat) 7.25. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure28. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. 7342- 42 Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure28. Read Identification ID Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 9 10 11 12 13 14 15 7 Manufacturer ID 6 5 4 3 2 1 7 9FH SI Command SO MSB CS# 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI 7 SO MSB 6 5 4 3 2 1 Memory Type JDID15-JDID8 7 0 6 MSB 5 4 3 2 Capacity JDID7-JDID0 1 0 Figure28a. Read Identification ID Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 6 5 IOs switch from Input to Output Command 9FH IO0 4 0 12 8 4 0 IO1 5 1 13 9 5 1 IO2 6 2 14 10 6 2 IO3 7 3 15 11 7 3 MID JDID15 JDID7-JDID8 JDID0 7.26. Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H / 32H) are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. 43 73 - 43 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure29. Figure29. Program/Erase Suspend Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 tSUS 7 Command SI 75H High-Z SO Accept read command Figure29a. Program/Erase Suspend Sequence Diagram (QPI) CS# 0 SCLK tSUS 1 Command 75H IO0 IO1 IO2 IO3 Accept Read 7.27. Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure30. Figure30. Program/Erase Resume Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 7AH SO Resume Erase/Program 44 73 - 44 Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure30a. Program/Erase Resume Sequence Diagram (QPI) CS# 0 SCLK 1 Command 7AH IO0 IO1 IO2 IO3 Resume previously suspended program or Erase 7.28. Erase Security Registers (44H) The GD25Q128C provides three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low � sending Erase Security Registers command � CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-8 0000 0000 0000 A7-0 Do not care Do not care Do not care Figure31. Erase Security Registers command Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 44H 9 29 30 31 24 Bits Address 23 22 MSB 45 73 - 45 2 1 0 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash 7.29. GD25Q128C Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-8 0000 0000 0000 A7-0 Byte Address Byte Address Byte Address Figure32. Program Security Registers command Sequence Diagram CS# 5 6 8 7 24-bit address 23 22 21 3 2 6 5 4 3 2 1 2079 42H Data Byte 1 2078 Command SI 28 29 30 31 32 33 34 35 36 37 38 39 9 10 2077 4 2076 3 2075 2 2074 1 1 0 0 7 1 MSB 0 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB 2073 0 SCLK SCLK SI 7 6 5 MSB 7.30. Data Byte 3 Data Byte 2 4 3 2 1 0 7 6 5 4 3 2 MSB Data Byte 256 1 0 7 6 5 4 3 2 MSB Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command i is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches the last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving CS# high. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 46 73 - 46 A11-8 0000 0000 0000 A7-0 Byte Address Byte Address Byte Address Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure33. Read Security Registers command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 28 29 30 31 24-bit address Command SI 9 10 48H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 7.31. Data Out1 5 4 3 2 7 6 MSB SO 1 0 Data Out2 7 6 5 MSB Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH) The individual block/sector lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, BP (4:0) bits in the Status Register. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. The individual Block/Sector Lock command (36H) sequence: CS# goes low �SI: Sending individual Block/Sector Lock command� SI: Sending 24bits individual Block/Sector Lock Address � CS# goes high. The command sequence is shown in Figure34. The individual Block/Sector Unlock command (39H) sequence: CS# goes low �SI: Sending individual Block/Sector Unlock command� SI: Sending 24bits individual Block/Sector Lock Address � CS# goes high. The command sequence is shown in Figure35. The Read individual Block/Sector lock command (3DH) sequence: CS# goes low � SI: Sending Read individual Block/Sector Lock command� SI: Sending 24bits individual Block/Sector Lock Address � SO: The Block/Sector Lock Bit will out �CS# goes high. If the least significant bit(LSB) is1, the corresponding block/sector is locked, if the LSB is 0, the corresponding block/sector is unlocked, Erase/Program operation can be performed. The command sequence is shown in Figure36. Figure34. Individual Block/Sector Lock command Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 8 Command 36H 9 29 30 31 24 Bits Address 23 22 MSB 47 73 - 47 2 1 0 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C Figure34a. Individual Block/Sector Lock command Sequence Diagram (QPI) CS# 0 SCLK 1 2 3 4 6 5 7 Command 36H A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 Figure35. Individual Block/Sector Unlock command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 Command SI 29 30 31 24 Bits Address 23 22 MSB 39H 2 1 0 Figure35a. Individual Block/Sector Unlock command Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 6 5 7 Command 39H A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 48 73 - 48 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector Dual and Quad Serial Flash GD25Q128C Figure36. Read Individual Block/Sector lock command Sequence Diagram CS# 0 1 2 3 4 5 6 8 7 29 30 31 32 33 34 35 36 37 38 9 SCLK 24Bits Address Command SI 23 22 3DH 0 1 MSB High-Z SO 2 Lock Value Out X X X X X X X 0 MSB Figure36a. Read Individual Block/Sector lock command Sequence Diagram (QPI) CS# SCLK 0 1 Command 2 3 4 5 6 7 8 9 24Bits Address Lock Value Out 3DH 7.32. IO0 X 0 IO1 X X IO2 X X IO3 X X Global Block/Sector Lock (7EH) or Unlock (98H) All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock command, or can set to 0 by the Global Block/Sector Unlock command. The Global Block/Sector Lock command (7EH) sequence: CS# goes low �SI: Sending Global Block/Sector Lock command� CS# goes high. The command sequence is shown in Figure37. The Global 3.3V Block/Sector Unlock command Uniform Sector(98H) sequence: CS# goes low �SI: Sending Global Block/Sector Unlock command� CS# goes high. The command sequence is shown in Figure38. Dual and Quad Serial Flash GD25Q128C Figure37. The Global Block/Sector Lock Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 Command 7EH High-Z Figure37a. The Global Block/Sector Lock Sequence Diagram (QPI) 49 CS# SCLK 73 - 49 0 1 Rev.1.0 SCLK 0 1 2 3 4 5 6 7 Command SI 7EH High-Z SO 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Figure37a. The Global Block/Sector Lock Sequence Diagram (QPI) CS# 0 SCLK 1 Command 7EH IO0 IO1 IO2 IO3 Figure38. The Global Block/Sector Unlock Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 98H High-Z SO 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Figure38a. The Global Block/Sector Unlock Sequence Diagram (QPI) CS# 0 SCLK 1 Command 98H IO0 IO1 50 IO2 IO3 7.33. Set Read Parameters (C0H) In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. In standard SPI mode, the “Wrap Length” is set by W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged when the Rev.1.0 73 - 50 device is switched from Standard SPI mode to QPI mode. P5-P4 Dummy Clocks Maximum Read Freq. P1-P0 Wrap Length IO1 IO2 IO 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3 7.33. Set Read Parameters (C0H) In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. In standard SPI mode, the “Wrap Length” is set by W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode. P5-P4 Dummy Clocks 00 4 Maximum Read Freq. 60MHz 01 6 10 8 11 8 P1-P0 Wrap Length 00 8-byte 80MHz 01 16-byte 80MHz 10 32-byte 80MHz 11 64-byte Figure39. Set Read Parameters command Sequence Diagram CS# SCLK 0 1 Command C0H 2 3 Read Parameters IO0 P4 P0 IO1 P5 P1 IO2 P6 P2 IO3 P7 P3 51 73 - 51 Rev.1.0 Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform 3.3V Sector 7.34. Dual and Quad Serial Flash GD25Q128C Burst Read with Wrap (0CH) The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)” command. Figure40. Burst Read with Wrap command Sequence Diagram CS# 0 SCLK 1 2 3 4 6 5 7 8 9 10 11 12 13 14 IOs switch from Input to output Command 0CH IO0 20 16 12 8 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 23 19 15 11 7 3 7 3 7 3 7 IO3 A23-16 A15-8 A7-0 Dummy* Byte1 Byte2 Byte3 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.35. Enable QPI (38H) The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the device from SPI mode to QPI mode. See the command Table 7.2. for all support QPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure41. Enable QPI mode command Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 38H 52 73 - 52 Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash 7.36. GD25Q128C Disable QPI (FFH) To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure42. Disable QPI mode command Sequence Diagram CS# 0 SCLK 1 Command FFH IO0 IO1 IO2 IO3 7.37. Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset (99H)” command sequence as follow: CS# goes low � Sending Enable Reset command � CS# goes high � CS# goes low � Sending Reset command � CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST =60us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure43. Enable Reset and Reset command Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 0 7 1 2 3 4 5 Command Command 66H 99H 6 7 High-Z 53 73 - 53 Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure44. Enable Reset and Reset command Sequence Diagram (QPI) CS# 0 SCLK 0 1 Command 66H 1 Command 99H IO0 IO1 IO2 IO3 7.38. Read Serial Flash Discoverable Parameter (5AH) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216. Figure45. Read Serial Flash Discoverable Parameter command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 28 29 30 31 24-bit address Command SI 9 10 23 22 21 5AH 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dummy Byte 7 6 5 4 3 2 1 0 7 6 MSB 54 73 - 54 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure45a. Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 6 7 Command 5AH IO0 A23-16 A15-8 20 16 12 8 A7-0 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 11 8 9 10 11 12 13 IOs switch from Input to output Dummy* 4 0 4 0 4 0 4 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte1 Byte2 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 55 73 - 55 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Table 7.4. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed:50444653H Add(H) DW Add Data Data (Byte) (Bit) 00H 07:00 53H 53H 01H 15:08 46H 46H 02H 23:16 44H 44H 03H 31:24 50H 50H SFDP Minor Revision Number Start from 00H 04H 07:00 00H 00H SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H Number of Parameters Headers Start from 00H 06H 23:16 01H 01H Unused Contains 0xFFH and can never be 07H 31:24 FFH FFH 08H 07:00 00H 00H Start from 0x00H 09H 15:08 00H 00H Start from 0x01H 0AH 23:16 01H 01H Parameter Table Length How many DWORDs in the 0BH 31:24 09H 09H (in double word) Parameter table Parameter Table Pointer (PTP) First address of JEDEC Flash 0CH 07:00 30H 30H Parameter table 0DH 15:08 00H 00H 0EH 23:16 00H 00H 0FH 31:24 FFH FFH 10H 07:00 C8H C8H changed ID number (JEDEC) 00H: It indicates a JEDEC specified header Parameter Table Minor Revision Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed ID Number It is indicates GigaDevice (GigaDevice Manufacturer ID) manufacturer ID Parameter Table Minor Revision Start from 0x00H 11H 15:08 00H 00H Start from 0x01H 12H 23:16 01H 01H Parameter Table Length How many DWORDs in the 13H 31:24 03H 03H (in double word) Parameter table Parameter Table Pointer (PTP) First address of GigaDevice Flash 14H 07:00 60H 60H Parameter table 15H 15:08 00H 00H 16H 23:16 00H 00H 17H 31:24 FFH FFH Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed 56 73 - 56 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Table 7.5. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) Data Data 00: Reserved; 01: 4KB erase; Block/Sector Erase Size 10: Reserved; 01:00 01b 02 1b 03 0b 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction 0: Nonvolatile status bit Requested for Writing to Volatile 1: Volatile status bit Status Registers (BP status register bit) 0: Use 50H Opcode, Write Enable Opcode Select for Writing to Volatile Status Registers 30H E5H 1: Use 06H Opcode, Note: If target flash status register is 04 0b 07:05 111b 15:08 20H 16 1b 18:17 00b 19 0b Nonvolatile, then bits 3 and 4 must be set to 00b. Unused Contains 111b and can never be changed 4KB Erase Opcode 31H (1-1-2) Fast Read 0=Not support, 1=Support Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte, addressing flash array 10: 4Byte only, 11: Reserved Double Transfer Rate (DTR) clocking 0=Not support, 1=Support 32H (1-2-2) Fast Read 0=Not support, 1=Support 20 1b (1-4-4) Fast Read 0=Not support, 1=Support 21 1b (1-1-4) Fast Read 0=Not support, 1=Support 22 1b 23 1b 33H 31:24 FFH 37H:34H 31:00 Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-4-4) Fast Read Number of Mode Bits 000b:Mode Bits not support 39H (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support Mode Bits (1-1-4) Fast Read Opcode 3BH 57 73 - 57 FFH 00100b 44H 07:05 010b 15:08 EBH 20:16 01000b 3AH 000b:Mode Bits not support F1H 07FFFFFFH 38H (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of 04:00 20H EBH 08H 23:21 000b 31:24 6BH 6BH Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of Mode Bits of Wait states Clocks) not support 04:00 000b: Mode Bits not support 3FH 0=not support 1=support Unused 0=not support Data 1=support 40H Unused Data 01000b 08H 07:05 000b 15:08 3BH 20:16 00010b 3EH (1-2-2) Fast Read Opcode (4-4-4) Fast Read (Bit) 3DH 0 0000b: Wait states (Dummy (2-2-2) Fast Read DW Add (Byte) 000b: Mode Bits not support (1-2-2) Fast Read Number of Mode Bits Add(H) 3CH (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number GD25Q128C 3BH 42H 23:21 010b 31:24 BBH 00 0b 03:01 111b 04 1b 07:05 111b BBH FEH Unused 43H:41H 31:08 0xFFH 0xFFH Unused 45H:44H 15:00 0xFFH 0xFFH 20:16 00000b (2-2-2) Fast Read Number 0 0000b: Wait states (Dummy of Wait states Clocks) not support (2-2-2) Fast Read Number of Mode Bits 46H 000b: Mode Bits not support (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of Mode Bits Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 3 erase Opcode Sector Type 4 Size 000b 47H 31:24 FFH FFH 49H:48H 15:00 0xFFH 0xFFH 20:16 00100b 000b: Mode Bits not support Sector Type 1 erase Opcode Sector Type 2 Size 23:21 44H 4AH (4-4-4) Fast Read Opcode Sector Type 1 Size 00H Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 4 erase Opcode 58 73 - 58 23:21 010b 4BH 31:24 EBH EBH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C Table 7.6. Parameter Table (1): GigaDevice Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) 61H:60H 63H:62H Data Data 15:00 3600H 3600H 31:16 2700H 2700H 2000H=2.000V Vcc Supply Maximum Voltage 2700H=2.700V 3600H=3.600V 1650H=1.650V Vcc Supply Minimum Voltage 2250H=2.250V 2350H=2.350V 2700H=2.700V HW Reset# pin 0=not support 1=support 00 1b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 1b SW Reset Opcode Should be issue Reset Enable(66H) before Reset cmd. 65H:64H 11:04 1001 1001b (99H) F99FH Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 66H 23:16 77H 77H 67H 31:24 64H 64H 00 1b 01 0b 09:02 36H 10 0b Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 08H:support 8B wrap-around read Wrap-Around Read data length 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B Individual block lock Individual block lock bit (Volatile/Nonvolatile) 0=not support 0=Volatile 1=support 1=Nonvolatile Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect 6BH:68H Secured OTP 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 1b Unused 15:14 11b Unused 31:16 FFH 59 73 - 59 E8D9H FFH Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Vcc(max) Program, Erase and Write command are ignored Chip Selection is not allowed Vcc(min) VWI tVSL Reset State Read command is allowed Device is fully accessible tPUW Time Table 8.1. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC(min) To CS# Low 10 us tPUW Time Delay Before Write Instruction 1 10 ms VWI Write Inhibit Voltage 1 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status Register bits are set to 0, except DRV1 bit (S22) is set to 1. 8.3. DATA RETENTION AND ENDURANCE Parameter Minimum Pattern Data Retention Time Erase/Program Endurance Test Condition Min Units 150� 10 Years 125� 20 Years -40 to 85� 100K Cycles 8.4. LATCH UP CHARACTERISTICS Parameter Min Input Voltage Respect To VSS On I/O Pins VCC Current 60 73 - 60 Max -1.0V VCC+1.0V -100mA 100mA Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C 8.5. ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 � Storage Temperature -65 to 150 � Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V -0.5 to 4.0 V VCC 0.8VCC Input timing reference level 0.7VCC 0.2VCC 0.1VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are <5ns 8.6. CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 Input Rise And Fall time pF 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure46. Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 61 73 - 61 20ns Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q128C 8.7. DC CHARACTERISTICS (T= -40�� ��������� 2.7~3.6V) Symbol Parameter Test Condition Min. Typ Max. Unit. ILI Input Leakage Current ±2 �� ILO Output Leakage Current ±2 �� ICC1 Standby Current 15 50 �� 1 5 �� 15 20 mA 13 18 mA CS#=VCC, VIN=VCC or VSS ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS CLK=0.1VCC / 0.9VCC at 104MHz, ICC3 Operating Current (Read) Q=Open(*1 I/O) CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) ICC4 Operating Current (PP) CS#=VCC 10 mA ICC5 Operating Current(WRSR) CS#=VCC 10 mA ICC6 Operating Current (SE) CS#=VCC 10 mA ICC7 Operating Current (BE) CS#=VCC 10 mA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL =100uA 0.2 V VOH Output High Voltage IOH =-����� VCC-0.2 62 73 - 62 V Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 8.8. AC CHARACTERISTICS (T= -40�� ��������� 2.7~3.6V, CL=30pf) Parameter Symbol Min. Typ. Max. Unit. fC Serial Clock Frequency For All Instructions Except Read DC. 104 MHz fC1 Serial Clock Frequency For Quad Read Instructions (1) DC. 104/80 MHz fC2 Serial Clock Frequency For QPI Instructions DC. 80 MHz DC. 80 MHz fR Serial Clock Frequency For: Read(03H), Read Manufacturer ID/device ID(90H), Read Identification(9FH) tCLH Serial Clock High Time 4.5 ns tCLL Serial Clock Low Time 4.5 ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (read/write) 20 ns tSHQZ Output Disable Time tCLQX Output Hold Time tDVCH 6 ns 1.0 ns Data In Setup Time 2 ns tCHDX Data In Hold Time 2 ns tHLCH HOLD# Low Setup Time (relative to Clock) 5 ns tHHCH HOLD# High Setup Time (relative to Clock) 5 ns tCHHL HOLD# High Hold Time (relative to Clock) 5 ns tCHHH HOLD# Low Hold Time (relative to Clock) 5 ns tHLQZ HOLD# Low To High-Z Output 6 ns tHHQX HOLD# Low To Low-Z Output 6 ns tCLQV Clock Low To Output Valid 6.5 ns tWHSL Write Protect Setup Time Before CS# Low 20 ns tSHWL Write Protect Hold Time After CS# High 100 ns tDP CS# High To Deep Power-Down Mode tRES1 CS# High To Standby Mode Without Electronic Signature Read 20 �� 30 �� tRES2 CS# High To Standby Mode With Electronic Signature Read 30 �� tSUS CS# High To Next Command After Suspend 20 us tRST CS# High To Next Command After Reset 60 us tW Write Status Register Cycle Time 5 30 ms tBP1 Byte Program Time( First Byte) 30 50 us tBP2 Additional Byte Program Time ( After First Byte) 2.5 12 us tPP Page Programming Time 0.6 2.4 ms tSE Sector Erase Time 50 400 ms tBE Block Erase Time(32K Bytes) 0.2 1.0 s 63 73 - 63 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C tBE Block Erase Time(64K Bytes) 0.3 1.2 s tCE Chip Erase Time(GD25Q128C) 60 120 s Note: 1. Serial Clock Frequency for Quad Read Instructions fC1 is 104MHz maximum, when operating temperature is �80�. Serial Clock Frequency for Quad Read Instructions fC1 is 80MHz maximum, when 80�� operating temperature � 85� . Figure47. Serial Input Timing tSHSL CS# tCHSL SCLK tSLCH tDVCH tCHSH MSB SO High-Z tCHCL tCLCH tCHDX SI tSHCH LSB Figure48. Output Timing CS# tCLH SCLK tCLQV tCLQX tCLQV tSHQZ tCLL tCLQX LSB SO SI Least significant address bit (LIB) in Figure49. Hold Timing CS# SCLK SO tCHHL tHLCH tCHHH tHLQZ tHHCH tHHQX HOLD# SI do not care during HOLD operation. 7364- 64 Rev.1.0 3.3V Uniform 3.3V Sector Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C Figure50. RESET Timing tRB1 tRB2 CS# RESET# tRLRH tRHSL Reset Timing Symbol Parameter Setup Speed Unit. tRLRH Reset pulse width MIN 1 us tRHSL Reset high time before read MIN 50 ns tRB1 Reset recovery time (For NOT busy mode) MAX 5 us tRB2 Reset recovery time (For busy mode) MAX 60 us 65 73 - 65 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 9. ORDERING INFORMATION GD XX X XX X X X X X Packing Type Y:Tray R:Tape & Reel Green Code G:Pb Free & Halogen Free Green Package Temperature Range I:Industrial(-40� to +85�) Package Type P: DIP8 300mil S:SOP8 208mil V:VSOP8 208mil F:SOP16 300mil W: WSON8 (6*5mm) Y: WSON8 (8*6mm) Z:TFBGA24(6*4 Ball Array) Generation C: C Version Density 128:128Mb Series Q: 3V, 4KB Uniform Sector B: 3V, 4KB Uniform Sector, QE=1 Permanently Product Family 25:SPI Interface Flash 66 73 - 66 Rev.1.0 3.3V Uniform Sector 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx Dual and Quad Serial Flash GD25Q128C 10. PACKAGE INFORMATION 10.1. Package SOP8 208MIL 8 � 5 E1 E L1 L 1 4 C D A2 A1 b e A Dimensions Symbol A1 A2 b C D E E1 Min 0.05 1.70 0.31 0.18 5.13 7.70 5.18 Nom 0.15 1.80 0.41 0.21 5.23 7.90 5.28 0.25 1.91 0.51 0.25 5.33 8.10 Min 0.002 0.067 0.012 0.007 0.202 Nom 0.006 0.071 0.016 0.008 0.010 0.075 0.020 0.010 Unit mm Max Inch Max A 2.16 0.085 e L L1 � 0.50 1.21 0 0.67 1.31 5 5.38 0.85 1.41 8 0.303 0.204 0.020 0.048 0 0.206 0.311 0.208 0.026 0.052 5 0.210 0.319 0.212 0.033 0.056 8 1.27 0.050 Note�Both package length and width do not include mold flash. 67 73 - 67 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash 10.2. GD25Q128C Package VSOP8 208MIL 8 � 5 E1 E L1 L 1 4 C D A2 A1 b e A Dimensions Symbol A A1 A2 b D E E1 e L Min - 0.05 0.75 0.35 5.18 7.70 5.18 - 0.50 Nom - 0.10 0.80 0.42 5.28 7.90 5.28 1.27BSC 0.65 Max 1.00 0.15 0.85 0.48 5.38 8.10 5.38 - Min - 0.002 0.030 0.014 0.204 0.303 0.204 Nom - 0.004 0.031 0.017 0.208 0.311 Max 0.04 0.006 0.033 0.019 0.212 0.319 Unit mm Inch L1 C � 0.09 0° - - 0.80 0.2 10° - 0.020 0.004 0° 0.208 0.050BSC 0.026 0 - 0.212 - 0.031 0.008 10° 1.31REF 0.052REF Note�Both package length and width do not include mold flash. 68 73 - 68 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash 10.3. GD25Q128C Package SOP16 300MIL � 9 15 E1 E L1 L 1 8 C D A A2 A1 b e Dimensions Symbol A A1 A2 b C D E E1 Min 2.36 0.10 2.24 0.36 0.20 10.10 10.10 7.42 Nom 2.55 0.20 2.34 0.41 0.25 10.30 10.35 7.52 Max 2.75 0.30 2.44 0.51 0.30 10.50 10.60 Min 0.093 0.004 0.088 0.014 0.008 0.397 Nom 0.100 0.008 0.092 0.016 0.010 Max 0.108 0.012 0.096 0.020 0.012 Unit mm Inch e L L1 � 0.40 1.31 0 0.84 1.44 5 7.60 1.27 1.57 8 0.397 0.292 0.016 0.052 0 0.405 0.407 0.296 0.033 0.057 5 0.413 0.417 0.299 0.050 0.062 8 1.27 0.050 Note�Both package length and width do not include mold flash. 69 73 - 69 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash 10.4. GD25Q128C Package DIP8 300MIL 4 1 E 11° E1 R0.005xDP0.020 11° 5° C 5 eB 8 D A2 L A1 b b1 e Dimensions Symbol A1 A2 b b1 C D E E1 Min 0.38 3.00 1.27 0.38 0.20 9.05 7.62 6.12 Nom 0.72 3.25 1.46 0.46 0.28 9.32 7.94 6.38 Max 1.05 3.50 1.65 0.54 0.34 9.59 8.26 Min 0.015 0.118 0.05 0.015 0.008 0.356 Nom 0.028 0.128 0.058 0.018 0.011 Max 0.041 0.138 0.065 0.021 0.014 Unit mm Inch e eB L 7.62 3.04 8.49 3.30 6.64 9.35 3.56 0.300 0.242 0.333 0.12 0.367 0.215 0.252 0.345 0.13 0.378 0.366 0.262 0.357 0.14 2.54 0.1 Note�Both package length and width do not include mold flash. 70 73 - 70 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector 10.5. Dual and Quad Serial Flash GD25Q128C Package WSON 8 (6*5mm) D A2 y E A1 A Top View L Side View D1 b 1 E1 e Bottom View Dimensions Symbol Unit mm Inch A A1 A2 b D D1 E E1 e y L 0.00 0.50 0.04 0.60 Min 0.70 0.19 0.35 5.90 3.25 4.90 3.85 Nom 0.75 0.22 0.42 6.00 3.37 5.00 3.97 Max 0.80 0.25 0.48 6.10 3.50 5.10 4.10 0.08 0.75 Min 0.028 0.007 0.014 0.232 0.128 0.193 0.151 0.000 0.020 Nom 0.030 0.009 0.016 0.236 0.133 0.197 0.156 0.001 0.024 Max 0.032 0.010 0.019 0.240 0.138 0.201 0.161 0.003 0.030 0.05 0.002 1.27 0.05 Note�Both package length and width do not include mold flash. 71 73 - 71 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector 10.6. Dual and Quad Serial Flash GD25Q128C Package WSON 8 (8*6mm) D A2 y E A1 A Top View L Side View D1 b 1 E1 e Bottom View Dimensions Symbol Unit mm Inch A Min 0.70 Nom 0.75 Max 0.80 Min 0.028 Nom 0.030 Max 0.032 A1 A2 0.20 0.05 0.008 0.002 b D D1 E E1 e K L 0.35 7.90 3.25 5.90 4.15 0.40 8.00 3.42 6.00 4.22 0.45 8.10 3.50 6.10 4.40 0.65 0.014 0.311 0.128 0.232 0.163 0.022 0.016 0.315 0.135 0.236 0.166 0.019 0.319 0.138 0.240 0.173 0.55 1.27 0.050 1.80 0.071 0.60 0.024 0.027 Note�Both package length and width do not include mold flash. 72 73 - 72 Rev.1.0 3.3V Uniform sector dual and quad serial flash GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash 10.7. GD25Q128C Package TFBGA-24BALL (6*4 ball array) 1 2 3 4 4 3 2 1 A A e B B C C E1 E D D E E F F e D D1 �b A1 A A2 Dimensions Symbol A mm D 0.35 5.90 0.40 6.00 0.35 0.45 6.10 8.10 Min 0.010 0.014 0.232 0.311 Nom 0.012 0.016 0.236 0.018 0.240 Min 0.25 Nom 0.30 Max Inch A1 Max 1.20 0.047 0.014 A2 0.85 0.033 D1 E b Unit E1 e 5.00 1.00 0.200 0.039 7.90 3.00 0.120 8.00 0.315 0.319 Note�Both package length and width do not include mold flash. 73 73 - 73 Rev.1.0