FM4 Family 32-BIT Microcontroller FM4 Peripheral Manual GDC Part Errata Sheet Page Item Description Original document code: MN709-00014-1v0-E Rev. 1.0 February 25, 2015 28 CHAPTER 2 4. Registers 4.5 GPCR4 “GPLLN: PLL feedback frequency division ratio setting bits” should be corrected as below. (Error) bit[6:0] Description 000000 setting is prohibited 000001 setting is prohibited setting is prohibited 0001011 setting is prohibited 0001100 1/13 0001101 1/14 1/(GPLLN[6:0] + 1) 0011111 1/32 010000 setting is prohibited setting is prohibited 1111111 setting is prohibited (Correct) bit[6:0] Description 000000 to setting is prohibited 0001011 0001100 Division ratio: 1/13 0001101 Division ratio: 1/14 (Continued) 1100011 (minimal value) Division ratio: 1/(GPLLN[6:0]+1) Division ratio: 1/100 (maximum value) 1100100 to setting is prohibited 1111111 Publication Number FM4_MN709-00014-1v0-E-DE CONFIDENTIAL Revision 3.0 Issue Date September 16, 2015 E R R A T A Page Item S H E E T Description Rev. 2.0 September 04, 2015 6 The target products “Table 4 TYPE4-M4 Product list” should be corrected as below. in this manual (Error) Flash memory size 384 Kbytes Description in this manual TYPE4-M4 VRAM Size VRAM 512 Kbytes + VFLASH 2 Mbytes 512 Kbytes 384 Kbytes S6E2D35G0AGB10 S6E2D35G0AGV20 S6E2D35G0AGZ20 S6E2D35J0AGV20 S6E2D35J0AGZ20 S6E2D35GAAGB10 S6E2D35GAAGV20 S6E2D35GAAGZ20 S6E2D35JAAGV20 S6E2D35JAAGZ20 S6E2D35GJAMV20 S6E2D55G0AGB10 S6E2D55G0AGV20 S6E2D55G0AGZ20 S6E2D55J0AGV20 S6E2D55J0AGZ20 S6E2D55GAAGB10 S6E2D55GAAGV20 S6E2D55GAAGZ20 S6E2D55JAAGV20 S6E2D55JAAGZ20 S6E2D55GJAMV20 S6E2DF5G0AGB10 S6E2DF5G0AGV20 S6E2DF5G0AGZ20 S6E2DF5J0AGV20 S6E2DF5J0AGZ20 S6E2DF5GAAG10 S6E2DF5GAAGV20 S6E2DF5GAAGZ20 S6E2DF5JAAGV20 S6E2DF5JAAGZ20 S6E2DF5GJAMV20 S6E2DH5G0AGB10 S6E2DH5G0AGV20 S6E2DH5G0AGZ20 S6E2DH5J0AGV20 S6E2DH5J0AGZ20 S6E2DH5GAAGB10 S6E2DH5GAAGV20 S6E2DH5GAAGZ20 S6E2DH5JAAGV20 S6E2DH5JAAGZ20 S6E2DH5GJAMV20 (Correct) Flash memory size 384 Kbytes Description in this manual VRAM 512 Kbytes VRAM 512 Kbytes + VFLASH 2 Mbytes S6E2D35G0AGB30 S6E2D35G0AGV20 S6E2D35G0AGE20 S6E2D35J0AGV20 S6E2D35GJAMV20 S6E2D55G0AGB30 S6E2D55G0AGV20 S6E2D55G0AGE20 S6E2D55J0AGV20 S6E2D55GJAMV20 S6E2DF5G0AGB30 S6E2DF5G0AGV20 S6E2DF5G0AGE20 S6E2DF5J0AGV20 S6E2DF5GJAMV20 S6E2DH5G0AGB30 S6E2DH5G0AGV20 S6E2DH5G0AGE20 S6E2DH5J0AGV20 S6E2DH5GJAMV20 TYPE4-M4 2 CONFIDENTIAL FM4_MN709-00014-1v0-E-DE3, September 16, 2015 E R R A T A Page S H E E T Item 116 Appendixes Description The register of Clock/Reset should be corrected as indicated by shading bellow. A.Register Map 1.Register Map (Error) 1.4 Clock/Reset Register Base_Address + Address +3 +2 +1 0x068 - - - 0x06C – 0xFFC - - - - +0 +0 INT_CLR[W] -0-000 (Correct) Register Base_Address + Address +3 +2 +1 0x068 - - - 0x06C – 0x070 - - - 228 Appendixes -0-000 - PLLCG_CTL[W] 0x074 0x078 – 0xFFC INT_CLR[W] -------- 11111111 00000000 00----00 - - - - Base_Address of GDC Sub system SDRAM controller should be corrected as indicated by the shading bellow. A.Register Map 1.Register Map 1.48 GDC Sub (Error) GDC Sub system SDRAM controller Base_Address : 0xD0A3_0000 System SDRAM Controller (Correct) GDC Sub System SDRAM Controller September 16, 2015, FM4_MN709-00014-1v0-E-DE3 CONFIDENTIAL Base_Address : 0xD0A0_3000 3 E R R A T A Page Item S H E E T Description Rev. 3.0 September 16, 2015 12 1.Overview 1.1 Feature Summary Note should be added as indicated by the shading below. (Error) 1.1.1 General Features 1.1.1 General features Controller for external graphics display. Accelerator for 2D block image transfer (blit) operations. Embedded SRAM video memory. Multilayer GDC bus matrix with master and slave ports. Signature computation for display content (use: data integrity/safety requirements) Command Sequencer for graphic operations. Quad SPI (Serial Peripheral Interface) for external memory extensions. SDRAM interface for external memory extensions. HBI (Hyper Bus Interface) interface for external memory extensions. Two processing pipeline (blit / display). Maximum core system clock frequency: Refer to the Data sheet. (Correct) 1.1.1 General Features Controller for external graphics display. Accelerator for 2D block image transfer (blit) operations. Embedded SRAM video memory. Multilayer GDC bus matrix with master and slave ports. Signature computation for display content (use: data integrity/safety requirements) Command Sequencer for graphic operations. Quad SPI (Serial Peripheral Interface) for external memory extensions. SDRAM interface for external memory extensions. HBI (Hyper Bus Interface) interface for external memory extensions. Two processing pipeline (blit / display). Maximum core system clock frequency: Refer to the Data sheet. Note: − User can leverage internal VRAM and external HyperRAM as a graphics memory allowed to be written by GDC. 4 CONFIDENTIAL FM4_MN709-00014-1v0-E-DE3, September 16, 2015