AMCC PPC405EP

Part Number PPC405EP
Revision 1.07 – September 10, 2007
PPC405EP
Data Sheet
PowerPC 405EP Embedded Processor
Features
•
•
•
•
•
•
AMCC PowerPC® 405 32-bit RISC processor
core operating up to 333MHz with 16KB Dand I-caches
PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
4KB on-chip memory (OCM)
External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8- or 16-bit SRAM and
external peripherals
- Up to five devices
DMA support for memory and UARTs.
- Scatter-gather chaining supported
- Four channels
PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
•
•
•
•
•
•
•
•
•
•
- Asynchronous PCI Bus interface
- Internal or external PCI Bus Arbiter
Two Ethernet 10/100Mbps (full-duplex) ports
with media independent interface (MII)
Programmable interrupt controller supports
seven external and 19 internal edge-triggered
or level-sensitive interrupts
Programmable timers
Software accessible event counters
Two serial ports (16750 compatible UART)
One IIC interface
General purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal processor local bus (PLB) runs at
SDRAM interface frequency
Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded
applications, the PowerPC 405EP (PPC405EP)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus interface,
AMCC
Ethernet interface, control for external ROM and
peripherals, DMA with scatter-gather support, serial
ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-27E, 0.18 μm (0.11 μm Leff)
Package: 31mm, 385-ball, enhanced plastic ball grid
array (E-PBGA)
Power (typical): 0.72W at 266MHz
1
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
List of Figures
PPC405EP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
31mm, 385-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
List of Tables
System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I/O Specifications—Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I/O Specifications—Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
AMCC
3
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local AMCC sales office.
Product Name
Order Part Number1, 2
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
PPC405EP
PPC405EP-3GB133C
133MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB133CZ
133MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB133C
133MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB133CZ
133MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB200C
200MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB200CZ
200MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB200C
200MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB200CZ
200MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB266C
266MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB266CZ
266MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB266C
266MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB266CZ
266MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB333C
333MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3GB333CZ
333MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB333C
333MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
PPC405EP
PPC405EP-3LB333CZ
333MHz
31mm, 385 ball E-PBGA
B
0x51210950
0x20267049
Notes: 1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
2. Package type G contains lead; package type L is lead-free.
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask
revision number and is specified in the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the PowerPC 405EP Embedded Processor User’s Manual for
details on accessing these registers.
Order Part Number Key
PPC405EP-3GB333Cx
Shipping Package
Blank = Tray
Z = Tape and reel
Part Number
Grade 3 Reliability
Package
4
Operational Case Temperature
Range (-40°C to +85°C)
Processor Speed (MHz)
Revision Level
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Figure 1. PPC405EP Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
OCM
SRAM
Timers
DOCM
MMU
IOCM
OCM
Control
PPC405
Processor Core
16KB
D-Cache
JTAG
Trace
DCU
ICU
Event
Counters
DCRs
GPIO
DCR Bus
16KB
I-Cache
UART
x2
GPT
On-chip Peripheral Bus (OPB)
Arb
DMA
Controller
(4-Channel)
Arb
IIC
OPB
Bridge
MAL
Ethernet
x2
Processor Local Bus (PLB)
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
29-bit addr
16-bit data
PCI Bridge
66 MHz max (async)
MII
The PPC405EP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
AMCC
5
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Address Maps
The PPC405EP incorporates two address maps. The first address map defines the possible use of addressable
memory regions that the processor can access. The second address map defines Device Configuration Register
(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EP processor through
the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (4GB System Memory)
Function
General Use
Boot-up
Subfunction
SDRAM, External Peripherals, and PCI
Memory
Note: Any of the address ranges listed at
right may be use for any of the above
functions.
Size
0xE7FFFFFF
3712MB
0xE8010000
0xE87FFFFF
8MB
0xEC000000
0xEEBFFFFF
44MB
0xEEE00000
0xEF3FFFFF
6MB
0xEF500000
0xEF5FFFFF
1MB
0xEF900000
0xFFFFFFFF
263MB
0xFFFFFFFF
2MB
0xFFFE0000
0xFFFFFFFF
128KB
0xE8000000
0xE800FFFF
64KB
PCI I/O
0xE8800000
0xEBFFFFFF
56MB
Configuration Registers
0xEEC00000
0xEEC00007
8B
Interrupt Acknowledge and Special Cycle
0xEED00000
0xEED00003
4B
Local Configuration Registers
0xEF400000
0xEF40003F
64B
GPT
0xEF600000
0xEF6000FF
256B
UART0
0xEF600300
0xEF600307
8B
UART1
0xEF600400
0xEF600407
8B
IIC0
0xEF600500
0xEF60051F
32B
OPB Arbiter
0xEF600600
0xEF60063F
64B
GPIO Controller Registers
0xEF600700
0xEF60077F
128B
Ethernet 0 Controller Registers
0xEF600800
0xEF6008FF
256B
Ethernet 1 Controller Registers
0xEF600900
0xEF6009FF
256B
2
PCI I/O
Internal Peripherals
End Address
0x00000000
0xFFE00000
Peripheral Bus Boot 1
PCI Boot
PCI
Start Address
Notes:
1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.
3. After the boot process, software may reassign the boot memory regions for other uses.
4. All address ranges not listed above are reserved.
6
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 2. DCR Address Map
Function
Total DCR Address Space1
Start Address
End Address
Size
0x000
0x3FF
1KW (4KB)1
16W
By function:
Reserved
0x000
0x00F
Memory Controller Registers
0x010
0x011
2W
External Bus Controller Registers
0x012
0x013
2W
Reserved
0x014
0x017
2W
On-Chip Memory Controller Registers
0x018
0x01F
8W
Reserved
0x020
0x07F
96W
PLB Registers
0x080
0x08F
16W
16W
Reserved
0x090
0x09F
OPB Bridge Out Registers
0x0A0
0x0A7
8W
Reserved
0x0A8
0x0AF
6W
Clock, Control, and Reset
0x0B0
0x0B7
8W
Power Management
0x0B8
0x0BF
8W
Interrupt Controller
0x0C0
0x0CF
16W
Reserved
0x0D0
0x0FF
48W
DMA Controller Registers
0x100
0x13F
64W
Reserved
0x140
0x17F
64W
Ethernet MAL Registers
0x180
0x1FF
128W
Event Counters
0x200
0x203
4W
Reserved
0x204
0x3FF
508W
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register, or 1 kiloword (KW) (which equals 4 KB).
AMCC
7
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the
processor core.
Features include:
•
•
•
Low-latency access to critical instructions and data
Performance identical to cache hits without misses
Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor
and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features include:
•
•
•
•
•
•
•
•
•
•
•
8
internal pci bus arbiter for up to three external devices at PCI bus speeds up to 66MHz. Internal arbiter use
is optional and can be disabled for systems which employ an external arbiter.
PCI bus frequency up to 66MHz
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
32-bit PCI address/data bus
Power Management:
- PCI Bus Power Management v1.1 compliant
Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
Buffering between PLB and PCI:
- PCI target 64-byte write post buffer
- PCI target 96-byte read prefetch buffer
- PLB slave 32-byte write post buffer
- PLB slave 64-byte read prefetch buffer
Error tracking/status
Supports PCI target side configuration
Supports processor access to all PCI address spaces:
- Single-beat PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-beat PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
SDRAM Memory Controller
The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to two physical banks. Up to
256MB per bank are supported, up to a maximum of 512MB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
•
•
•
•
•
•
•
•
•
•
•
11x8 to 13x11 addressing for SDRAM (2 banks)
32-bit memory interface support
Programmable address compare for each bank of memory
Industry standard 168-pin DIMMS are supported (some configurations)
Up to 133MHz memory supported by the 266MHz processor
Up to 111MHz memory supported by the 333MHz processor
4MB to 256MB per bank
Programmable address mapping and timing
Auto refresh
Page mode accesses with up to 4 open pages
Power management (self-refresh)
External Peripheral Bus Controller (EBC)
•
•
•
•
•
•
•
•
•
Supports five banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
Up to 66MHz operation
Burst and non-burst devices
8- and 16-bit byte-addressable data bus width support
Latch data on Ready, synchronous or asynchronous
Programmable 2K clock time-out counter with disable for Ready
Programmable access timing per device
- 0–255 wait states for non-bursting devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
Programmable address mapping
Peripheral Device pacing with external “Ready”
DMA Controller
•
•
•
•
•
•
AMCC
Supports memory-to-memory transfers
Four channels
Scatter/gather capability for programming multiple DMA operations
32-bit addressing
Address increment or decrement
Internal 32-byte data buffering capability
9
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Serial Interface
•
•
•
•
•
•
•
One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided
Internal serial clock to allows a wide range of baud rates
Register compatibility with NS16750 register set
Complete status reporting capability
Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
Fully programmable serial-interface characteristics
Supports DMA using internal DMA engine
IIC Bus Interface
•
•
•
•
•
•
•
•
Compliant with Phillips® Semiconductors I2C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed VDD IIC interface
•
•
•
•
•
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
General Purpose IO (GPIO) Controller
•
•
•
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose.
Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, threestated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the local PowerPC processor.
Features include:
•
•
•
•
•
•
10
Supports seven external and 19 internal interrupts
Edge-triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to processor core
Programmable critical interrupt priority ordering
Programmable critical interrupt vector for faster vector processing
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
10/100 Mbps Ethernet MAC
•
•
Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation
Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
JTAG
•
•
•
AMCC
IEEE 1149.1 test access port
IBM RISCWatch debugger support
JTAG Boundary Scan Description Language (BSDL)
11
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Figure 2. 31mm, 385-Ball E-PBGA Package
Top View
Logo View
Gold Gate Release
Corresponds to
A01 Ball Location
®
PPC405EP
1YWWBZZZZZ
15.5 TYP
Lot Number
Part Number
C
Notes: 1. All dimensions are in mm.
2. Package available in leaded and lead-free configurations.
0.20 C
0.25 C
A
0.20
31.0
Bottom View
AB
Y
V
T
31.0 ± 0.2
P
M
K
H
F
D
B
B
27.98
AC
1.27 TYP
AA
Mold
Compound
W
U
R
Thermal Balls
N
PCB
Substrate
L
J
G
E
C
A
01 03 05 07 09 11 13 15 17 19 21 23
02 04 06 08 10 12 14 16 18 20 22
0.65 ± 0.05 SOLDERBALL x 385
∅ 0.30 s C A s B s
∅ 0.15 s C
12
0.35 C
0.6±0.1
2.36 REF
2.65 max
2.07 min
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Pin Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the
signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate
signal in brackets. Shared signals appear alphabetically multiple times in the list—once for each signal assigned to
the ball. The page number listed gives the page in “Signal Functional Description” on page 31 where the signals in
the indicated interface group begin.
Table 3. Signals Listed Alphabetically (Sheet 1 of 10)
Signal Name
Ball
AGND
AB21
AVDD
AC20
BA0
Y15
BA1
AC16
BankSel0
AB13
BankSel1
AC13
CAS
Y14
ClkEn0
AB14
ClkEn1
AC14
DQM0
AC10
DQM1
AA7
DQM2
W04
DQM3
U02
Interface Group
Page
System
35
SDRAM
33
SDRAM
33
SDRAM
33
SDRAM
33
SDRAM
33
EMCMDClk
Y06
Ethernet
32
EMCMDIO
AA5
Ethernet
32
EMC0Tx0D0
U03
EMC0Tx0D1
N03
EMC0Tx0D2
L01
Ethernet
32
EMC0Tx0D3
P03
EMC0Tx0En
W01
Ethernet
32
EMC0Tx0Err
V03
Ethernet
32
EMC0Tx1D0
B15
EMC0Tx1D1
C14
EMC0Tx1D2
A15
Ethernet
32
EMC0Tx1D3
D14
32
EMC0Tx1En
A16
Ethernet
EMC0Tx1Err
C15
Ethernet
32
ExtReset
A03
External Slave Peripheral
33
AMCC
13
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 10)
Signal Name
Ball
GND
A01
GND
A02
GND
A07
GND
A12
GND
A17
GND
A22
GND
A23
GND
B01
GND
B02
GND
B22
GND
B23
GND
C03
GND
C21
GND
D04
GND
D20
GND
E05
GND
E09
GND
E12
GND
E15
GND
E19
GND
G01
GND
G23
GND
J05
GND
J19
GND
K10K14
GND
L10L14
14
Interface Group
Page
Ground
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls.
35
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 10)
Signal Name
GND
Ball
GND
M05
GND
M10M14
GND
M19
GND
M20
GND
M23
GND
N10N14
GND
P10P14
GND
R05
GND
R19
GND
U01
GND
U23
GND
W05
GND
W09
GND
W12
GND
W15
GND
W19
GND
Y04
GND
Y20
GND
AA03
GND
AA21
GND
AB01
GND
AB02
GND
AB22
GND
AB23
GND
AC01
GND
AC02
GND
AC07
GND
AC12
GND
AC17
GND
AC22
GND
AC23
AMCC
Interface Group
Page
Power
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls.
35
M01
15
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 10)
Signal Name
GPIO00[PerBLast]
Ball
GPIO01[TS1E]
AA23
GPIO02[TS2E]
Y22
GPIO03[TS1O]
Y23
GPIO04[TS2O]
W21
GPIO05[TS3]
U20
GPIO06[TS4]
V23
GPIO07[TS5]
U21
GPIO08[TS6]
U22
GPIO09[TrcClk]
T21
GPIO10[PerCS1]
C02
GPIO11[PerCS2]
E03
GPIO12[PerCS3]
D03
GPIO13[PerCS4]
D05
GPIO14[PerAddr03]
B04
GPIO15[PerAddr04]
A04
GPIO16[PerAddr05]
A05
GPIO17[IRQ0]
W22
GPIO18[IRQ1]
W23
GPIO19[IRQ2]
V21
GPIO20[IRQ3]
V22
GPIO21[IRQ4]
T22
GPIO22[IRQ5]
R20
GPIO23[IRQ6]
T23
GPIO24[UART0_DCD]
M04
GPIO25[UART0_DSR]
K01
GPIO26[UART0_RI]
L04
GPIO27[UART0_DTR]
J01
GPIO28[UART1_Rx]
J02
GPIO29[UART1_Tx]
J03
GPIO30[RejectPkt0]
W20
GPIO31[RejectPkt1]
Y21
Halt
C22
IICSCL
AB4
IICSDA
Y01
[IRQ0]GPIO17
W22
[IRQ1]GPIO18
W23
[IRQ2]GPIO19
V21
[IRQ3]GPIO20
V22
[IRQ4]GPIO21
T22
[IRQ5]GPIO22
R20
[IRQ6]GPIO23
T23
16
Interface Group
Page
A09
System
35
System
35
Internal Peripheral
34
Interrupts
34
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 10)
Signal Name
Ball
MemAddr00
AB15
MemAddr01
AB16
MemAddr02
AB17
MemAddr03
AA17
MemAddr04
AC18
MemAddr05
AA18
MemAddr06
AC19
MemAddr07
AB19
MemAddr08
Y18
MemAddr09
AA19
MemAddr10
Y19
MemAddr11
AA20
MemAddr12
AC21
MemClkOut0
AA14
MemClkOut1
Y13
MemData00
AB12
MemData01
AA12
MemData02
AC11
MemData03
AA11
MemData04
Y11
MemData05
AA10
MemData06
AC9
MemData07
AB9
MemData08
AC8
MemData09
Y09
MemData10
AA8
MemData11
AB7
MemData12
AB6
MemData13
Y07
MemData14
AA6
MemData15
AC5
MemData16
AB5
MemData17
AC4
MemData18
Y05
MemData19
AA4
MemData20
AB3
MemData21
Y03
MemData22
W03
MemData23
V04
MemData24
W02
MemData25
U04
MemData26
V02
MemData27
T04
MemData28
T02
MemData29
R04
MemData30
R03
MemData31
R02
AMCC
Interface Group
Page
SDRAM
Note: During a CAS cycle MemAddr00 is the least significant bit (lsb) on this bus.
33
SDRAM
33
SDRAM
Note: MemData00 is the most significant bit (msb) on this bus.
33
17
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 10)
Signal Name
Ball
OVDD
B11
OVDD
B09
OVDD
B19
OVDD
C17
OVDD
D13
OVDD
E06
OVDD
E07
OVDD
E08
OVDD
E16
OVDD
E17
OVDD
E18
OVDD
E21
OVDD
F05
OVDD
F19
OVDD
F23
OVDD
G05
OVDD
G19
OVDD
H05
OVDD
H19
OVDD
H22
OVDD
K04
OVDD
K20
OVDD
K23
OVDD
M22
OVDD
N01
OVDD
P20
OVDD
P23
OVDD
T05
OVDD
T19
OVDD
T20
OVDD
U05
OVDD
U19
OVDD
V01
OVDD
V05
OVDD
V19
OVDD
W06
OVDD
W07
OVDD
W08
OVDD
W16
OVDD
W17
OVDD
W18
OVDD
Y12
OVDD
AC06
18
Interface Group
Page
Power
35
Power
35
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 10)
Signal Name
Ball
PCIAD00
B16
PCIAD01
C16
PCIAD02
B17
PCIAD03
D16
PCIAD04
B18
PCIAD05
D17
PCIAD06
C18
PCIAD07
A19
PCIAD08
D18
PCIAD09
C19
PCIAD10
A20
PCIAD11
B20
PCIAD12
C20
PCIAD13
C23
PCIAD14
D21
PCIAD15
D22
PCIAD16
J22
PCIAD17
J23
PCIAD18
K21
PCIAD19
K22
PCIAD20
L21
PCIAD21
L22
PCIAD22
L23
PCIAD23
M21
PCIAD24
N23
PCIAD25
N22
PCIAD26
N21
PCIAD27
P22
PCIAD28
P21
PCIAD29
R23
PCIAD30
R22
PCIAD31
R21
PCIC0/BE0
A18
PCIC1/BE1
D19
PCIC2/BE2
L20
PCIC3/BE3
N20
Interface Group
Page
PCI
Note: PCIAD31 is the most significant bit (msb) on this bus.
31
PCI
31
PCIClk
B21
PCI
31
PCIDevSel
H21
PCI
31
PCIFrame
F22
PCI
31
PCI
31
PCI
31
PCI
31
PCIGnt0/Req
D23
PCIGnt1
E23
PCIGnt2
F21
PCIIDSel
A21
PCIINT[PerWE]
D15
PCI
31
PCIIRDY
H20
PCI
31
PCIParity
J21
PCI
31
PCIPErr
H23
PCI
31
AMCC
19
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 8 of 10)
Signal Name
PCIReq0/Gnt
Ball
Interface Group
Page
E20
PCIReq1
F20
PCIReq2
E22
PCIReset
G20
PCI
31
PCISErr
J20
PCI
31
PCIStop
G22
PCI
31
PCITRDY
G21
PCI
31
[PerAddr03]GPIO14
B04
[PerAddr04]GPIO15
A04
External Slave Peripheral
Note: PerAddr3 is the most significant bit (msb) on this bus.
33
[PerAddr05]GPIO16
A05
PerAddr06
D07
PerAddr07
B06
PerAddr08
A06
PerAddr09
D08
PerAddr10
C07
PerAddr11
B07
PerAddr12
C08
PerAddr13
B08
PerAddr14
D09
PerAddr15
A08
PerAddr16
C09
PerAddr17
D10
PerAddr18
C10
PerAddr19
B10
PerAddr20
D11
PerAddr21
A10
PerAddr22
C11
PerAddr23
A11
PerAddr24
D12
PerAddr25
B12
PerAddr26
C12
PerAddr27
A13
PerAddr28
B13
PerAddr29
C13
PerAddr30
A14
PerAddr31
B14
PCI
31
[PerBLast]GPIO00
A09
External Slave Peripheral
33
PerClk
C04
External Slave Peripheral
33
PerCS0
E04
[PerCS1]GPIO10
C02
External Slave Peripheral
33
[PerCS2]GPIO11
E03
[PerCS3]GPIO12
D03
[PerCS4]GPIO13
D05
20
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 9 of 10)
Signal Name
Ball
PerData00
P02
PerData01
N04
PerData02
P01
PerData03
M02
PerData04
M03
PerData05
L02
PerData06
L03
PerData07
K02
PerData08
K03
PerData09
H01
PerData10
J04
PerData11
G02
PerData12
G04
PerData13
H04
PerData14
F01
PerData15
D01
Interface Group
External Slave Peripheral
Note: PerData00 is the most significant bit (msb) on this bus.
Page
33
PerOE
F04
External Slave Peripheral
33
PerReady
B03
External Slave Peripheral
33
PerR/W
D02
External Slave Peripheral
33
PerWBE0
F03
External Slave Peripheral
33
PerWBE1
E01
External Slave Peripheral
33
Ethernet
32
Ethernet
32
Ethernet
32
Ethernet
32
[PerWE]PCIINT
D15
PHY0Col0
AB8
PHY0Col1
C05
PHY0CrS0
AA9
PHY0CrS1
B05
PHY0Rx0Clk
AB10
PHY0Rx0D0
Y16
PHY0Rx0D1
AA22
PHY0Rx0D2
AA16
PHY0Rx0D3
AA13
PHY0Rx0DV
Y10
Ethernet
32
PHY0Rx0Err
AB11
Ethernet
32
PHY0Rx1Clk
E02
Ethernet
32
PHY0Rx1D0
R01
Ethernet
32
PHY0Rx1D1
H03
PHY0Rx1D2
G03
PHY0Rx1D3
F02
PHY0Rx1DV
D06
Ethernet
32
PHY0Rx1Err
C01
Ethernet
32
PHY0Tx0Clk
Y08
PHY0Tx1Clk
C06
Ethernet
32
System
35
SysClk
AB18
RAS
AA15
SDRAM
33
[RejectPkt0]GPIO30
W20
System
35
[RejectPkt1]GPIO31
Y21
System
35
Other
36
System
35
Reserved
SysErr
AMCC
–
Y17
21
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 10 of 10)
Signal Name
SysReset
Ball
AB20
Interface Group
Page
System
35
TCK
Y02
JTAG
34
TDI
AA1
JTAG
34
TDO
AA2
JTAG
34
TestEn
V20
System
35
TMS
AC3
JTAG
34
TRST
H02
JTAG
34
Trace
35
Trace
35
Internal Peripheral
34
Internal Peripheral
34
Power
35
SDRAM
33
[TS1E]GPIO01
AA23
[TS2E]GPIO02
Y22
[TS1O]GPIO03
Y23
[TS2O]GPIO04
W21
[TS3]GPIO05
U20
[TS4]GPIO06
V23
[TS5]GPIO07
U21
[TS6]GPIO08
U22
[TrcClk]GPIO09
T21
UART0_CTS
T03
[UART0_DCD]GPIO24
M04
[UART0_DSR]GPIO25
K01
[UART0_DTR]GPIO27
J01
[UART0_RI]GPIO26
L04
UART0_RTS
N02
UART0_Rx
T01
UART0_Tx
P04
[UART1_Rx]GPIO28
J02
[UART1_Tx]GPIO29
J03
VDD
E10
VDD
E11
VDD
E13
VDD
E14
VDD
K05
VDD
K19
VDD
L05
VDD
L19
VDD
N05
VDD
N19
VDD
P05
VDD
P19
VDD
W10
VDD
W11
VDD
W13
VDD
W14
WE
AC15
22
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 1 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
A01
GND
B01
GND
C01
PHY0Rx1Err
D01
PerData15
A02
GND
B02
GND
C02
GPIO10[PerCS1]
D02
PerR/W
A03
ExtReset
B03
PerReady
C03
GND
D03
GPIO12[PerCS3]
A04
GPIO15[PerAddr04]
B04
GPIO14[PerAddr03]
C04
PerClk
D04
GND
A05
GPIO16[PerAddr05]
B05
PHY0CrS1
C05
PHY0Col1
D05
GPIO13[PerCS4]
A06
PerAddr08
B06
PerAddr07
C06
PHY0Tx1Clk
D06
PHY0Rx1DV
A07
GND
B07
PerAddr11
C07
PerAddr10
D07
PerAddr06
A08
PerAddr15
B08
PerAddr13
C08
PerAddr12
D08
PerAddr09
A09
GPIO00[PerBLast]
B09
OVDD
C09
PerAddr16
D09
PerAddr14
A10
PerAddr21
B10
PerAddr19
C10
PerAddr18
D10
PerAddr17
A11
PerAddr23
B11
OVDD
C11
PerAddr22
D11
PerAddr20
A12
GND
B12
PerAddr25
C12
PerAddr26
D12
PerAddr24
A13
PerAddr27
B13
PerAddr28
C13
PerAddr29
D13
OVDD
A14
PerAddr30
B14
PerAddr31
C14
EMC0Tx1D1
D14
EMC0Tx1D3
A15
EMC0Tx1D2
B15
EMC0Tx1D0
C15
EMC0Tx1Err
D15
PCIINT[PerWE]
A16
EMC0Tx1En
B16
PCIAD00
C16
PCIAD01
D16
PCIAD03
A17
GND
B17
PCIAD02
C17
OVDD
D17
PCIAD05
A18
PCIC0/BE0
B18
PCIAD04
C18
PCIAD06
D18
PCIAD08
A19
PCIAD07
B19
OVDD
C19
PCIAD09
D19
PCIC1/BE1
A20
PCIAD10
B20
PCIAD11
C20
PCIAD12
D20
GND
A21
PCIIDSel
B21
PCIClk
C21
GND
D21
PCIAD14
A22
GND
B22
GND
C22
Halt
D22
PCIAD15
A23
GND
B23
GND
C23
PCIAD13
D23
PCIGnt0/Req
AMCC
23
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
E01
PerWBE1
F01
PerData14
G01
GND
H01
PerData09
E02
PHY0Rx1Clk
F02
PHY0Rx1D3
G02
PerData11
H02
TRST
E03
GPIO11[PerCS2]
F03
PerWBE0
G03
PHY0Rx1D2
H03
PHY0Rx1D1
E04
PerCS0
F04
PerOE
G04
PerData12
H04
PerData13
E05
GND
F05
OVDD
G05
OVDD
H05
OVDD
E06
OVDD
F06
No ball
G06
No ball
H06
No ball
E07
OVDD
F07
No ball
G07
No ball
H07
No ball
E08
OVDD
F08
No ball
G08
No ball
H08
No ball
E09
GND
F09
No ball
G09
No ball
H09
No ball
E10
VDD
F10
No ball
G10
No ball
H10
No ball
E11
VDD
F11
No ball
G11
No ball
H11
No ball
E12
GND
F12
No ball
G12
No ball
H12
No ball
E13
VDD
F13
No ball
G13
No ball
H13
No ball
E14
VDD
F14
No ball
G14
No ball
H14
No ball
E15
GND
F15
No ball
G15
No ball
H15
No ball
E16
OVDD
F16
No ball
G16
No ball
H16
No ball
E17
OVDD
F17
No ball
G17
No ball
H17
No ball
E18
OVDD
F18
No ball
G18
No ball
H18
No ball
E19
GND
F19
OVDD
G19
OVDD
H19
OVDD
E20
PCIReq0/Gnt
F20
PCIReq1
G20
PCIReset
H20
PCIIRDY
E21
OVDD
F21
PCIGnt2
G21
PCITRDY
H21
PCIDevSel
E22
PCIReq2
F22
PCIFrame
G22
PCIStop
H22
OVDD
E23
PCIGnt1
F23
OVDD
G23
GND
H23
PCIPErr
24
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
J01
GPIO27[UART0_DTR]
K01
GPIO25[UART0_DSR]
L01
EMC0Tx0D2
M01
GND
J02
GPIO28[UART1_Rx]
K02
PerData07
L02
PerData05
M02
PerData03
J03
GPIO29[UART1_Tx]
K03
PerData08
L03
PerData06
M03
PerData04
J04
PerData10
K04
OVDD
L04
GPIO26[UART0_RI]
M04
GPIO24[UART0_DCD]
J05
GND
K05
VDD
L05
VDD
M05
GND
J06
No ball
K06
No ball
L06
No ball
M06
No ball
J07
No ball
K07
No ball
L07
No ball
M07
No ball
J08
No ball
K08
No ball
L08
No ball
M08
No ball
J09
No ball
K09
No ball
L09
No ball
M09
No ball
J10
No ball
K10
GND
L10
GND
M10
GND
J11
No ball
K11
GND
L11
GND
M11
GND
J12
No ball
K12
GND
L12
GND
M12
GND
J13
No ball
K13
GND
L13
GND
M13
GND
J14
No ball
K14
GND
L14
GND
M14
GND
J15
No ball
K15
No ball
L15
No ball
M15
No ball
J16
No ball
K16
No ball
L16
No ball
M16
No ball
J17
No ball
K17
No ball
L17
No ball
M17
No ball
J18
No ball
K18
No ball
L18
No ball
M18
No ball
J19
GND
K19
VDD
L19
VDD
M19
GND
J20
PCISErr
K20
OVDD
L20
PCIC2/BE2
M20
GND
J21
PCIParity
K21
PCIAD18
L21
PCIAD20
M21
PCIAD23
J22
PCIAD16
K22
PCIAD19
L22
PCIAD21
M22
OVDD
J23
PCIAD17
K23
OVDD
L23
PCIAD22
M23
GND
AMCC
25
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
N01
OVDD
P01
PerData02
R01
PHY0Rx1D0
T01
UART0_Rx
N02
UART0_RTS
P02
PerData00
R02
MemData31
T02
MemData28
N03
EMC0Tx0D1
P03
EMC0Tx0D3
R03
MemData30
T03
UART0_CTS
N04
PerData01
P04
UART0_Tx
R04
MemData29
T04
MemData27
N05
VDD
P05
VDD
R05
GND
T05
OVDD
N06
No ball
P06
No ball
R06
No ball
T06
No ball
N07
No ball
P07
No ball
R07
No ball
T07
No ball
N08
No ball
P08
No ball
R08
No ball
T08
No ball
N09
No ball
P09
No ball
R09
No ball
T09
No ball
N10
GND
P10
GND
R10
No ball
T10
No ball
N11
GND
P11
GND
R11
No ball
T11
No ball
N12
GND
P12
GND
R12
No ball
T12
No ball
N13
GND
P13
GND
R13
No ball
T13
No ball
N14
GND
P14
GND
R14
No ball
T14
No ball
N15
No ball
P15
No ball
R15
No ball
T15
No ball
N16
No ball
P16
No ball
R16
No ball
T16
No ball
N17
No ball
P17
No ball
R17
No ball
T17
No ball
N18
No ball
P18
No ball
R18
No ball
T18
No ball
N19
VDD
P19
VDD
R19
GND
T19
OVDD
N20
PCIC3/BE3
P20
OVDD
R20
GPIO22[IRQ5]
T20
OVDD
N21
PCIAD26
P21
PCIAD28
R21
PCIAD31
T21
GPIO09[TrcClk]
N22
PCIAD25
P22
PCIAD27
R22
PCIAD30
T22
GPIO21[IRQ4]
N23
PCIAD24
P23
OVDD
R23
PCIAD29
T23
GPIO23[IRQ6]
26
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 5 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
U01
GND
V01
OVDD
W01
EMC0Tx0En
Y01
IICSDA
U02
DQM3
V02
MemData26
W02
MemData24
Y02
TCK
U03
EMC0Tx0D0
V03
EMC0Tx0Err
W03
MemData22
Y03
MemData21
U04
MemData25
V04
MemData23
W04
DQM2
Y04
GND
U05
OVDD
V05
OVDD
W05
GND
Y05
MemData18
U06
No ball
V06
No ball
W06
OVDD
Y06
EMC0MDClk
U07
No ball
V07
No ball
W07
OVDD
Y07
MemData13
U08
No ball
V08
No ball
W08
OVDD
Y08
PHY0Tx0Clk
U09
No ball
V09
No ball
W09
GND
Y09
MemData09
U10
No ball
V10
No ball
W10
VDD
Y10
PHY0Rx0DV
U11
No ball
V11
No ball
W11
VDD
Y11
MemData04
U12
No ball
V12
No ball
W12
GND
Y12
OVDD
U13
No ball
V13
No ball
W13
VDD
Y13
MemClkOut1
U14
No ball
V14
No ball
W14
VDD
Y14
CAS
U15
No ball
V15
No ball
W15
GND
Y15
BA0
U16
No ball
V16
No ball
W16
OVDD
Y16
PHY0Rx0D0
U17
No ball
V17
No ball
W17
OVDD
Y17
SysErr
U18
No ball
V18
No ball
W18
OVDD
Y18
MemAddr08
U19
OVDD
V19
OVDD
W19
GND
Y19
MemAddr10
U20
GPIO05[TS3]
V20
TestEn
W20
GPIO30[RejectPkt0]
Y20
GND
U21
GPIO07[TS5]
V21
GPIO19[IRQ2]
W21
GPIO04[TS2O]
Y21
GPIO31[RejectPkt1]
U22
GPIO08[TS6]
V22
GPIO20[IRQ3]
W22
GPIO17[IRQ0]
Y22
GPIO02[TS2E]
U23
GND
V23
GPIO06[TS4]
W23
GPIO18[IRQ1]
Y23
GPIO03[TS1O]
AMCC
27
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
AA01
TDI
AB01
GND
AC01
GND
AA02
TDO
AB02
GND
AC02
GND
AA03
GND
AB03
MemData20
AC03
TMS
AA04
MemData19
AB04
IICSCL
AC04
MemData17
AA05
EMC0MDIO
AB05
MemData16
AC05
MemData15
AA06
MemData14
AB06
MemData12
AC06
OVDD
AA07
DQM1
AB07
MemData11
AC07
GND
AA08
MemData10
AB08
PHY0Col0
AC08
MemData08
AA09
PHY0CrS0
AB09
MemData07
AC09
MemData06
AA10
MemData05
AB10
PHY0Rx0Clk
AC10
DQM0
AA11
MemData03
AB11
PHY0Rx0Err
AC11
MemData02
AA12
MemData01
AB12
MemData00
AC12
GND
AA13
PHY0Rx0D3
AB13
BankSel0
AC13
BankSel1
AA14
MemClkOut0
AB14
ClkEn0
AC14
ClkEn1
AA15
RAS
AB15
MemAddr00
AC15
WE
AA16
PHY0Rx0D2
AB16
MemAddr01
AC16
BA1
AA17
MemAddr03
AB17
MemAddr02
AC17
GND
AA18
MemAddr05
AB18
SysClk
AC18
MemAddr04
AA19
MemAddr09
AB19
MemAddr07
AC19
MemAddr06
AA20
MemAddr11
AB20
SysReset
AC20
AVDD
AA21
GND
AB21
AGND
AC21
MemAddr12
AA22
PHY0Rx0D1
AB22
GND
AC22
GND
AA23
GPIO01[TS1E]
AB23
GND
AC23
GND
28
Ball
Signal Name
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Signal List
The following table provides a summary of the number of package pins associated with each functional interface
group.
Table 5. Pin Summary
Group
No. of Pins
Non multiplexed
215
Multiplexed
33
Total Signal Pins
248
OVDD
43
VDD
16
Gnd
53
Thermal (and Gnd)
25
Reserved
0
Total Pins
385
In the table “Signal Functional Description” on page 31, each external signal is listed along with a short description
of the signal function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals
Listed Alphabetically” on page 13 for the pin (ball) number to which each signal is assigned.
Multiplexed Pins
Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In
most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed
on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name
in “Signals Listed Alphabetically” on page 13. It is expected that in any single application a particular pin will always
be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin
selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, in the PCI interface PCIC3:0/BE3:0
serves as both Command and Byte Enable signals. In this example, the pins are also bidirectional, serving as both
inputs and outputs.
Initialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Initialization” on page 48). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an
appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os)
and pull-down value of 1kΩ to GND, applies only to individually terminated signals. To prevent possible damage to
the device, I/Os capable of becoming outputs must never be tied together and terminated through a common
resistor.
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that
the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the
PPC405EP.
AMCC
29
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pullup and pull-down terminations as specified in the “Signal Functional Description” on page 31, good design practice
is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM,
and PCI buses should be configured and terminated as follows:
•
•
•
Peripheral interface—PerAddr03:31, PerData00:15, and all of the control signals are driven by default. Pull
up PerReady.
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405EP
to actively drive all of the SDRAM address, data, and control signals.
PCI—The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI
interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and
actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following:
- Strap the PPC405EP to disable the internal PCI arbiter.
- Individually pull up PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V.
- Pull up PCIReq1:2 through a 3.3kΩ resistor to +3.3V.
- Pull down PCIReq0/Gnt through a 1kΩ resistor to GND.
External Bus Control Signals
All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the highimpedance state when ExtReset = 0. In addition, as detailed in the PowerPC 405EP Embedded Processor User’s
Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals
between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven
state may affect any devices receiving that particular signal.
The following table lists all of the I/O signals provided by the PPC405EP. Please refer to “Signals Listed
Alphabetically” on page 13 for the pin number to which each signal is assigned.
30
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 1 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
PCI Address/Data Bus. Multiplexed address and data bus.
Note: The target device number is driven on PCIAD11:31 for PCI
Type 0 configuration transactions.
Connect the target IDSEL associated with device:
1 to PCIAD16
2 to PCIAD17
...
21 to PCIAD31.
I/O
5V tolerant
3.3V PCI
PCI bus command and byte enables.
I/O
5V tolerant
3.3V PCI
I
5V tolerant
3.3V PCI
Notes
PCI Interface
PCIAD00:31
PCIC3:0/BE3:0
PCIClk
PCIFrame
PCIFrame is driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
I/O
5V tolerant
3.3V PCI
PCIParity
PCI parity. Parity is even across PCIAD00:31 and PCIC3:0/BE3:0.
PCIParity is valid one cycle after either an address or data phase.
The PCI device that drove PCIAD00:31 is responsible for driving
PCIParity on the next PCI bus clock.
I/O
5V tolerant
3.3V PCI
PCIIRDY
PCIIRDY is driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer data.
I/O
5V tolerant
3.3V PCI
2
PCITRDY
The target of the current PCI transaction drives PCITRDY. Assertion
of PCITRDY indicates that the PCI target is ready to transfer data.
I/O
5V tolerant
3.3V PCI
2
PCIStop
The target of the current PCI transaction can assert PCIStop to
indicate to the requesting PCI master that it wants to end the current
transaction.
I/O
5V tolerant
3.3V PCI
2
PCIDevSel
PCIDevSel is driven by the target of the current PCI transaction. A
PCI target asserts PCIDevSel when it has decoded an address and
command encoding and claims the transaction.
I/O
5V tolerant
3.3V PCI
2
PCIIDSel
PCIIDSel is used during configuration cycles to select the PCI slave
interface for configuration.
I
5V tolerant
3.3V PCI
PCIINT
PCI interrupt. Open-drain output (two states; 0 or open circuit)
or
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
O
5V tolerant
3.3V PCI
PCISErr
PCISErr is used for reporting address parity errors or catastrophic
failures detected by a PCI target.
I/O
5V tolerant
3.3V PCI
2
PCIPErr
PCIPErr is used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD00:31,
PCIC3:0/BE3:0, and PCIParity, two PCI clocks following the data in
which bad parity is detected.
I/O
5V tolerant
3.3V PCI
2
PCI specific reset.
O
5V tolerant
3.3V PCI
Multipurpose signal, used as PCIReq0 when internal arbiter is used,
and as Gnt when external arbiter is used.
I
5V tolerant
3.3V PCI
PCIReset
PCIReq0/Gnt
AMCC
PCIClk is used as the asynchronous PCI clock when in asynch mode.
2
31
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Notes
I/O
Type
PCIReq input when internal arbiter is used.
I
5V tolerant
3.3V PCI
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
O
5V tolerant
3.3V PCI
PCIGnt output when internal arbiter is used.
O
5V tolerant
3.3V PCI
PHY0Rx0:1D3:0
Received data. This is a nibble wide bus from the PHY. The data is
synchronous with the PHY0RxClk.
I
5V tolerant
3.3V LVTTL
EMC0Tx0:1D3:0
Transmit data. A nibble wide data bus towards the net. The data is
synchronous to the PHY0TxClk.
O
5V tolerant
3.3V LVTTL
PHY0Rx0:1Err
Receive Error. This signal comes from the PHY and is synchronous to
the PHY0RxClk.
I
5V tolerant
3.3V LVTTL
1
PHY0Rx0:1Clk
Receive Medium clock. This signal is generated by the PHY. If an
EMAC interface is not used, this clock must be present in order to
reset the EMAC.
I
5V tolerant
3.3V LVTTL
1
PHY0Rx0:1DV
Receive Data Valid. Data on the Data Bus is valid when this signal is
activated. Deassertion of this signal indicates end of the frame
reception.
I
5V tolerant
3.3V LVTTL
1
PHY0CrS0:1
Carrier Sense signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMC0Tx0:1Err
Transmit Error. This signal is generated by the Ethernet controller, is
connected to the PHY and is synchronous with the PHYTxClk. It
informs the PHY that an error was detected.
O
5V tolerant
3.3V LVTTL
EMC0Tx0:1En
Transmit Enable. This signal is driven by the EMAC to the PHY. Data
is valid during the active state of this signal. Deassertion of this signal
indicates end of frame transmission. This signal is synchronous to the
PHY0TxClk.
O
5V tolerant
3.3V LVTTL
PHY0Tx0:1Clk
This clock comes from the PHY and is the Medium Transmit clock. If
an EMAC interface is not used, this clock must be present in order to
reset the EMAC.
I
5V tolerant
3.3V LVTTL
1
PHY0Col0:1
Collision signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMC0MDClk
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with respect to
this clock.
O
5V tolerant
3.3V LVTTL
EMC0MDIO
Management Data Input/Output is a bidirectional signal between the
Ethernet controller and the PHY. It is used to transfer control and
status information.
I/O
5V tolerant
3.3V LVTTL
PCIReq1:2
PCIGnt0/Req
PCIGnt1:2
Description
Ethernet Interface
32
1
1
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
MemData00:31
Memory data bus.
Notes:
1. MemData00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:00
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
O
3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks.
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM for byte lane: 0 (MemData00:7),
1 (MemData08:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
Select up to two external SDRAM banks.
O
3.3V LVTTL
Write Enable.
O
3.3V LVTTL
SDRAM Clock Enable.
O
3.3V LVTTL
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL
or zero-delay buffer.
O
3.3V LVTTL
Notes
SDRAM Interface
DQM0:3
BankSel0:1
WE
ClkEn0:1
MemClkOut0:1
External Slave Peripheral Interface
PerData00:15
Peripheral data bus.
Note: PerData00 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr03:05
PerAddr06:31
Peripheral address bus.
Note: PerAddr03 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:1
These pins act as byte-enables which are valid for an entire cycle or
as write-byte-enables which are valid for each byte on each data
transfer, allowing partial word transactions.
O
5V tolerant
3.3V LVTTL
7
[PerWE]
Peripheral write enable. Low when either of the two PerWBE0:1 write
byte enables are low.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
PerCS0
Peripheral chip select bank 0.
O
5V tolerant
3.3V LVTTL
7
Four additional peripheral chip selects
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
1, 7
PerOE
Peripheral output enable.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Peripheral read/write. High indicates a read from memory, low
indicates a write to memory.
O
5V tolerant
3.3V LVTTL
[PerCS1:4]
AMCC
33
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
I
5V tolerant
3.3V LVTTL
1
1, 7
PerReady
Ready to transfer data.
[PerBLast]
Used to indicates the last transfer of a memory access.
To access this function, software must toggle a DCR bit.
I/O
5V tolerant
3.3V LVTTL
PerClk
Peripheral clock to be used by peripheral slaves.
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by peripheral slaves.
O
5V tolerant
3.3V LVTTL
Internal Peripheral Interface
UART0_Rx
UART0 Serial Data In.
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Serial Data Out.
O
5V tolerant
3.3V LVTTL
6
[UART0_DCD]
UART0 Data Carrier Detect.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART0_DSR]
UART0 Data Set Ready.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
UART0 Data Terminal Ready.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
6
[UART0_RI]
UART0 Ring Indicator.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART1_Rx]
UART1 Serial Data In.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART1_Tx]
UART1 Serial Data Out.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
IICSCL
IIC Serial Clock.
I/O
3.3V IIC
1, 2
IICSDA
IIC Serial Data.
I/O
3.3V IIC
1, 2
Interrupt requests
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
TDI
Test data in.
I
5V tolerant
3.3V LVTTL
1, 4
TMS
JTAG test mode select.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_CTS
[UART0_DTR]
Interrupts Interface
[IRQ0:6]
JTAG Interface
34
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
TDO
Test data out.
O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller.
I
5V tolerant
3.3V LVTTL
5
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
1, 2
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
6
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
1, 2
I/O
5V tolerant
3.3V LVTTL
1
System Interface
SysReset
SysErr
Halt
GPIO00:31
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
TestEn
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
I
1.8V CMOS
w/pull-down
SysClk
Main system clock input.
I
3.3V LVTTL
External request to reject a packet.
I
5V tolerant
3.3V LVTTL
AVDD
Clean voltage input for the PLL.
I
AGND
Clean Ground input for the PLL.
I
[TS1E]
[TS2E]
Even Trace execution status. To access this function, software must
toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software must
toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TS3:6]
Trace status. To access this function, software must toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TrcClk]
Trace interface clock. Operates at half the CPU core frequency. To
access this function, software must toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
GND
Ground
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also
thermal balls.
na
na
na
OVDD
Output driver voltage—3.3V.
na
na
na
[RejectPkt0:1]
Trace Interface
Power
AMCC
35
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
I/O
Type
Notes
Logic voltage—1.8V.
na
na
na
Reserved pins. Do not make voltage, ground, or signal connections to
these pins.
na
na
na
Signal Name
VDD
Description
Other pins
Reserved
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Symbol
Value
Unit
Supply Voltage (Internal Logic)
VDD
0 to +1.95
V
Supply Voltage (I/O Interface)
OVDD
0 to +3.6
V
PLL Supply Voltage
AVDD
0 to +1.95
V
Input Voltage (1.8V CMOS receivers)
VIN
0 to +1.95
V
Input Voltage (3.3V LVTTL receivers)
VIN
0 to +3.6
V
Input Voltage (5.0V LVTTL receivers)
VIN
0 to +5.5
V
Storage Temperature Range
TSTG
-55 to +150
°C
Case temperature under bias
TC
-40 to +120
°C
Note: All specified voltages are with respect to GND.
Table 8. Package Thermal Specifications
The PPC405EP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the EPBGA packages in a convection environment are as follows:
Package—Thermal Resistance
Airflow
ft/min (m/sec)
Symbol
Unit
0 (0)
100 (0.51)
200 (1.02)
31mm, 385-balls—Junction-to-Case
θJC
2
2
2
°C/W
31mm, 385-balls—Case-to-Ambient1
θCA
17.8
16.8
16.1
°C/W
Note:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
b. TA = TC – P×θ CA, where TA is ambient temperature and P is power consumption.
36
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Notes:
1. PCI drivers meet PCI specifications.
2. See “5V-Tolerant Input Current” on page 38.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Logic Supply Voltage (133, 200, 266MHz)
VDD
+1.65
+1.8
+1.95
V
Logic Supply Voltage (333MHz)
VDD
+1.7
+1.8
+1.9
V
I/O Supply Voltage
OVDD
+3.0
+3.3
+3.6
V
PLL Supply Voltage (133, 200, 266MHz)
AVDD
+1.65
+1.8
+1.95
V
PLL Supply Voltage (333MHz)
AVDD
+1.7
+1.8
+1.9
V
Input Logic High
(1.8V CMOS receivers)
VIH
0.65VDD
VDD
V
Input Logic High
(3.3V PCI receivers)
VIH
0.5OVDD
OVDD+0.5
V
Input Logic High
(3.3V LVTTL, 5V tolerant receivers)
VIH
+2.0
+5.5
V
Input Logic Low
(1.8V CMOS receivers)
VIL
0
0.65VDD
V
Input Logic Low
(3.3V PCI receivers)
VIL
-0.5
0.35OVDD
V
Input Logic Low
(3.3V LVTTL, 5V tolerant receivers)
VIL
0
+0.8
V
Output Logic High
(3.3V PCI receivers)
VOH
0.9OVDD
OVDD
V
Output Logic High
(3.3V LVTTL, 5V tolerant receivers)
VOH
+2.4
OVDD
V
Output Logic Low
(3.3V PCI receivers)
VOL
-0.5
0.35OVDD
V
Output Logic Low
(3.3V LVTTL, 5V tolerant receivers)
VOL
0
+0.4
V
Input Leakage Current
(no pull-up or pull-down)
IIL1
0
0
μA
Input Leakage Current
(with internal pull-down)
IIL2
0
200
μA
5V Tolerant I/O Input Current
IIL4
±10
-325
μA
VIMAO1.8
VDD + 0.6
V
Input Max Allowable Overshoot
(3.3V LVTTL, 5V tolerant receivers)
VIMAO
+5.5
V
Input Max Allowable Undershoot
(3.3V LVTTL, 5V tolerant receivers)
VIMAU
Output Max Allowable Overshoot
(3.3V LVTTL, 5V tolerant receivers)
VOMAO
Output Max Allowable Undershoot
(3.3V LVTTL, 5V tolerant receivers)
VOMAU
Input Max Allowable Overshoot
(1.8V CMOS receivers)
AMCC
-0.6
2
V
+5.5
-0.6
Notes
V
V
37
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 9. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Notes:
1. PCI drivers meet PCI specifications.
2. See “5V-Tolerant Input Current” on page 38.
Parameter
Case Temperature
Symbol
Minimum
TC
-40
1.0
2.0
Typical
Maximum
Unit
+85
°C
Notes
Figure 3. 5V-Tolerant Input Current
50
0
-50
-100
Input Current (μA)
-150
-200
-250
-300
-350
0.0
3.0
4.0
5.0
Input Voltage (V)
Table 10. Input Capacitance
Parameter
Symbol
Maximum
Unit
3.3V LVTTL I/O
CIN1
12
pF
5V tolerant, 3.3V LVTTL I/O
CIN2
12
pF
PCI I/O
CIN3
12
pF
Rx only pins
CIN4
9
pF
IIC pads
CIN5
6.7
pF
38
Notes
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 11. DC Electrical Characteristics
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Active Operating Current (VDD)–266MHz
IDD
300
610
mA
Active Operating Current (VDD)–333MHz
IDD
325
690
mA
Active Operating Current (OVDD)
IODD
45
200
mA
PLL VDD Input current
IPLL
16
23
mA
Active Operating Power–266 MHz
PDD
0.72
1.92
W
Active Operating Power–333MHz
PDD
0.76
2.07
W
Note:
1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are
dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external
interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different
results. VDD (logic) current and power are primarily dependent on the applications running and the use of internal chip functions
(DMA, PCI, Ethernet, and so on). OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and
utilization of the external buses. The following information provides details about the conditions under which the values in the table
above could be obtained:
a. In general, there would be four PCI devices, an external bus master on the peripheral bus, and external wrap-back on the
Ethernet port. For IODD measurements, PLB = 133.3MHz, OPB = PerClk = 66.6MHz, and PCI = SysClk = 33.3MHz.
b. Typical current and power are characterized at VDD = +1.8V, OVDD = +3.3V, and TC = +36 °C while running various
applications under the Linux operating system.
c. Maximum current and power are characterized at VDD = +1.9V, OVDD = +3.6V, and TC = +85 °C while running applications
designed to maximize CPU power consumption. An external PCI master heavily loads the PCI bus with transfers targeting
SDRAM while the internal DMA controller further increases SDRAM bus traffic.
2. AVDD should be derived from VDD using the following circuit:
AVDD
VDD
L1
+
C1
C2
C1 – 3.3 μF SMT tantalum
C3
AGND
GND
AMCC
L1 – 2.2 μH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C2 – 0.1 μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01 μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
39
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Test Conditions
Clock timing and switching characteristics are specified in accordance with
operating conditions shown in the table “Recommended DC Operating
Conditions.” For all signals other than PCI signals, AC specifications are
characterized at OVDD = 3V and TC = 85°C with the 50pF test load shown
in the figure at right.
For PCI signals there are two different test load circuits, one for the rising
edge and one the falling edge as shown in the figures at right.
Output
Pin
50pF
All signals other
than PCI
Output
Pin
PCI Rising edge
Output
Pin
10pF
25Ω
25Ω
OVDD
PCI Falling edge
10pF
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AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 12. Clocking Specifications
Symbol
Parameter
Min
Max
Units
133.33, 200, 266.66, or
333.33
MHz
CPU
PFC
Processor clock frequency
PTC
Processor clock period
7.5, 5, 3.75 or 3
ns
SysClk Input
SCFC
Frequency
25
100
MHz
SCTC
Period
10
40
ns
SCTCS
Edge stability (phase jitter, cycle to cycle)
–
±0.15
ns
SCTCH
Input high time
40% of nominal period
60% of nominal period
ns
SCTCL
Input low time
40% of nominal period
60% of nominal period
ns
PLBFC
MHz
Note: Input slew rate > 2V/ns
MemClkOut Output
MCOFC
Frequency
MCOTC
Period
MCOTCS
Edge stability (phase jitter, cycle to cycle)
MCOTCH
MCOTCL
1/PLBFC
ns
–
±0.2
ns
Output high time
45% of nominal period
55% of nominal period
ns
Output low time
45% of nominal period
55% of nominal period
ns
TrcClk Output
TCFC
Clock output frequency
PFC/2
MHz
TCTC
Clock period
PTCx2
ns
TCTCS
Clock edge stability (phase jitter, cycle to cycle)
± 0.2
ns
TCTCH
Clock output high time
45% of nominal period
55% of nominal period
ns
TCTCL
Clock output low time
45% of nominal period
55% of nominal period
ns
500
1000
MHz
Other Clocks
VCOFC
VCO frequency @ PFC = 133, 200, or 266MHz
VCOFC
VCO frequency @ PFC = 333MHz
500
1333
MHz
PLBFC
PLB frequency @ PFC = 266.66MHz
66.66
133.33
MHz
PLBFC
PLB frequency @ PFC = 333.33MHz
55.55
111.11
MHz
PLBFC
PLB frequency @ PFC = 200MHz
50
100
MHz
OPBFC
OPB frequency @ PFC = 133.33MHz
8.33
66.66
MHz
OPBFC
OPB frequency @ PFC = 266.66MHz
16.66
66.66
MHz
OPBFC
OPB frequency @ PFC = 333.33MHz
13.87
55.55
MHz
OPBFC
OPB frequency @ PFC = 200MHz
12.5
50
MHz
Figure 4. Clocking Waveform
2.0V
1.5V
0.8V
TCH
TCL
TC
AMCC
41
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405EP. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC405EP the following conditions must be met:
•
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405EP with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC405EP peripherals impose more stringent requirements (see Note 1).
Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock
tracks the modulation.
Use the SDRAM MemClkOut since it also tracks the modulation.
•
•
•
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the
connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation.
2. Operation of the PPC405EP PCI Bridge is unaffected by the use of an SSCG.
The PCI controller must be operated in asynchronous mode. When in asynchronous mode, the PCI bus clock
must be driven into the PPC405EP PCIClk input. In this configuration the PCI controller supports the
66.66 MHz PCI clock specification which specifies a maximum frequency deviation of -1% at a modulation of
between 30 kHz and 33 kHz.
3. Ethernet operation is unaffected.
4. IIC operation is unaffected.
Caution: It is up to the system designer to ensure that any SSCG used with the PPC405EP meets the above
requirements and does not adversely affect other aspects of the system.
42
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 13. Peripheral Interface Clock Timings
Parameter
Min
Max
Units
Note 1
66.66
MHz
15
Note 1
ns
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
–
2.5
MHz
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
EMC0MDClk output frequency
EMC0MDClk period
400
–
ns
EMC0MDClk output high time
160
–
ns
EMC0MDClk output low time
160
–
ns
PHY0Tx0:1Clk input frequency
2.5
25
MHz
PHY0Tx0:1Clk period
40
400
ns
PHY0Tx0:1Clk input high time
35% of nominal period
–
ns
PHY0Tx0:1Clk input low time
35% of nominal period
–
ns
2.5
25
MHz
PHY0Rx0:1Clk input frequency
PHY0Rx0:1Clk period
40
400
ns
PHY0Rx0:1Clk input high time
35% of nominal period
–
ns
PHY0Rx0:1Clk input low time
35% of nominal period
–
ns
–
66.66
MHz
PerClk output frequency
PerClk period
15
–
ns
PerClk output high time
45% of nominal period
55% of nominal period
ns
PerClk output low time
45% of nominal period
55% of nominal period
ns
± 0.3
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
Note:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405EP Embedded Processor
User’s Manual for more information.
AMCC
43
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Figure 5. Input Setup and Hold Timing Waveform
System Clock
1.5V
TIS
TIH
MIN
MIN
Inputs
1.5V
Valid
Figure 6. Output Delay and Float Timing Waveform
System Clock 1.5V
TOH
MIN
TOV
MAX
Outputs
1.5V
Valid
TOF
Outputs
44
MAX
MIN
1.5V
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 14. I/O Specifications—Group 1 (Sheet 1 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, IOH is specified at 0.9OVDD and IOL is specified at 0.1OVDD. For all other interfaces, IOH is specified at 2.4V and IOL
is specified at 0.4V.
Input (ns)
Signal
Setup Time
(TIS min)
Output (ns)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Output Current (mA)
Hold Time
(TOH min)
IOH
(min)
IOL
(min)
Clock
Notes
PCI Interface
PCIAD31:00
3
0
6
1
0.5
1.5
PCIClk
1
PCIC3:0/BE3:0
3
0
6
1
0.5
1.5
PCIClk
1
PCIClk
na
na
na
na
na
na
async
PCIDevSel
3
0
6
1
0.5
1.5
PCIClk
1
PCIFrame
3
0
6
1
0.5
1.5
PCIClk
1
PCIGnt0/Req
PCIGnt1:2
na
na
6
1
0.5
1.5
PCIClk
1
PCIIDSel
3
0
na
na
na
na
PCIClk
1
PCIINT[PerWE]
na
na
na
na
0.5
1.5
PCIClk
1
PCIIRDY
3
0
6
1
0.5
1.5
PCIClk
1
PCIParity
3
0
6
1
0.5
1.5
PCIClk
1
PCIPErr
3
0
6
1
0.5
1.5
PCIClk
1
PCIReq0/Gnt
PCIReq1:2
5
0
na
na
na
na
PCIClk
1
PCIReset
na
na
na
na
0.5
1.5
PCIClk
1
PCISErr
na
na
na
na
0.5
1.5
PCIClk
1
PCIStop
3
0
6
1
0.5
1.5
PCIClk
1
PCITRDY
3
0
6
1
0.5
1.5
PCIClk
1
na
na
settable
2
10.3
7.1
async
2
0
1 OPB clock
period + 10ns
1 OPB clock
period
10.3
7.1
EMC0MDClk
2
2
Ethernet Interface
EMC0MDClk
EMC0MDIO
100
EMC0Tx0:1D3:0
na
na
14
5
10.3
7.1
PHY0TxClk
EMC0Tx0:1En
na
na
14
5
10.3
7.1
PHY0TxClk
2
EMC0Tx0:1Err
na
na
14
5
10.3
7.1
PHY0TxClk
2
PHY0Col0:1
2
3
na
na
na
na
PHY0RxClk
2
PHY0CrS0:1
2
3
na
na
na
na
PHY0RxClk
2
PHY0Rx0:1Clk
na
na
na
na
na
na
async
2
PHY0Rx0:1D3:0
2
4
na
na
na
na
PHY0RxClk
2
PHY0Rx0:1DV
2
4
na
na
na
na
PHY0RxClk
2
PHY0Rx0:1Err
2
4
na
na
na
na
PHY0RxClk
2
PHY0Tx0:1Clk
na
na
na
na
na
na
async
2
AMCC
45
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 14. I/O Specifications—Group 1 (Sheet 2 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, IOH is specified at 0.9OVDD and IOL is specified at 0.1OVDD. For all other interfaces, IOH is specified at 2.4V and IOL
is specified at 0.4V.
Input (ns)
Signal
Setup Time
(TIS min)
Output (ns)
Output Current (mA)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOH
(min)
IOL
(min)
Clock
Notes
Internal Peripheral Interface
IICSCL
na
na
na
na
15.3
10.2
IICSDA
na
na
na
na
15.3
10.2
UART0_CTS
na
na
na
na
na
na
UART0_RTS
na
na
na
na
10.3
7.1
UART0_Rx
na
na
na
na
na
na
UART0_Tx
na
na
na
na
10.3
7.1
UART1_Rx
na
na
na
na
na
na
UART1_Tx
na
na
na
na
10.3
7.1
10.3
7.1
Interrupts Interface
[IRQ0:6]
JTAG Interface
TCK
na
na
na
na
na
na
TDI
na
na
na
na
na
na
async
async
TDO
na
na
na
na
10.3
7.1
async
TMS
na
na
na
na
na
na
async
TRST
na
na
na
na
na
na
async
GPIO00:31
na
na
na
na
10.3
7.1
Halt
na
na
na
na
na
na
async
SysErr
na
na
na
na
10.3
7.1
async
System Interface
SysReset
na
na
na
na
10.3
7.1
async
TestEn
na
na
na
na
na
na
async
async
[RejectPkt0:1]
3
1
na
na
na
na
SysClk
na
na
na
na
na
na
46
AMCC
Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 15. I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. IOH is specified at 2.4V and IOL is specified at 0.4V.
Input (ns)
Signal
Output (ns)
Output Current (mA)
Hold Time
(TOH min)
IOH
(minimum)
IOL
(minimum)
Clock
Notes
4.7
2
15.3
10.2
MemClkOut
1, 2
4.5
1.7
15.3
10.2
MemClkOut
1, 2
na
4.8
2
15.3
10.2
MemClkOut
1, 2
na
na
4.1
1.6
28.7
19.3
MemClkOut
1, 2
DQM0:3
na
na
4.7
1.9
15.3
10.2
MemClkOut
1, 2
MemAddr12:00
na
na
4.8
2.1
15.3
10.2
MemClkOut
1, 2
MemData00:31
1.6
1
4
1.2
15.3
10.2
MemClkOut
1, 2
RAS
na
na
5
2.1
15.3
10.2
MemClkOut
1, 2
WE
na
na
4.9
2
15.3
10.2
MemClkOut
1, 2
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
BA1:0
na
na
BankSel3:0
na
na
CAS
na
ClkEn0:1
SDRAM Interface
External Slave Peripheral Interface
PerAddr06:31
na
na
3.8
1.6
15.3
10.2
PerClk
[PerBLast]
4
1
8
0
12
8
PerClk
PerCS0
[PerCS1:4]
na
na
4.1
1.5
10.3
7.1
PerClk
PerData00:31
5
1
6.4
1.5
15.3
10.2
PerClk
PerOE
na
na
4.1
1.5
10.3
7.1
PerClk
PerR/W
na
na
4.1
1.6
10.3
7.1
PerClk
PerReady
6.5
1
na
na
na
na
PerClk
PerWBE0:3
na
na
4.1
1.6
10.3
7.1
PerClk
ExtReset
na
na
na
na
15.3
10.2
PerClk
PerClk
na
na
0.4
-0.2
15.3
10.2
PLB Clk
AMCC
4
47
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs.
Strapping
When the SysReset input is driven low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to PPC405EP start-up. The actual capture instant is the nearest system clock edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to +5V. The
recommended pull-down is 1KΩ to GND. These pins are use for strap functions only during reset. They are used
for other signals during normal operation. The following table lists the strapping pins along with their functions and
strapping options. The signal names assigned to the pins for normal operation appear below the pin number.
Table 16. Strapping Pin Assignments
Function
IIC EEPROM controller
If the controller is enabled, 32 bytes of configuration data
are read from the EEPROM.
Option
Disable
0
Enable
1
EEPROM address (P04 = 1)
or
Boot ROM width (P04 = 0)
When P04 = 1, these pins set the high-order two
bits of the EEPROM base address.
When P04 = 0, these pins indicated the width of
the boot ROM.
Ball Strapping
P04
UART0_Tx
N02
UART0_RTS
Y17
SysErr
High order EEPROM base address bits
Address bit
Address bit
0
8 bits
0
16 bits
0
1
reserved
1
0
reserved
1
1
EEPROM
During reset, configuration values other than the internal default values can be read from a serial EEPROM
connected to the IIC port. The association of bits in the EEPROM with the configuration values and their default
values are covered in detail in the PowerPC 405EP Embedded Processor User’s Manual.
Note: If P04 is strapped to 1, and the EEPROM is not connected or is defective, the PPC405EP remains in the
reset state and will not boot.
48
AMCC
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Document Revision History
Revision
Date
1.01
07/30/04
Initial Release
1.02
01/10/05
Add lead-free part numbers and clean up AMCC conversion.
1.03
05/01/07
Add information on connection of target device IDSEL to the addess bus.
Modify description of TRST signal.
Remove note on TrcClk concerning initilization.
1.04
06/01/07
Update package thickness values (package drawing).
Add Logo View to package drawing.
1.05
07/18/07
Add instructions to PHY clock signals indicating they must be present even if interface is
not used.
1.06
09/06/07
Correct AMCC phone numbers.
1.07
09/10/07
Change TestEn signal from active low to active high.
AMCC
Description
49
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Applied Micro Circuits Corporation
215 Moffett Park Drive, Sunnyvale, CA 94089
Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601
http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available
datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation.
50
AMCC