Datasheet - Spansion

S25FL004K / S25FL008K / S25FL016K
4-Mbit / 8-Mbit / 16-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
S25FL004K / S25FL008K / S25FL016K Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL004K-016K_00
Revision 02
Issue Date July 14, 2011
D a t a
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Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
S25FL004K / S25FL008K / S25FL016K
4-Mbit / 8-Mbit / 16-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
 Single power supply operation
 Speed
– Full voltage range: 2.7 to 3.6V read and write operations
 Memory architecture
– Uniform 4-kB sectors
– 256-byte page size
 Program
– Page Program (up to 256 bytes) in 0.7 ms (typical)
– Program operations are on a page by page basis
– Quad Page Programming
 Erase
–
–
–
–
Bulk erase function
Uniform sector erase (4 kB)
Uniform block erase (32 kB and 64 kB)
Erase/Program Suspend and Resume
 Cycling endurance
– 100,000 erase/program cycles typical
 Data retention
–
–
–
–
–
–
Normal READ (Serial): 50 MHz clock rate
FAST_READ (Serial): 104 MHz clock rate (maximum)
104 MHz Dual SPI/Quad SPI clocks
208/416 MHz equivalent Dual/Quad SPI
50 MB/s continuous data transfer rate (S25FL004K/S25FL008K)
52 MB/s continuous data transfer rate (S25FL016K)
 Low Power Consumption
– 4 mA active current
<1 µA in Deep Power-down mode (typical) (S25FL004K/
S25FL016K)
1 µA in Deep Power-down mode (typical) (S25FL008K)
– Industrial temperature range (–40°C to +85°C)
 Efficient “Continuous Read Mode”
–
–
–
–
Low Instruction overhead
Continuous Read with 8/16/32/64-byte Wrap
As few as 8 clocks to address memory
Allows true XIP (execute in place) operation
– 20-year data retention typical
 Process technology
– Manufactured on 0.09 µm process technology
 Package option
– Industry Standard Pinouts
– 8-pin SO package (208 mils)
– 8-pin SO package (150 mils)
Publication Number S25FL004K-016K_00
Memory Protection Features
 Advanced security features
–
–
–
–
–
–
–
Software and Hardware Write-Protect
Top/Bottom, 4-kB complement array protection
Power Supply Lock-Down and OTP protection
64-bit Unique ID for each device
Discoverable Parameters (SFDP) Registers
3x 256-byte Security Registers with OTP locks
Volatile and Non-volatile Status Register Bits
Revision 02
Issue Date July 14, 2011
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
D a t a
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General Description
The S25FL004K (4-Mbit), S25FL008K (8-Mbit), and S25FL016K (16-Mbit) Serial Flash memories provide an
ideal storage solution for systems with limited space, pins and power. The devices offer flexibility and
performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM,
executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a
single 2.7V to 3.6V power supply with current consumption as low as 4 mA active and 1 µA for deep powerdown. All devices are offered in space-saving packages.
The S25FL004K, S25FL008K, and S25FL016K support the standard Serial Peripheral Interface (SPI), and a
high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock (CLK), Chip Select (CS#),
Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). SPI clock frequencies of up to 104 MHz are
supported allowing equivalent clock rates of 208 MHz (104 MHz x 2) for Dual I/O and 416 MHz (104 MHz x 4)
for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform
standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device
identification with a 64-bit Unique Serial Number.
S25FL004K
The S25FL004K array is organized into 2,048 programmable pages of 256 bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4-kB sector erase), groups of 128 (32-kB
block erase), groups of 256 (64-kB block erase) or the entire chip (chip erase). The S25FL004K has 128
erasable sectors and 8 erasable blocks respectively. The small 4-kB sectors allow for greater flexibility in
applications that require data and parameter storage.
S25FL008K
The S25FL008K array is organized into 4,096 programmable pages of 256 bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4-kB sector erase), groups of 128 (32-kB
block erase), groups of 256 (64-kB block erase) or the entire chip (chip erase). The S25FL008K has 256
erasable sectors and 16 erasable blocks respectively. The small 4-kB sectors allow for greater flexibility in
applications that require data and parameter storage.
S25FL016K
The S25FL016K array is organized into 8,192 programmable pages of 256 bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4-kB sector erase), groups of 128 (32-kB
block erase), groups of 256 (64-kB block erase) or the entire chip (chip erase). The S25FL016K has 512
erasable sectors and 32 erasable blocks respectively. The small 4-kB sectors allow for greater flexibility in
applications that require data and parameter storage.
4
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
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Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
S25FL004K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2
S25FL008K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3
S25FL016K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
SPI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
Write Enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2
Write Enable for Volatile Status Register (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
Write Disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4
Read Status Register-1 (05h) and Read Status Register-2 (35h) . . . . . . . . . . . . . . . . . . . . .
7.5
Write Status Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6
Read Data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7
Fast Read (0Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8
Fast Read Dual Output (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9
Fast Read Quad Output (6Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Fast Read Dual I/O (BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Fast Read Quad I/O (EBh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Word Read Quad I/O (E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Octal Word Read Quad I/O (E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 Set Burst with Wrap (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 Continuous Read Mode Bits (M7-0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 Continuous Read Mode Reset (FFh or FFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17 Page Program (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18 Quad Page Program (32h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19 Sector Erase (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20 32 KB Block Erase (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21 64 KB Block Erase (D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22 Chip Erase (C7h / 60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23 Erase / Program Suspend (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.24 Erase / Program Resume (7Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.25 Deep Power-down (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.26 Release from Deep Power-down / Device ID (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27 Read Manufacturer / Device ID (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.28 Read Manufacturer / Device ID Dual I/O (92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.29 Read Manufacturer / Device ID Quad I/O (94h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.30 Read Unique ID Number (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.31 Read JEDEC ID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.32 Read SFDP Register (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.33 Erase Security Registers (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.34 Program Security Registers (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.35 Read Security Registers (48h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.2
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
23
26
27
27
28
28
29
30
31
32
33
34
36
37
39
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
58
59
60
5
D a t a
8.3
8.4
8.5
8.6
8.7
8.8
8.9
6
S h e e t
Power-Up Timing and Write Inhibit Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
63
63
64
66
66
66
9.
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.1
SOA008 narrow — 8-pin Plastic Small Outline Package (150-mils Body Width) . . . . . . . . . 67
9.2
SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width) . . . . . . . . . . . 68
10.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
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Figures
Figure 2.1
Figure 6.1
Figure 6.2
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
Figure 7.10
Figure 7.11
Figure 7.12
Figure 7.13
Figure 7.14
Figure 7.15
Figure 7.16
Figure 7.17
Figure 7.18
Figure 7.19
Figure 7.20
Figure 7.21
Figure 7.22
Figure 7.23
Figure 7.24
Figure 7.25
Figure 7.26
Figure 7.27
Figure 7.28
Figure 7.29
Figure 7.30
Figure 7.31
Figure 7.32
Figure 7.33
Figure 7.34
Figure 7.35
Figure 7.36
Figure 7.37
Figure 7.38
Figure 7.39
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
8-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Enable Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Enable for Volatile Status Register Instruction Sequence Diagram . . . . . . . . . . . . . . .
Write Disable Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Status Register Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Status Register Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Data Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Read Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Read Dual Output Instruction Sequence Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Read Quad Output Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10) . . . . . .
Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) . . . . . . . . . .
Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) . . . . . .
Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) . . . . . . . . .
Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) . . . . .
Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10). . . . . . . . .
Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10)
Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) . . . .
Set Burst with Wrap Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Read Mode Reset for Fast Read Dual/Quad I/O . . . . . . . . . . . . . . . . . . . . . . . .
Page Program Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad Page Program Instruction Sequence Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sector Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 kB Block Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64 kB Block Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erase/Program Suspend Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erase/Program Resume Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deep Power-down Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release from Deep Power-down Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release from Deep Power-down / Device ID Instruction Sequence Diagram . . . . . . . . . . . .
Read Manufacturer / Device ID Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Manufacturer / Device ID Dual I/O Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Manufacturer / Device ID Quad I/O Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Unique ID Number Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read JEDEC ID Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read SFDP Register Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erase Security Registers Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
12
18
18
26
27
27
28
29
29
30
31
32
33
34
35
35
36
37
38
38
39
40
41
42
43
44
45
46
47
48
49
50
50
51
52
53
54
55
56
58
59
60
62
64
66
66
66
7
D a t a
S h e e t
Tables
Table 3.1
Table 4.1
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 8.1
8
8-pin SOIC 150-mil / 208-mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
S25FL004K, S25FL008K, and S25FL016K Valid Combinations . . . . . . . . . . . . . . . . . . . . . .13
Status Register Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
S25FL004K Status Register Memory Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .19
S25FL008K Status Register Memory Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .20
S25FL016K Status Register Memory Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .21
S25FL004K Status Register Memory Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .22
S25FL008K Status Register Memory Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .22
S25FL016K Status Register Memory Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .23
Manufacturer Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Instruction Set (Erase, Program Instructions (1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Instruction Set (Read Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Instruction Set (ID, Security Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Flash Discoverable Parameter Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
1. Block Diagrams
1.1
S25FL004K Block Diagram
SFDP Register
000000h
Security Register 1 - 3
0000FFh
003000h
002000h
001000h
0030FFh
0020FFh
0010FFh
Block Segmentation
xxFF00h
•
xxF000h
Sector 15 (4 kB)
xxFFFFh
•
xxF0FFh
xxEF00h
•
xxE000h
Sector 14 (4 kB)
xxEFFFh
•
xxE0FFh
xxDF00h
•
xxD000h
Sector 13 (4 kB)
xxDFFFh
•
xxD0FFh
07FF00h
•
070000h
07FFFFh
•
0700FFh
Sector 2 (4 kB)
xx2FFFh
•
xx20FFh
xx1F00h
•
xx1000h
Sector 1 (4 kB)
xx1FFFh
•
xx10FFh
xx0F00h
•
xx0000h
Sector 0 (4 kB)
xx0FFFh
•
xx00FFh
Write Protect Logic and Row Decode
xx2F00h
•
xx2000h
04FF00h
•
040000h
Block 4 (64 kB)
04FFFFh
•
0400FFh
03FF00h
•
030000h
Block 3 (64 kB)
03FFFFh
•
0300FFh
S25FL0040K
•
•
•
•
•
•
WP (IO2)
Block 7 (64 kB)
Write Control
Logic
•
•
•
Status
Register
High Voltage
Generators
HOLD# (IO3)
CLK
CS#
SPI
Command &
Control Logic
Page Address
Latch / Counter
01FF00h
•
010000h
Block 1 (64 kB)
01FFFFh
•
0100FFh
00FF00h
•
000000h
Block 0 (64 kB)
00FFFFh
•
0000FFh
Beginning
Page Address
Ending
Page Address
Column Decode
And 256-byte Page Buffer
Data
SI (IO0)
SO (IO1)
July 14, 2011 S25FL004K-016K_00_02
Byte Address
Latch / Counter
S25FL004K / S25FL008K / S25FL016K
9
D a t a
1.2
S h e e t
S25FL008K Block Diagram
SFDP Register
000000h
Security Register 1 - 3
0000FFh
003000h
002000h
001000h
0030FFh
0020FFh
0010FFh
Block Segmentation
xxFF00h
•
xxF000h
Sector 15 (4 kB)
xxFFFFh
•
xxF0FFh
xxEF00h
•
xxE000h
Sector 14 (4 kB)
xxEFFFh
•
xxE0FFh
xxDF00h
•
xxD000h
Sector 13 (4 kB)
xxDFFFh
•
xxD0FFh
0FFF00h
•
0F0000h
xx2FFFh
•
xx20FFh
xx1F00h
•
xx1000h
Sector 1 (4 kB)
xx1FFFh
•
xx10FFh
xx0F00h
•
xx0000h
Sector 0 (4 kB)
xx0FFFh
•
xx00FFh
08FF00h
•
080000h
Block 8 (64 kB)
08FFFFh
•
0800FFh
07FF00h
•
070000h
Block 7 (64 kB)
07FFFFh
•
0700FFh
•
•
•
Write Control
Logic
04FF00h
•
040000h
Block 4 (64 kB)
04FFFFh
•
0400FFh
03FF00h
•
030000h
Block 3 (64 kB)
03FFFFh
•
0300FFh
•
•
•
High Voltage
Generators
00FF00h
•
000000h
HOLD# (IO3)
CLK
SPI
Command &
Control Logic
Page Address
Latch / Counter
S25FL008K
Sector 2 (4 kB)
Write Protect Logic and Row Decode
xx2F00h
•
xx2000h
Status
Register
CS#
0FFFFFh
•
0F00FFh
•
•
•
•
•
•
WP# (IO2)
Block 15 (64 kB)
Beginning
Page Address
Block 0 (64 kB)
00FFFFh
•
0000FFh
Ending
Page Address
Column Decode
And 256-byte Page Buffer
Data
SI (IO0)
SO (IO1)
10
Byte Address
Latch / Counter
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
1.3
S h e e t
S25FL016K Block Diagram
SFDP Register
000000h
Security Register 1 - 3
0000FFh
003000h
002000h
001000h
0030FFh
0020FFh
0010FFh
Block Segmentation
xxFF00h
•
xxF000h
Sector 15 (4 kB)
xxFFFFh
•
xxF0FFh
xxEF00h
•
xxE000h
Sector 14 (4 kB)
xxEFFFh
•
xxE0FFh
xxDF00h
•
xxD000h
Sector 13 (4 kB)
xxDFFFh
•
xxD0FFh
1FFF00h
•
1F0000h
xx2FFFh
•
xx20FFh
xx1F00h
•
xx1000h
Sector 1 (4 kB)
xx1FFFh
•
xx10FFh
xx0F00h
•
xx0000h
Sector 0 (4 kB)
xx0FFFh
•
xx00FFh
10FF00h
•
100000h
Block 16 (64 kB)
10FFFFh
•
1000FFh
0FFF00h
•
0F0000h
Block 15 (64 kB)
0FFFFFh
•
0F00FFh
•
•
•
Write Control
Logic
Status
Register
08FF00h
•
080000h
Block 8 (64 kB)
08FFFFh
•
0800FFh
07FF00h
•
070000h
Block 7 (64 kB)
07FFFFh
•
0700FFh
•
•
•
High Voltage
Generators
00FF00h
•
000000h
HOLD# (IO3)
CLK
SPI
Command &
Control Logic
Page Address
Latch / Counter
S25FL016K
Sector 2 (4 kB)
Write Protect Logic and Row Decode
xx2F00h
•
xx2000h
CS#
1FFFFFh
•
1F00FFh
•
•
•
•
•
•
WP# (IO2)
Block 31 (64 kB)
Beginning
Page Address
Block 0 (64 kB)
00FFFFh
•
0000FFh
Ending
Page Address
Column Decode
And 256-byte Page Buffer
Data
SI (IO0)
SO (IO1)
July 14, 2011 S25FL004K-016K_00_02
Byte Address
Latch / Counter
S25FL004K / S25FL008K / S25FL016K
11
D a t a
S h e e t
2. Connection Diagrams
Figure 2.1 8-pin Plastic Small Outline Package (SO)
CS#
1
8
VCC
SO (IO1)
2
7
HOLD# (IO3)
WP# (IO2)
3
6
CLK
GND
4
5
SI (IO0)
3. Input/Output Descriptions
Table 3.1 8-pin SOIC 150-mil / 208-mil
Pin No.
Pin Name
I/O
1
CS#
I
2
SO (IO1)
I/O
3
WP# (IO2)
I/O
4
GND
Function
Chip Select Input
Data Output (Data Input Output 1) (1)
Write Protect Input (Data Input Output 2) (2)
Ground
5
SI (IO0)
I/O
6
CLK
I
7
HOLD# (IO3)
I/O
8
VCC
Data Input (Data Input Output 0) (1)
Serial Clock Input
Hold Input (Data Input Output 3) (2)
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions.
12
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
4.
S h e e t
Ordering Information
The ordering part number is formed by a valid combination of the following:
S25FL
016
K
0X
M
F
I
01
1
Packing Type
0
= Tray
1
= Tube
3
= 13” Tape and Reel
Model Number (Additional Ordering Options)
01 = 8-pin SO package (208 mil)
04 = 8-pin SO package (150 mil)
Temperature Range
I
=
Industrial (–40°C to +85°C)
Package Materials
F
= Lead (Pb)-free
Package Type
M
= 8-pin SO package
Speed
0X =
104 MHz
Device Technology
K
= 0.09 µm process technology
Density
004 =
008 =
016 =
4 Mbit
8 Mbit
16 Mbit
Device Family
S25FL
Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
4.1
Valid Combinations
Table 4.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 4.1 S25FL004K, S25FL008K, and S25FL016K Valid Combinations
Valid Combinations
Base Ordering
Part Number
Speed Option
Package &
Temperature
Model
Number
Packing Type
Package Marking
S25FL004K
0X
MFI
01, 04
0, 1, 3
FL004KIF
S25FL008K
0X
MFI
01, 04
0, 1, 3
FL008KIF
S25FL016K
0X
MFI
01, 04
0, 1, 3
FL016KIF
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
13
D a t a
5.
S h e e t
Functional Description
5.1
5.1.1
SPI Operations
Standard SPI Instructions
The S25FL004K/S25FL008K/S25FL016K is accessed through an SPI compatible bus consisting of four
signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Standard
SPI instructions use the SI input pin to serially write instructions, addresses or data to the device on the rising
edge of CLK. The SO output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode
3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of
CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#.
5.1.2
Dual SPI Instructions
The S25FL004K/S25FL008K/S25FL016K supports Dual SPI operation when using the “Fast Read Dual
Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to
or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read
instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing
non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the SI and SO pins
become bidirectional I/O pins: IO0 and IO1.
5.1.3
Quad SPI Instructions
The S25FL004K/S25FL008K/S25FL016K supports Quad SPI operation when using the “Fast Read Quad
Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O
(E3h)” instructions. These instructions allow data to be transferred to or from the device four to six times the
rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus
(XIP). When using Quad SPI instructions the SI and SO pins become bidirectional IO0 and IO1, and the WP#
and HOLD# pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register-2 to be set.
5.1.4
Hold Function
For Standard SPI and Dual SPI operations, the HOLD# signal allows the S25FL004K/S25FL008K/
S25FL016K operation to be paused while it is actively selected (when CS# is low). The HOLD# function may
be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider
if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case
the HOLD# function can save the state of the instruction and the data in the buffer so programming can
resume where it left off once the bus is available again. The HOLD# function is only available for standard SPI
and Dual SPI operation, not during Quad SPI.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will activate on
the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD#
condition will activate after the next falling edge of CLK. The HOLD# condition will terminate on the rising
edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition
will terminate after the next falling edge of CLK. During a HOLD# condition, the Serial Data Output (SO) is
high impedance, and Serial Data Input (SI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal
should be kept active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic
state of the device.
14
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
5.2
S h e e t
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the S25FL004K/
S25FL008K/S25FL016K provides several means to protect the data from inadvertent writes.
5.2.1
Write Protect Features
 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (WP# pin) write protection using Status Register
 Write Protection using Deep Power-down instruction
 Lock Down write protection until next power-up
 One Time Program (OTP) write protection
Upon power-up or at power-down, the S25FL004K/S25FL008K/S25FL016K will maintain a reset condition
while VCC is below the threshold value of VWI, (see Figure 8.1, Power-Up Timing and Voltage Levels
on page 62). While reset, all operations are disabled and no instructions are recognized. During power-up
and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a
time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase
and the Write Status Register instructions. Note that the chip select pin (CS#) must track the VCC supply level
at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resistor on CS# can be
used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion as small as 4-kB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled or
disabled under hardware control. See Status Register on page 16. for further information. Additionally, the
Deep Power-down instruction offers an extra level of write protection as all instructions are ignored except for
the Release from Deep Power-down instruction.
6. Control and Status Registers
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection,
Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status
Register instruction can be used to configure the device write protection features, Quad SPI setting and
Security Register OTP lock. Write access to the Status Register is controlled by the state of the non-volatile
Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI
operations, the WP# pin.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
15
D a t a
6.1
6.1.1
S h e e t
Status Register
BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/
Program Security Register instruction. During this time the device will ignore further instructions except for the
Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in Section 8.6,
AC Electrical Characteristics on page 64). When the program, erase or write status/security register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
6.1.2
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state
occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
6.1.3
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2)
that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register
Instruction (see tW in AC Electrical Characteristics on page 64). All, none or a portion of the memory array
can be protected from Program and Erase instructions (see Table 6.3 on page 20). The factory default setting
for the Block Protection Bits is 0 (none of the array is protected.)
6.1.4
Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in Table 6.1, Status Register Protection Bits on page 17.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending
on the state of the SRP0, SRP1 and WEL bits.
6.1.5
Sector/Block Protect (SEC)
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as
shown in Table 6.1. The default setting is SEC=0.
6.1.6
Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance,
when CMP=0, a top 4-kB sector can be protected while the rest of the array is not; when CMP=1, the top 4-kB
sector will become unprotected while the rest of the array become read-only. Please refer to Table 6.1 for
details. The default setting is CMP=0.
16
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6.1.7
S h e e t
Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8
and S7). The SRP bits control the method of write protection: software protection, hardware protection, power
supply lock-down or one time programmable (OTP) protection.
Table 6.1 Status Register Protection Bits
SRP1
SRP0
WP#
Status Register
Description
0
0
X
Software Protection
WP# pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware Protected
When WP# pin is low the Status Register locked and can not be
written to.
0
1
1
Hardware Unprotected
When WP# pin is high the Status register is unlocked and can be
written to after a Write Enable instruction, WEL=1.
1
0
X
Power Supply LockDown
Status Register is protected and can not be written to again until
the next power-down, power-up cycle. (1)
1
1
X
One Time Program (2)
Status Register is permanently protected and can not be written
to.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Spansion for details.
6.1.8
Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/
Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah)
instruction as well as a power-down, power-up cycle.
6.1.9
Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB[3:1] is 0, Security Registers are unlocked. LB[3:1] can be set to 1 individually using the
Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-byte Security Register will become read-only permanently.
6.1.10
Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled. When
the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# functions are disabled.
Note: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual
SPI operation, the QE bit should never be set to a 1.
July 14, 2011 S25FL004K-016K_00_02
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Figure 6.1 Status Register 1
S7
S6
S5
S4
S3
S2
SRP0
SEC
TB
BP2
BP1
BP0
S1
S0
WEL BUSY
Status Register Protect 0
(non-volatile)
Sector Protect
(non-volatile)
Top/Bottom Protect
(non-volatile)
Block Protect Bits
(non-volatile)
Write Enable Latch
Erase/Write In Progress
Figure 6.2 Status Register 2
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
LB3
LB2
LB1
(R)
QE
SRP1
Suspend Status
Complement Protect
(non-volatile)
Security Register Lock Bits
(non-volatile OTP)
Reserved
Quad Enable
(non-volatile)
Status Register Protect 1
((non-volatile)
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D a t a
S h e e t
Table 6.2 S25FL004K Status Register Memory Protection (CMP = 0)
Status Register (1)
S25FL004K (4 Mbit) Memory Protection (2)
SEC
TB
BP2
BP1
BP0
Block(s)
Addresses
Density
Portion
X
X
0
0
0
None
None
None
None
0
0
0
0
1
7
070000h – 07FFFFh
64 kB
Upper 1/8
0
0
0
1
0
6 and 7
060000h – 07FFFFh
128 kB
Upper 1/4
0
0
0
1
1
4 thru 7
040000h – 07FFFFh
256 kB
Upper 1/2
0
1
0
0
1
0
000000h – 00FFFFh
64 kB
Lower 1/8
0
1
0
1
0
0 and 1
000000h – 01FFFFh
128 kB
Lower 1/4
0
1
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/2
0
X
1
X
X
0 thru 7
000000h – 07FFFFh
512 kB
All
Upper 1/128
1
0
0
0
1
7
07F000h – 07FFFFh
4 kB
1
0
0
1
0
7
07E000h – 07FFFFh
8 kB
Upper 1/64
1
0
0
1
1
7
07C000h – 07FFFFh
16 kB
Upper 1/32
1
0
1
0
X
7
078000h – 07FFFFh
32 kB
Upper 1/16
1
0
1
1
0
7
078000h – 07FFFFh
32 kB
Upper 1/16
1
1
0
0
1
0
000000h – 000FFFh
4 kB
Lower 1/128
1
1
0
1
0
0
000000h – 001FFFh
8 kB
Lower 1/64
1
1
0
1
1
0
000000h – 003FFFh
16 kB
Lower 1/32
1
1
1
0
X
0
000000h – 007FFFh
32 kB
Lower 1/16
1
1
1
1
0
0
000000h – 007FFFh
32 kB
Lower 1/16
1
X
1
1
1
0 thru 7
000000h – 07FFFFh
512 kB
All
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
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Table 6.3 S25FL008K Status Register Memory Protection (CMP = 0)
Status Register (1)
S25FL008K (8 Mbit) Memory Protection (2)
SEC
TB
BP2
BP1
BP0
Block(s)
Addresses
Density
Portion
X
X
0
0
0
None
None
None
None
Upper 1/16
0
0
0
0
1
15
0F0000h – 0FFFFFh
64 kB
0
0
0
1
0
14 and 15
0E0000h – 0FFFFFh
128 kB
Upper 1/8
0
0
0
1
1
12 thru 15
0C0000h – 0FFFFFh
256 kB
Upper 1/4
0
0
1
0
0
8 thru 15
080000h – 0FFFFFh
512 kB
Upper 1/2
0
1
0
0
1
0
000000h – 00FFFFh
64 kB
Lower 1/16
0
1
0
1
0
0 and 1
000000h – 01FFFFh
128 kB
Lower 1/8
0
1
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/4
0
1
1
0
0
0 thru 7
000000h – 07FFFFh
512 kB
Lower 1/2
0
X
1
0
1
0 thru 15
000000h – 0FFFFFh
1 MB
All
X
X
1
1
X
0 thru 15
000000h – 0FFFFFh
1 MB
All
1
0
0
0
1
15
0FF000h – 0FFFFFh
4 kB
Upper 1/256
1
0
0
1
0
15
0FE000h – 0FFFFFh
8 kB
Upper 1/128
1
0
0
1
1
15
0FC000h – 0FFFFFh
16 kB
Upper 1/64
1
0
1
0
X
15
0F8000h – 0FFFFFh
32 kB
Upper 1/32
1
1
0
0
1
0
000000h – 000FFFh
4 kB
Lower 1/256
1
1
0
1
0
0
000000h – 001FFFh
8 kB
Lower 1/128
1
1
0
1
1
0
000000h – 003FFFh
16 kB
Lower 1/64
1
1
1
0
X
0
000000h – 007FFFh
32 kB
Lower 1/32
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
20
S25FL004K / S25FL008K / S25FL016K
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D a t a
S h e e t
Table 6.4 S25FL016K Status Register Memory Protection (CMP = 0)
Status Register (1)
S25FL016K (16 Mbit) Memory Protection (2)
SEC
TB
BP2
BP1
BP0
Protected Block(s)
Protected Addresses
Protected
Density
Protected Portion (2)
X
X
0
0
0
None
None
None
None
0
0
0
0
1
31
1F0000h – 1FFFFFh
64 kB
Upper 1/32
0
0
0
1
0
30 and 31
1E0000h – 1FFFFFh
128 kB
Upper 1/16
0
0
0
1
1
28 thru 31
1C0000h – 1FFFFFh
256 kB
Upper 1/8
0
0
1
0
0
24 thru 31
180000h – 1FFFFFh
512 kB
Upper 1/4
0
0
1
0
1
16 thru 31
100000h – 1FFFFFh
1 MB
Upper 1/2
0
1
0
0
1
0
000000h – 00FFFFh
64 kB
Lower 1/32
0
1
0
1
0
0 and 1
000000h – 01FFFFh
128 kB
Lower 1/16
0
1
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/8
0
1
1
0
0
0 thru 7
000000h – 07FFFFh
512 kB
Lower 1/4
0
1
1
0
1
0 thru 15
000000h – 0FFFFFh
1 MB
Lower 1/2
X
X
1
1
X
0 thru 31
000000h – 1FFFFFh
2 MB
All
1
0
0
0
1
31
1FF000h – 1FFFFFh
4 kB
Upper 1/512
1
0
0
1
0
31
1FE000h – 1FFFFFh
8 kB
Upper 1/256
1
0
0
1
1
31
1FC000h – 1FFFFFh
16 kB
Upper 1/128
1
0
1
0
X
31
1F8000h – 1FFFFFh
32 kB
Upper 1/64
1
1
0
0
1
0
000000h – 000FFFh
4 kB
Lower 1/512
1
1
0
1
0
0
000000h – 001FFFh
8 kB
Lower 1/256
1
1
0
1
1
0
000000h – 003FFFh
16 kB
Lower 1/128
1
1
1
0
X
0
000000h – 007FFFh
32 kB
Lower 1/64
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
21
D a t a
S h e e t
Table 6.5 S25FL004K Status Register Memory Protection (CMP = 1)
Status Register (1)
S25FL004K (4 Mbit) Memory Protection (2)
SEC
TB
BP2
BP1
BP0
Block(s)
Addresses
Density
Portion
X
X
0
0
0
0 thru 7
000000h – 07FFFFh
512 kB
All
0
0
0
0
1
0 thru 6
000000h – 06FFFFh
448 kB
Lower 7/8
0
0
0
1
0
0 thru 5
000000h – 05FFFFh
384 kB
Lower 3/4
0
0
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/2
0
1
0
0
1
1 thru 7
010000h – 07FFFFh
448 kB
Upper 7/8
0
1
0
1
0
2 thru 7
020000h – 07FFFFh
384 kB
Upper 3/4
0
1
0
1
1
4 thru 7
040000h – 07FFFFh
256 kB
Upper 1/2
1
0
0
0
1
0 thru 7
000000h – 07EFFFh
508 kB
Lower 127/128
1
0
0
1
0
0 thru 7
000000h – 07DFFFh
504 kB
Lower 63/64
1
0
0
1
1
0 thru 7
000000h – 07BFFFh
496 kB
Lower 31/32
1
0
1
0
X
0 thru 7
000000h – 077FFFh
480 kB
Lower 15/16
1
0
1
1
0
0 thru 7
000000h – 077FFFh
480 kB
Lower 15/16
1
1
0
0
1
0 thru 7
001000h – 07FFFFh
508 kB
Upper 127/128
1
1
0
1
0
0 thru 7
002000h – 07FFFFh
504 kB
Upper 63/64
1
1
0
1
1
0 thru 7
004000h – 07FFFFh
496 kB
Upper 31/32
1
1
1
0
X
0 thru 7
008000h – 07FFFFh
480 kB
Upper 15/16
1
1
1
1
0
0 thru 7
008000h – 07FFFFh
480 kB
Upper 15/16
X
X
1
1
1
None
None
None
None
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
Table 6.6 S25FL008K Status Register Memory Protection (CMP = 1)
Status Register (1)
S25FL008K (8 Mbit) Memory Protection (2)
SEC
TB
BP2
BP1
BP0
Block(s)
Addresses
Density
X
X
0
0
0
0 thru 15
000000h – 0FFFFFh
1 MB
Portion
All
0
0
0
0
1
0 thru 14
000000h – 0EFFFFh
960 kB
Lower 15/16
0
0
0
1
0
0 thru 13
000000h – 0DFFFFh
896 kB
Lower 7/8
0
0
0
1
1
0 thru 11
000000h – 0BFFFFh
768 kB
Lower 3/4
0
0
1
0
0
0 thru 7
000000h – 07FFFFh
512 kB
Lower 1/2
0
1
0
0
1
1 thru 15
010000h – 0FFFFFh
960 kB
Upper 15/16
0
1
0
1
0
2 thru 15
020000h – 0FFFFFh
896 kB
Upper 7/8
0
1
0
1
1
4 thru 15
040000h – 0FFFFFh
768 kB
Upper 3/4
0
1
1
0
0
8 thru 15
080000h – 0FFFFFh
512 kB
Upper 1/2
X
X
1
1
1
None
None
None
None
1
0
0
0
1
0 thru 15
000000h – 0FEFFFh
1,020 kB
Lower 255/256
1
0
0
1
0
0 thru 15
000000h – 0FDFFFh
1,016 kB
Lower 127/128
1
0
0
1
1
0 thru 15
000000h – 0FBFFFh
1,008 kB
Lower 63/64
1
0
1
0
X
0 thru 15
000000h – 0F7FFFh
992 kB
Lower 31/32
1
1
0
0
1
0 thru 15
001000h – 0FFFFFh
1,020 kB
Upper 255/256
1
1
0
1
0
0 thru 15
002000h – 0FFFFFh
1,016 kB
Upper 127/128
1
1
0
1
1
0 thru 15
004000h – 0FFFFFh
1,008 kB
Upper 63/64
1
1
1
0
X
0 thru 15
008000h – 0FFFFFh
992 kB
Upper 31/32
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
22
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
Table 6.7 S25FL016K Status Register Memory Protection (CMP = 1)
Status Register (1)
S25FL016K (16 Mbit) Memory Protection (2)
SEC
TB
BP2
BP1
BP0
Protected Block(s)
Protected Addresses
Protected
Density
Protected Portion (2)
X
X
0
0
0
0 thru 31
000000h – 1FFFFFh
All
All
0
0
0
0
1
0 thru 30
000000h – 1EFFFFh
1,984 kB
Lower 31/32
0
0
0
1
0
0 thru 29
000000h – 1DFFFFh
1,920 kB
Lower 15/16
0
0
0
1
1
0 thru 27
000000h – 1BFFFFh
1,792 kB
Lower 7/8
0
0
1
0
0
0 thru 23
000000h – 17FFFFh
1,536 kB
Lower 3/4
0
0
1
0
1
0 thru 15
000000h – 0FFFFFh
1 MB
Lower 1/2
0
1
0
0
1
1 thru 31
010000h – 1FFFFFh
1,984 kB
Upper 31/32
0
1
0
1
0
2 and 31
020000h – 1FFFFFh
1,920 kB
Upper 15/16
0
1
0
1
1
4 thru 31
040000h – 1FFFFFh
1,792 kB
Upper 7/8
0
1
1
0
0
8 thru 31
080000h – 1FFFFFh
1,536 kB
Upper 3/4
0
1
1
0
1
16 thru 31
100000h – 1FFFFFh
1 MB
Upper 1/2
X
X
1
1
X
None
None
None
None
1
0
0
0
1
0 thru 31
000000h – 1FEFFFh
2,044 kB
Lower 511/512
1
0
0
1
0
0 thru 31
000000h – 1FDFFFh
2,040 kB
Lower 255/256
Lower 127/128
1
0
0
1
1
0 thru 31
000000h – 1FBFFFh
2,032 kB
1
0
1
0
X
0 thru 31
000000h – 1F7FFFh
2,016 kB
Lower 63/64
1
1
0
0
1
0 thru 31
001000h – 1FFFFFh
2,044 kB
Upper 511/512
1
1
0
1
0
0 thru 31
002000h – 1FFFFFh
2,040 kB
Upper 255/256
1
1
0
1
1
0 thru 31
004000h – 1FFFFFh
2,032 kB
Upper 127/128
1
1
1
0
X
0 thru 31
008000h – 1FFFFFh
2,016 kB
Upper 63/64
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
7. Instructions
The instruction set of the S25FL004K, S25FL008K, and S25FL008K consist of thirty five basic instructions
that are fully controlled through the SPI bus (see Table 7.3 to Table 7.5 on page 26). Instructions are initiated
with the falling edge of Chip Select (CS#). The first byte of data clocked into the SI input provides the
instruction code. Data on the SI input is sampled on the rising edge of clock with most significant bit (MSB)
first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in the figures below.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8 bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
23
D a t a
S h e e t
Table 7.1 Manufacturer Identification
Manufacturer ID
Value
(MF7-MF0)
EFh
Table 7.2 Device Identification
Device Density
S25FL004K
S25FL008K
S25FL016K
Device ID
Instruction
Value
(ID7-ID0)
ABh, 90h, 92h, 94h
12h
(ID15-ID0)
9Fh
4013h
(ID7-ID0)
ABh, 90h, 92h, 94h
13h
(ID15-ID0)
9Fh
4014h
(ID7-ID0)
ABh, 90h
14h
(ID15-ID0)
9Fh
4015h
Table 7.3 Instruction Set (Erase, Program Instructions (1))
Instruction Name
BYTE 1
(CODE)
Write Enable
06h
Write Enable for Volatile Status
Register
50h
BYTE 2
BYTE 3
BYTE 4
BYTE 5
Write Disable
04h
Read Status Register-1
05h
(S7–S0) (2)
Read Status Register-2
35h
(S15–S8) (2)
Write Status Register
01h
(S7–S0)
Page Program
02h
A23–A16
A15–A8
A7–A0
(D7–D0)
Quad Page Program
32h
A23–A16
A15–A8
A7–A0
(D7–D0, …) (3)
(S15–S8)
Sector Erase (4 kB)
20h
A23–A16
A15–A8
A7–A0
Block Erase (32 kB)
52h
A23–A16
A15–A8
A7–A0
D8h
A23–A16
A15–A8
A7–A0
Block Erase (64 kB)
Chip Erase
BYTE 6
C7h/60h
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Power-down
(S25FL004K/S25FL008K)
B9h
Deep Power-down (S25FL016K)
B9h
Continuous Read Mode Reset
(4)
FFh
FFh
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on
the SO pin.
2. The Status Register contents will repeat continuously until CS# terminates the instruction.
3. Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……)
4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See Section 7.15 and Section 7.16
on page 40 for more information.
24
S25FL004K / S25FL008K / S25FL016K
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S h e e t
Table 7.4 Instruction Set (Read Instructions)
Instruction Name
BYTE 1
(CODE)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
Read Data
03h
A23–A16
A15–A8
A7–A0
(D7–D0)
Fast Read
0Bh
A23–A16
A15–A8
A7–A0
dummy
BYTE 6
(D7–D0)
Fast Read Dual Output
3Bh
A23–A16
A15–A8
A7–A0
dummy
(D7–D0, …) (1)
Fast Read Quad Output
6Bh
A23–A16
A15–A8
A7–A0
dummy
(D7–D0, …) (3)
Fast Read Dual I/O
BBh
A23–A8 (2)
A7–A0, M7–M0
(2)
(D7–D0, …) (1)
Fast Read Quad I/O
EBh
A23–A0,
M7–M0 (4)
(x,x,x,x,
D7–D0, …) (5)
(D7–D0, …) (3)
Word Read Quad I/O (7)
E7h
A23–A0,
M7–M0 (4)
(x,x, D7–D0,
…) (6)
(D7–D0, …) (3)
Octal Word Read Quad I/O (8)
E3h
A23–A0,
M7–M0 (4)
(D7–D0, …) (3)
Set Burst with Wrap
77h
xxxxxx,
W6–W4 (4)
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
Set Burst with Wrap Input
IO0 = x, x, x, x, x, x, W4, x
IO1 = x, x, x, x, x, x, W5, x
IO2 = x, x, x, x, x, x, W6 x
IO3 = x, x, x, x, x, x, x, x
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0, …..)
IO1 = (x, x, x, x, D5, D1, …..)
IO2 = (x, x, x, x, D6, D2, …..)
IO3 = (x, x, x, x, D7, D3, …..)
6. Word Read Quad I/O Data
IO0 = (x, x, D4, D0, …..)
IO1 = (x, x, D5, D1, …..)
IO2 = (x, x, D6, D2, …..)
IO3 = (x, x, D7, D3, …..)
7. The lowest address bit must be 0. (A0 = 0)
8. The lowest 4 address bits must be 0. (A0, A1, A2, A3 = 0)
July 14, 2011 S25FL004K-016K_00_02
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Table 7.5 Instruction Set (ID, Security Instructions)
Instruction Name
BYTE 1
(CODE)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
Release Power down / Device ID
(S25FL004K/S25FL008K)
ABh
dummy
dummy
dummy
(ID7-ID0) (1)
Release from Deep Power down
/ Device ID (S25FL016K)
ABh
dummy
dummy
dummy
(ID7-ID0) (1)
Manufacturer/ Device ID (2)
90h
dummy
dummy
00h
(MF7-MF0)
(ID7-ID0)
BYTE 6
Manufacturer/Device ID by Dual
I/O
92h
A23-A8
A7-A0, M[7:0]
(MF[7:0],
ID[7:0])
Manufacture/Device ID by Quad
I/O
94h
A23-A0, M[7:0]
xxxx, (MF[7:0],
ID[7:0])
(MF[7:0],
ID[7:0], …)
JEDEC ID
9Fh
(MF7-MF0)
Manufacturer
(ID15-ID8)
Memory Type
(ID7-ID0)
Capacity
Read Unique ID
4Bh
dummy
dummy
dummy
dummy
(ID63-ID0)
dummy
(D7-0)
Read SFDP Register
48h, 5Ah
00h
00h
A7-A0
Erase Security Registers (3)
44h
A23-A16
A15-A8
A7-A0
Program Security Registers (3)
42h
A23-A16
A15-A8
A7-A0
(D7-0)
(D7-0)
Read Security Registers (3)
48h
A23-A16
A15-A8
A7-A0
dummy
(D7-0)
Notes:
1. The Device ID will repeat continuously until CS# terminates the instruction.
2. See Manufacturer and Device Identification table for Device ID information.
3. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
7.1
Write Enable (06h)
The Write Enable instruction (Figure 7.1) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip
Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction
is entered by driving CS# low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge
of CLK, and then driving CS# high.
Figure 7.1 Write Enable Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (06h)
SI
SO
26
High Impedance
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S25FL004K-016K_00_02 July 14, 2011
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7.2
S h e e t
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in Section 6.1, Status Register on page 16 can also be written
to as volatile bits. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction.
Write Enable for Volatile Status Register instruction (Figure 7.2) will not set the Write Enable Latch (WEL) bit,
it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.
Figure 7.2 Write Enable for Volatile Status Register Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (50h)
SI
High Impedance
SO
7.3
Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0.
The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the SI pin
and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion
of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector
Erase, Block Erase and Chip Erase instructions.
Figure 7.3 Write Disable Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (04h)
SI
SO
July 14, 2011 S25FL004K-016K_00_02
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27
D a t a
7.4
S h e e t
Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving CS# low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status Register-2
into the SI pin on the rising edge of CLK. The status register bits are then shifted out on the SO pin at the
falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.4. The Status Register bits are
shown in Figure 6.1 and Figure 6.2 and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE,
LB3-1, CMP and SUS bits (see Section 6.1, Status Register on page 16).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is
complete and if the device can accept another instruction. The Status Register can be read continuously, as
shown in Figure 7.4. The instruction is completed by driving CS# high.
Figure 7.4 Read Status Register Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15
16 17
18 19
20
21 22 23
Mode 0
Instruction (05h or 35h)
SI
Status Register 1 or 2 Out
Status Register 1 or 2 Out
High Impedance
7
SO
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
7.5
Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1,
QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit locations are
read-only and will not be affected by the Write Status Register instruction. LB3-1 are non-volatile OTP bits;
once each is set to 1, it can not be cleared to 0. The Status Register bits are shown in Figure 6.1 and
Figure 6.2 on page 18, and described Section 6.1, Status Register on page 16.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must
equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code
“01h”, and then writing the status register data byte as illustrated in Figure 7.5.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRP1 and LB3, LB2, LB1 can not be changed from 1 to 0 because of the OTP protection for these bits. Upon
power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will
be restored when power on again.
To complete the Write Status Register instruction, the CS# pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If CS# is driven high after the eighth clock the CMP, QE and SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high, the
self-timed Write Status Register cycle will commence for a time duration of tW (see Section 8.6, AC Electrical
Characteristics on page 64). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write
Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After
the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
28
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During volatile Status Register write operation (50h combined with 01h), after CS# is driven high, the Status
Register bits will be refreshed to the new values within the time period of tSHSL2 (see Section 8.6, AC
Electrical Characteristics on page 64). BUSY bit will remain 0 during the Status Register bit refresh period.
Refer to Section 6.1, Status Register on page 16 for detailed Status Register Bit descriptions. Factory default
for all status Register bits are 0.
Figure 7.5 Write Status Register Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17
18 19
Mode 0
20 21 22 23 Mode 3
Mode 0
Status Register In
Instruction (01h)
SI
7
6
5
4
3
2
1
0
X 14 13 12 11
X
9
8
High Impedance
SO
= MSB
7.6
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the CLK
pin. After the address is received, the data byte of the addressed memory location will be shifted out on the
SO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream
of data. This means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in Figure 7.6. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects
on the current cycle. The Read Data instruction allows clock rates from DC to a maximum of fR. (See AC
Electrical Characteristics on page 64.)
Figure 7.6 Read Data Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32
33 34 35 36 37 38 39
Mode 0
24-Bit Address
Instruction (03h)
SI
23 22 21
3
2
1
0
Data Out 1
High Impedance
SO
7
6
5
4
3
Data Out 2
2
1
0
7
= MSB
July 14, 2011 S25FL004K-016K_00_02
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29
D a t a
7.7
S h e e t
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR. (See AC Electrical Characteristics on page 64.) This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in Figure 7.7. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value on
the SO pin is a “don’t care”.
Figure 7.7 Fast Read Instruction Sequence Diagram
CS#
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28 29
30 31
Mode 0
24-Bit Address
Instruction (0Bh)
SI
23
22 21
3
2
1
0
SO
CS#
32
33 34 35
36 37
38 39 40 41
42
43 44
45 46 47
CLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
Data Out 1
SO
7
6
5
4
3
Data Out 2
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
30
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S25FL004K-016K_00_02 July 14, 2011
D a t a
7.8
S h e e t
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins; IO0 and IO1. This allows data to be transferred from the S25FL004K/S25FL008K/
S25FL016K at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for
quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR. (See AC Electrical Characteristics on page 64.) This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in Figure 7.8. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
Figure 7.8 Fast Read Dual Output Instruction Sequence Diagram
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29
30 31
Mode 0
24-Bit Address
Instruction (3Bh)
IO0
23
22 21
3
2
1
0
IO1
CS
32
33 34 35
36 37
38 39 40
41
42
43 44 45 46 47
48 49 50
51 52 53
54 55
CLK
IO_0 Switches from Input to Output
Dummy Clocks
IO0
6
4
2
0
6
4
2
0
6
4
2
0
6
IO1
7
5
3
1
7
5
3
1
7
5
3
1
7
Data Out 1
Data Out 2
Data Out 3
4
5
2
0
6
3
1
7
Data Out 4
= MSB
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31
D a t a
7.9
S h e e t
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except
that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed
before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1).
The Fast Read Quad Output Instruction allows data to be transferred from the S25FL004K/S25FL008K/
S25FL016K at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR. (See AC
Electrical Characteristics on page 64.) This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in Figure 7.9. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock.
Figure 7.9 Fast Read Quad Output Instruction Sequence Diagram
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29
30 31
Mode 0
24-Bit Address
Instruction (6Bh)
23
IO0
22
21
3
2
1
0
44
45
46 47
IO1
IO2
IO3
CS
32
33
34
35
36
37
38
39
40
41
42
43
CLK
IO_0 Switches from Input to Output
Dummy Clocks
IO0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
IO3
Byte 1 Byte 2
32
S25FL004K / S25FL008K / S25FL016K
Byte 3
Byte 4
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.10
S h e e t
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins,
IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the
Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP)
directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.10. The upper nibble of the
(M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after CS# is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 7.11. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions. (See Continuous Read Mode Reset (FFh or FFFFh) on page 40.)
Figure 7.10 Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)
CS#
CLK
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17
18 19
20 21 22 23 Mode 3
Mode 0
Mode 0
Instruction (BBh)
IO0
6
IO1
7
4
2
5
3
0
1
6
7
4
2
0
6
4
2
0
6
4
5
3
1
7
5
3
1
7
5
A15-8
A23-16
A7-0
M7-0
CS#
23 24 25
26 27
28 29 30
31 32
33 34 35 36
37 38 39
CLK
IO Switches from Input to Output
IO0
6
4
2
0
6
4
2
0
6
IO1
7
5 3
Byte 1
1
7
5 3
Byte 2
1
7
July 14, 2011 S25FL004K-016K_00_02
2
0
6
4
2
0
5 3
Byte 3
1
7
5
3
Byte 4
1
4
S25FL004K / S25FL008K / S25FL016K
6
33
D a t a
S h e e t
Figure 7.11 Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
IO0
6
IO1
7
4
2
5
3
0
1
6
4
2
0
6
4
7
5
3
1
7
5
A15-8
A23-16
2
0
6
4
3
1
7
5
M7-0
A7-0
CS#
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
6
4
2
0
6
7
5
3
1
7
CLK
IO Switches from Input to Output
IO0
6
IO1
7
4
2
0
6
4
2
0
6
4
2
5
3
1
7
5
3
1
7
5
3
Byte 2
Byte 1
7.11
0
1
Byte 3
Byte 4
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are
required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status
Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.12, Fast Read Quad I/O
Instruction Sequence (Initial instruction or previous M5-4 ¹10) on page 35. The upper nibble of the (M7-4)
controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first
byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the EBh instruction code, as shown in Figure 7.13, Fast Read
Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page 35. This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low.
If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is raised and
then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read
Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (see
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page 40).
34
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
Figure 7.12 Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13
14 15 16
17 18 19 20 21 22 23
Mode 0
IO Switches from
Input to Output
Instruction (EBh)
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
3
7
3
7
IO3
A15-8
A23-16
M7-0
A7-0
Dummy Dummy
Byte 1
Byte 2
Figure 7.13 Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
CS#
CLK
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
IO Switches from Input to Output
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16
A15-8
A7-0
M7-0
Dummy
Dummy
Byte 1
Byte 2
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a
“Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output
data starts at the initial address specified in the instruction, once it reaches the ending boundary of the
8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. See Section 7.14, Set Burst with Wrap (77h) on page 39.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
35
D a t a
7.12
S h e e t
Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that
the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data output. The
Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP)
directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word
Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.14. The upper nibble of the
(M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E7h instruction code, as shown in Figure 7.15. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page 40).
Figure 7.14 Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
15 16 17 18
19 20 21 22
23
CLK Mode 0
IO Switches from
Input to Output
Instruction (E7h)
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16
36
A15-8
A7-0
S25FL004K / S25FL008K / S25FL016K
M7-0
Dummy
Byte 1
Byte 2
3
Byte 3
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
Figure 7.15 Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
Mode 0
IO Switches from Input to Output
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
IO3
A23-16
A15-8
A7-0
M7-0
Dummy
Byte 1
Byte 2
3
Byte 3
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a
“Set Burst with Wrap” command prior to E7h. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output
data starts at the initial address specified in the instruction, once it reaches the ending boundary of the
8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. See Section 7.14, Set Burst with Wrap (77h) on page 39.
7.13
Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not
required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read
Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.16, Octal
Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 ¹ 10) on page 38. The upper
nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”).
However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E3h instruction code, as shown in Figure 7.17, Octal Word
Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page 38. This reduces the
instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page 40).
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
37
D a t a
S h e e t
Figure 7.16 Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10)
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15
16 17 18 19
20 21 22 23
Mode 0
Instruction (E3h)
IO Switches from Input to Output
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
IO3
A15-8
A23-16
M7-0
A7-0
Dummy
Byte 2
Byte 1
Byte 3
Figure 7.17 Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
CS#
CLK
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
IO Switches from Input to Output
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16
38
A15-8
A7-0
M7-0
Byte 1
S25FL004K / S25FL008K / S25FL016K
Byte 2
Byte 3
Byte 4
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.14
S h e e t
Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read
Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain
applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the CS# pin low and
then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction
sequence is shown in Figure 7.18, Set Burst with Wrap Instruction Sequence on page 39. Wrap bit W7 and
the lower nibble W3-0 are not used.
W6, W5
W4 = 0
Wrap Around
W4 =1 (DEFAULT)
Wrap Length
Wrap Around
Wrap Length
N/A
00
Yes
8-byte
No
01
Yes
16-byte
No
N/A
10
Yes
32-byte
No
N/A
11
Yes
64-byte
No
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page.
To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a
system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap instruction to
reset W4 = 1 prior to any normal Read instructions since S25FL004K/S25FL008K/S25FL016K does not have
a hardware Reset Pin.
Figure 7.18 Set Burst with Wrap Instruction Sequence
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
Instruction (77h)
IO0
X
X
X
X
X
X
w4
X
IO1
X
X
X
X
X
X
w5
X
IO2
X
X
X
X
X
X
w6
X
X
X
X
X
X
X
X
X
IO3
don’t care don’t care don’t care
7.15
wrap bit
Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”,
“Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random Flash
memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place) to be
performed on serial flash devices.
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit SPI
instruction code (BBh, EBh, E7h or E3h) is needed or not for the next command. When M5-4 = (1,0), the next
command will be treated same as the current Dual/Quad I/O Read command without needing the 8-bit
instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can
be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
39
D a t a
7.16
S h e e t
Continuous Read Mode Reset (FFh or FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in Figure 7.19.
Figure 7.19 Continuous Read Mode Reset for Fast Read Dual/Quad I/O
Mode Bit Reset
for Quad I/O
Mode Bit Reset
for Quad I/O
CS#
Mode 3
CLK
IO0
0
1
2
3
4
5
6
7
8
9
10
11
12
Mode 0
13
14
15
Mode 3
Mode 0
FFh
FFh
IO1
Don’t Care
IO2
Don’t Care
IO3
Don’t Care
Since S25FL004K/S25FL008K/S25FL016K does not have a hardware Reset pin, so if the controller resets
while S25FL004K/S25FL008K/S25FL016K is set to Continuous Mode Read, the S25FL004K/S25FL008K/
S25FL016K will not recognize any initial standard SPI instructions from the controller. To address this
possibility, it is recommended to issue a Continuous Read Mode Reset instruction as the first instruction after
a system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard SPI
instructions to be recognized.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is
“FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in
instruction “FFFFh”.
40
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.17
S h e e t
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving
the CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least
one data byte, into the SI pin. The CS# pin must be held low for the entire length of the instruction while data
is being sent to the device. The Page Program instruction sequence is shown in Figure 7.20, Page Program
Instruction Sequence Diagram on page 41.
If an entire 256-byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not 0, and the number of clocks exceed the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks can not exceed the remaining page length. If
more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and
overwrite previously sent data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After CS# is driven
high, the self-timed Page Program instruction will commence for a time duration of tPP. (See AC Electrical
Characteristics on page 64.) While the Page Program cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page
Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected
by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.
Figure 7.20 Page Program Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29
30
31 32 33
34 35 36 37 38 39
Mode 0
Instruction (02h)
Data Byte 1
24-Bit Address
23
SI
22 21
3
2
1
2
1
0
0
7
6
5
4
3
2
1
0
CS#
CLK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
7
6
5
4
3
2
1
0
= MSB
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
41
D a t a
7.18
S h e e t
Quad Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve
performance for PROM Programmer and applications that have slow clock speeds <5 MHz. Systems with
faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent
page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the CS# pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The CS# pin must be
held low for the entire length of the instruction while data is being sent to the device. All other functions of
Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence
is shown in Figure 7.21, Quad Page Program Instruction Sequence Diagram on page 42.
Figure 7.21 Quad Page Program Instruction Sequence Diagram
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28 29
30
31 32 33
34 35 36 37 38 39
Byte 1
Byte 2
Byte 3
Byte 4
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
537
538
539
540
Mode 0
536
CLK
Instruction (32h)
24-Bit Address
IO0
23
22
21
3
2
1
0
44
45 46 47
48 49
50
51 52 53
54 55
543
41 42 43
542
40
541
CS#
CLK
Mode 3
Mode 0
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10 Byte 11 Byte 12
IO0
4
0
4
0
4
0
4
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
0
4
4
0
4
0
4
0
4
0
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
7
3
0
4
5
1
5
2
6
2
3
7
3
Byte 253 Byte 254 Byte 255 Byte 256
0
3
= MSB
42
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.19
S h e e t
Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the
instruction code “20h” followed a 24-bit sector address (A23-A0). (See Section 1., Block Diagrams on page 9
for the block diagrams of S25FL004K, S25FL008K, and S25FL016K.) The Sector Erase instruction sequence
is shown in Figure 7.22 on page 43.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After CS# is driven high, the self-timed Sector Erase instruction
will commence for a time duration of tSE. (See AC Electrical Characteristics on page 64.) While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not
be executed if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits (see Table 6.2, Table 6.3, and Table 6.4 for Status Register Memory Protection (CMP = 0)).
Figure 7.22 Sector Erase Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
29 30 31 Mode 3
Mode 0
Mode 0
Instruction (20h)
SIO
24-Bit Address
23 22
2
1
0
High Impedance
SO
= MSB
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
43
D a t a
7.20
S h e e t
32 KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32k-bytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the
instruction code “52h” followed a 24-bit block address (A23-A0). (See Section 1., Block Diagrams on page 9
for the block diagrams of S25FL004K, S25FL008K,and S25FL016K.) The Block Erase instruction sequence
is shown in Figure 7.23.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1. (See AC Electrical Characteristics on page 64.) While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed
if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Table 6.2, Table 6.3, and Table 6.4 for Status Register Memory Protection (CMP = 0)).
Figure 7.23 32 kB Block Erase Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
29 30 31 Mode 3
Mode 0
Mode 0
Instruction (52h)
SIO
24-Bit Address
23 22
2
1
0
High Impedance
SO
= MSB
44
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.21
S h e e t
64 KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64k-bytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the
instruction code “D8h” followed a 24-bit block address (A23-A0). (See Section 1., Block Diagrams on page 9
for the block diagrams of S25FL004K, S25FL008K,and S25FL016K.) The Block Erase instruction sequence
is shown in Figure 7.24.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE. (See AC Electrical Characteristics on page 64.) While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed
if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Table 6.2, Table 6.3, and Table 6.4 for Status Register Memory Protection (CMP = 0)).
Figure 7.24 64 kB Block Erase Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
29
30
31
Mode 3
Mode 0
Mode 0
Instruction (D8h)
SI
24-Bit Address
23
22
2
1
0
High Impedance
SO
= MSB
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
45
D a t a
7.22
S h e e t
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 7.25.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence
for a time duration of tCE. (See AC Electrical Characteristics on page 64.) While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The
BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the
Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Table 6.2, Table 6.3, and Table 6.4 for Status
Register Memory Protection (CMP = 0)).
Figure 7.25 Chip Erase Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
Mode 0
5
6
7
Mode 3
Mode 0
Instruction (C7h/60h)
SI
SO
46
High Impedance
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.23
S h e e t
Erase / Program Suspend (75h)
The Erase/Program Suspend instruction 75h, allows the system to interrupt a Sector or Block Erase operation
or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The
Erase/Program Suspend instruction sequence is shown in Figure 7.26, Erase/Program Suspend Instruction
Sequence on page 47.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register
instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend.
Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction 75h will be accepted by the device only if the SUS bit in the Status
Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation
is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by
the device. A maximum of time of tSUS (Section 8.6, AC Electrical Characteristics on page 64) is required to
suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0
within tSUS and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program
Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction
75h is not issued earlier than a minimum of time of tSUS following the preceding Resume instruction 7Ah.
Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend
state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was
being suspended may become corrupted. It is recommended for the user to implement system design
techniques against the accidental power interruption and preserve data integrity during erase/program
suspend state.
Figure 7.26 Erase/Program Suspend Instruction Sequence
CS#
t SUS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (75h)
SI
High Impedance
SO
Accept Read or Program Instruction
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
47
D a t a
7.24
S h e e t
Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation
or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be
accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0.
After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within
200 ns and the Sector or Block will complete the erase operation or the page will complete the program
operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored
by the device. The Erase/Program Resume instruction sequence is shown in Figure 7.27.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be
issued within a minimum of time of “tSUS” following a previous Resume instruction.
Figure 7.27 Erase/Program Resume Instruction Sequence
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (7Ah)
SI
Resume Sector or Block Erase
48
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.25
S h e e t
Deep Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced
with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down
instruction especially useful for battery powered applications (see ICC1 and ICC2 in Section 8.4, DC Electrical
Characteristics on page 63). The instruction is initiated by driving the CS# pin low and shifting the instruction
code “B9h” as shown in Figure 7.28.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep Powerdown instruction will not be executed. After CS# is driven high, the power-down state will entered within the
time duration of tDP. (See AC Electrical Characteristics on page 64.) While in the power-down state only the
Release from Deep Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is
always available during normal operation. Ignoring all but one instruction makes the Power Down state a
useful condition for securing maximum write protection. The device always powers-up in the normal operation
with the standby current of ICC1.
Figure 7.28 Deep Power-down Instruction Sequence Diagram
CS#
t DP
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (B9h)
SI
Standard Current
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
Deep Power-down Current
49
D a t a
7.26
S h e e t
Release from Deep Power-down / Device ID (ABh)
The Release from Deep Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the deep power-down state, or obtain the devices electronic identification (ID)
number.
To release the device from the deep power-down state, the instruction is issued by driving the CS# pin low,
shifting the instruction code “ABh” and driving CS# high as shown in Figure 7.29. Release from deep powerdown will take the time duration of tRES1 (Section 8.6, AC Electrical Characteristics on page 64) before the
device will resume normal operation and other instructions are accepted. The CS# pin must remain high
during the tRES1 time duration.
When used only to obtain the Device ID while not in the deep power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits
are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID values for
the S25FL004K/S25FL008K/S25FL016K is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The instruction is completed by driving CS# high.
When used to release the device from the deep power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 7.30, except that after CS# is driven high it must
remain high for a time duration of tRES2. After this time duration the device will resume normal operation and
other instructions will be accepted. If the Release from Deep Power-down / Device ID instruction is issued
while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will
not have any effects on the current cycle.
Figure 7.29 Release from Deep Power-down Instruction Sequence
CS#
t RES1
0
Mode 3
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Mode 0
Instruction (ABh)
SI
High Impedance
SO
Deep Power-down Current
Stand-by Current
Figure 7.30 Release from Deep Power-down / Device ID Instruction Sequence Diagram
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7 8
9
10
Mode 3
28 29 30 31 32 33 34 35 36 37 38
Mode 0
Mode 0
Instruction (ABh)
23 22 21
SI
t RES2
3 Dummy Bytes
3
2
1
0
Device ID
High Impedance
SO
7
5
4
3
2
1
0
Deep Power-down Current
= MSB
50
6
S25FL004K / S25FL008K / S25FL016K
Stand-by Current
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.27
S h e e t
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Deep Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Deep Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID and the Device ID are
shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.31. The Device
ID values for the S25FL004K/S25FL008K/S25FL016K is listed in Table 7.2, Device Identification on page 24.
If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the
other. The instruction is completed by driving CS# high.
Figure 7.31 Read Manufacturer / Device ID Diagram
CS#
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28 29 30
31
Mode 0
Address (000000h)
Instruction (90h)
SI
23
22 21
3
2
1
0
High Impedance
SO
CS#
31
32 33 34 35 36
37 38 39 40 41 42
Mode 3
43 44 45 46
CLK
Mode 0
SI
Manufacturer ID
Device ID (
)
SO
7
6
5
4
3
2
1
0
= MSB
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
51
D a t a
7.28
S h e e t
Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The
instruction is initiated by driving the CS# pin low and shifting the instruction code “92h” followed by a 24-bit
address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After which,
the Manufacturer ID and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most
significant bits (MSB) first as shown in Figure 7.32. The Device ID values for the S25FL004K/S25FL008K/
S25FL016K is listed in Table 7.2, Device Identification on page 24. If the 24-bit address is initially set to
000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and
Device IDs can be read continuously, alternating from one to the other. The instruction is completed by
driving CS# high.
Figure 7.32 Read Manufacturer / Device ID Dual I/O Diagram
CS#
CLK
IO0
IO1
CS#
CLK
IO0
IO1
Note:
1. The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
52
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.29
S h e e t
Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The
instruction is initiated by driving the CS# pin low and shifting the instruction code “94h” followed by a four
clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input the
Address bits four bits per clock. After which, the Manufacturer ID and the Device ID are shifted out four bits
per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.33. The Device
ID values for the S25FL004K/S25FL008K/S25FL016K is listed in Table 7.2, Device Identification on page 24.
If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the
other. The instruction is completed by driving CS# high.
Figure 7.33 Read Manufacturer / Device ID Quad I/O Diagram
CS#
CLK
IO0
IO1
IO2
IO3
CS#
CLK
IO0
IO1
IO2
IO3
Note:
1. The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
53
D a t a
7.30
S h e e t
Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each S25FL004K/S25FL008K/S25FL016K device. The ID number can be used in conjunction with user
software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated
by driving the CS# pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks.
After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in Figure 7.34.
Figure 7.34 Read Unique ID Number Instruction Sequence
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15 16
17 18 19
20 21 22 23
Mode 0
Dummy 1
Instruction (4B)
Dummy 2
SI
High Impedance
SO
CS#
24 25 26 27 28
29 30 31
32 33
34
35 36 37 38 39
40
41 42
43 44 101 102 103 Mode 3
Mode 0
CLK
Dummy 3
Dummy 4
64-bit Unique Serial Number
SI
*
SO
63
62 61 60 59
2
1
0
= MSB
54
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.31
S h e e t
Read JEDEC ID (9Fh)
For compatibility reasons, the S25FL004K/S25FL008K/S25FL016K provides several instructions to
electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the
JEDEC standard for SPI compatible serial flash memories that was adopted in 2003. The instruction is
initiated by driving the CS# pin low and shifting the instruction code “9Fh”. The JEDEC assigned
Manufacturer ID byte and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then
shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.35. For
memory type and capacity values refer to Manufacturer and Device Identification table.
Figure 7.35 Read JEDEC ID Instruction Sequence
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
Mode 0
Instruction (9Fh)
SI
Manufacturer ID (EFh)
High Impedance
SO
CS#
15 16
16 17
17 18
18
15
19
19
20
20
21
21
22 23
23 24
24
22
25 26
26 27
27 28
28 29
29 30
30 31
31
25
Mode 3
Mode 0
CLK
SI
Memory Type ID15-ID8
SO
7
6
5
4
3
2
1
Capacity ID7-ID0
0
7
6
5
4
3
2
1
0
= MSB
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
55
D a t a
7.32
S h e e t
Read SFDP Register (5Ah)
The S25FL004K/S25FL008K/S25FL016K features a 256-byte Serial Flash Discoverable Parameter (SFDP)
register that contains information about devices operational capability such as available commands, timing
and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables.
Currently only one PID table is specified but more may be added in the future. The Read SFDP Register
instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications.
The Read SFDP instruction is initiated by driving the CS# pin low and shifting the instruction code “5Ah”
followed by a 24-bit address (A23-A0)(1) into the SI pin. Eight “dummy” clocks are also required before the
SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first
as shown in Figure 7.36. For SFDP register values and descriptions, refer to Table 7.6.
Note: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-byte SFDP Register.
Figure 7.36 Read SFDP Register Instruction Sequence Diagram
CS#
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28 29
30 31
Mode 0
24-bit Address
Instruction (5Ah)
SI
23
22 21
3
2
1
0
44 45 46
47
SO
CS#
32
33 34 35
36 37
38 39 40 41
42 43
CLK
Dummy Byte
SI
Data Out 1
SO
7
6
5
4
3
Data Out 2
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
Table 7.6 Serial Flash Discoverable Parameter Definition Table (Sheet 1 of 2)
Byte Address
Data
Description
00h
53h
SFDP Signature
01h
46h
SFDP Signature
02h
44h
SFDP Signature
Comment
SFDP Signature = 50444653h
03h
50h
SFDP Signature
04h
01h
SFDP Minor Revisions
05h
01h
SFDP Major Revisions
06h
00h
Number of Parameter Headers (NPH)
SFDP revision 1.1
07h
FFh
Reserved
08h
EFh
PID (3)(0): Manufacturer JEDEC ID
09h
00h
PID(0): Serial Flash Basics Minor Revisions
0Ah
01h
PID(0): Serial Flash Basics Major Revisions
1 Parameter Header
EFh
Serial Flash Basics Revision 1.0
56
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
Table 7.6 Serial Flash Discoverable Parameter Definition Table (Sheet 2 of 2)
Byte Address
Data
0Bh
04h
PID(0): Serial Flash Basics Length
Description
0Ch
80h
PID(0): Address of Parameter ID(0) Table (A7-A0)
0Dh
00h
PID(0): Address of Parameter ID(0) Table (A15-A8)
0Eh
00h
PID(0): Address of Parameter ID(0) Table (A23-A16)
0Fh
FFh
Reserved
10h
EFh
PID(1): Manufacturer JEDEC ID
11h
00h
PID(1): Serial Flash Properties Minor Revisions
12h
01h
PID(1): Serial Flash Properties Major Revisions
13h
00h
PID(1): Serial Flash Properties Length
14h
90h
PID(1): Address of Parameter ID(1) Table (A7-A0)
15h
00h
PID(1): Address of Parameter ID(1) Table (A15-A8)
16h
00h
PID(1): Address of Parameter ID(1) Table (A23-A16)
Comment
4 Dwords (2)
PID(0) Table Address = 000080h
EFh
Serial Flash Properties Revision 1.0
17h
FFh
Reserved
... (1)
FFh
Reserved
80h
E5h
Bit[7:5]
Bit[4:3]
Bit[2]
Bit[1:0]
81h
20h
4 kbyte Erase Opcode
F1h
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2:1]
Bit[0]
82h
=
=
=
=
=
=
=
=
=
=
=
111
00
1
01
1
1
1
1
0
00
1
Reserved
Supports Single Input Quad Output
Supports Quad Input Quad Output
Supports Dual Input Dual Output
Dual Transfer Rate not Supported
3-byte/24-bit Addressing
Supports Single Input Dual Output
FFh
Reserved
84h
FFh
Flash Size in Bits
85h
FFh
Flash Size in Bits
3Fh
(S25FL004K)
86h
PID(1) Table Address = 000090h
Reserved
Non-volatile Status Register
Page Programmable
Supports 4 kB Erase
83h
7Fh
(S25FL008K)
00h = Unimplemented
4 Megabits = 003FFFFFh (S25FL004K)
8 Megabits = 007FFFFFh (S25FL008K)
Flash Size in Bits
16 Megabits = 00FFFFFFh (S25FL016K)
FFh
(S25FL016K)
87h
00h
Flash Size in Bits
88h
44h
Bit[7:5] = 010
Bit[4:0] = 00100
89h
EBh
Quad Input Quad Output Fast Read Opcode
8Ah
08h
Bit[7:5] = 000
Bit[4:0] = 01000
8Bh
6Bh
Single Input Quad Output Fast Read Opcode
8Ch
08h
Bit[7:5] = 000
Bit[4:0] = 01000
8Dh
3Bh
Single Input Dual Output Fast Read Opcode
8Eh
80h
Bit[7:5] = 100
Bit[4:0] = 00000
8Fh
BBh
Dual Input Dual Output Fast Read Opcode
... (1)
FFh
Reserved
FFh
FFh
Reserved
8 Mode Bits are needed
16 Dummy Bits are needed
No Mode Bits are needed
8 Dummy Bits are needed
No Mode Bits are needed
8 Dummy Bits are needed
8 Mode bits are needed
No Dummy bits are needed
Fast Read Quad I/O Setting
Fast Read Quad Output Setting
Fast Read Dual Output Setting
Fast Read Dual I/O Setting
Notes:
1. Data stored in Byte Address 18h to 7Fh and 90h to FFh are Reserved, the value is FFh.
2. 1 Dword = 4 bytes.
3. PID(x) = Parameter Identification Table (x).
July 14, 2011 S25FL004K-016K_00_02
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57
D a t a
7.33
S h e e t
Erase Security Registers (44h)
The S25FL004K/S25FL008K/S25FL016K offers three 256-byte Security Registers which can be erased and
programmed individually. These registers may be used by the system manufacturers to store security and
other important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
Address
A23-16
A15-12
A11-8
A7-0
Security Register #1
00h
0001b
0000b
Don’t Care
Security Register #2
00h
0010b
0000b
Don’t Care
Security Register #3
00h
0011b
0000b
Don’t Care
The Erase Security Register instruction sequence is shown in Figure 7.37. The CS# pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (see AC Electrical Characteristics on page 64). While the Erase Security Register cycle is in progress,
the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY
bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Security Register Lock Bits (LB3:1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will
be permanently locked, and an Erase Security Register instruction to that register will be ignored (see
Security Register Lock Bits (LB3, LB2, LB1) on page 17).
Figure 7.37 Erase Security Registers Instruction Sequence
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
29
30
31
Mode 0
Mode 3
Mode 0
24-bit Address
Instruction (44h)
SI
23
22
2
1
0
High Impedance
SO
= MSB
58
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
7.34
S h e e t
Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte
to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write
Enable instruction must be executed before the device will accept the Program Security Register Instruction
(Status Register bit WEL= 1). The instruction is initiated by driving the CS# pin low then shifting the instruction
code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the SI pin. The CS# pin
must be held low for the entire length of the instruction while data is being sent to the device.
Address
A23-16
A15-12
A11-8
A7-0
Security Register #1
00h
0001b
0000b
Byte Address
Security Register #2
00h
0010b
0000b
Byte Address
Security Register #3
00h
0011b
0000b
Byte Address
The Program Security Register instruction sequence is shown in Figure 7.38. The Security Register Lock Bits
(LB3:1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1,
the corresponding security register will be permanently locked, and a Program Security Register instruction to
that register will be ignored (see Security Register Lock Bits (LB3, LB2, LB1) on page 17 and Page Program
(02h) on page 41 for detail descriptions).
Figure 7.38 Program Security Registers Instruction Sequence
CS#
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28 29
30 31 32 33 34
35 36 37 38 39
Mode 0
24-bit Address
Instruction (42h)
SI
3
2
Data Byte 1
23
22 21
1
49
50 51 52 53 54 55
0
7
6
5
4
3
2
1
0
2079
2077
2078
2076
2075
46 47 48
2073
41 42 43 44 45
2074
40
2072
CS#
Mode 0
CLK
Data Byte 2
SI
Mode 3
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
1
0
= MSB
July 14, 2011 S25FL004K-016K_00_02
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59
D a t a
7.35
S h e e t
Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving the
CS# pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight
“dummy” clocks into the SI pin. The code and address bits are latched on the rising edge of the CLK pin. After
the address is received, the data byte of the addressed memory location will be shifted out on the SO pin at
the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to
the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the
register (byte FFh), it will reset to 00h, the first byte of the register, and continue to increment. The instruction
is completed by driving CS# high. The Read Security Register instruction sequence is shown in Figure 7.39.
If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process
(BUSY=1), the instruction is ignored and will not have any effects on the current cycle. The Read Security
Register instruction allows clock rates from DC to a maximum of FR (see Section 8.6, AC Electrical
Characteristics on page 64).
Address
A23-16
A15-12
A11-8
A7-0
Security Register #1
00h
0001b
0000b
Byte Address
Security Register #2
00h
0010b
0000b
Byte Address
Security Register #3
00h
0011b
0000b
Byte Address
Figure 7.39 Read Security Registers Instruction Sequence
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29
30 31
Mode 0
24-bit Address
Instruction (48h)
SI
23 22
21
3
2
1
0
SO
CS#
32
33 34 35
7
6
36
37 38 39 40
41
42 43 44
45 46
47
CLK
Dummy Byte
SI
5
4
3
2
1
0
Data Out 1
SO
7
6
5
4
3
Data Out 2
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
60
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
8.
8.1
S h e e t
Electrical Characteristics
Absolute Maximum Ratings
Parameters(1)
Symbol
Conditions
Range
Unit
Supply Voltage
VCC
–0.6 to +4.0
V
Voltage Applied to Any Pin
VIO
Relative to Ground
–0.6 to VCC+0.4
V
Transient Voltage on any Pin
VIOT
<20 ns Transient Relative to Ground
–2.0V to VCC+2.0V
V
Storage Temperature
TSTG
–65 to +150
°C
Lead Temperature
TLEAD
(Note 2)
°C
Electrostatic Discharge Voltage
VESD
–2000 to +2000
V
Human Body Model (3)
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed.
Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent
damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on
restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
8.2
Operating Ranges
Parameter
Symbol
Conditions
S25FL004K
S25FL008K
Spec
S25FL016K
Min
Unit
Max
FR = 104 MHz FR = 104 MHz FR = 104 MHz
3.0
Supply Voltage (1)
VCC
Ambient Temperature,
Operating
TA
fR = 50 MHz
fR = 50 MHz
FR = 80 MHz
FR = 80 MHz
FR = 70 MHz
fR = 50 MHz
fR = 50 MHz
fR = 50 MHz
3.6
V
+85
°C
2.7
Industrial
–40
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write)
voltage.
8.3
Power-Up Timing and Write Inhibit Threshold
Parameter
Symbol
Spec
Min
Max
Unit
VCC (min) to CS# Low
tVSL (1)
10
Time Delay Before Write Instruction
tPUW (1)
1
10
ms
µs
Write Inhibit Threshold Voltage
VWI (1)
1.0
2.0
V
Note:
1. These parameters are characterized only.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
61
D a t a
S h e e t
Figure 8.1 Power-Up Timing and Voltage Levels
VCC
VCC (max)
Program, Erase, and Write instructions are ignored
CS# must track VCC
VCC (min)
t VSL
Reset
State
Read instructions
allowed
Device is fully
accessible
VWI
t PUW
Time
62
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
8.4
S h e e t
DC Electrical Characteristics
Spec
Parameter
Symbol
Conditions
Unit
Min
Input Capacitance
CIN (1)
Output Capacitance
COUT (1)
Typ
Max
VIN = 0V (1)
6
pF
VOUT = 0V (1)
8
pF
Input Leakage
ILI
±2
µA
I/O Leakage
ILO
±2
µA
Standby Current
(S25FL004K/ S25FL008K)
ICC1
25
50
10
25
CS# = VCC, VIN = GND or VCC
µA
Standby Current (S25FL016K)
Power-down Current
ICC2
CS# = VCC, VIN = GND or VCC
1
5
µA
Deep Power-down Current (S25FL016K)
ICC2
CS# = VCC, VIN = GND or VCC
1
5
µA
Current: Read Data / Dual /Quad 1 MHz
(2)
ICC3
C = 0.1 VCC / 0.9 VCC
SO = Open
4/5/6
6/7.5/9
mA
Current: Read Data / Dual /Quad 33 MHz
(2)
ICC3
C = 0.1 VCC / 0.9 VCC
SO = Open
6/7/8
9/10.5/12
mA
ICC3
C = 0.1 VCC / 0.9 VCC
SO = Open
7/8/9
10/12/13.5
mA
ICC3
C = 0.1 VCC / 0.9 VCC
SO = Open
10/11/12
15/16.5/18
mA
8
12
ICC4
CS# = VCC
10
15
Current: Read Data / Dual Output Read/
Quad Output read 50 MHz (2)
(S25FL004K)
Current: Read Data / Dual /Quad 50 MHz
(2) (S25FL008K/S25FL016K)
Current: Read Data / Dual Output Read/
Quad Output Read 80 MHz (2)
Current: Write Status Register
(S25FL004K/S25FL008K)
Current: Write Status Register
(S25FL016K)
mA
Current Page Program
ICC5
CS# = VCC
20
25
mA
Current Sector/Block Erase
ICC6
CS# = VCC
20
25
mA
Current Chip Erase
ICC7
CS# = VCC
20
25
mA
Input Low Voltage
VIL
VCC x 0.3
V
Input High Voltage
VIH
Output Low Voltage
VOL
IOL = 100 µA
0.2
V
Output High Voltage
VOH
IOH = –100 µA
VCC x 0.7
V
VCC – 0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25°C, VCC = 3V.
2. Checker Board Pattern.
8.5
AC Measurement Conditions
Parameter
Symbol
Load Capacitance
Input Rise and Fall Times
Spec
Min
Max
Unit
CL
30
pF
T R , TF
5
ns
Input Pulse Voltages
VIN
0.2 VCC to 0.8 VCC
V
Input Timing Reference Voltages
IN
0.3 VCC to 0.7 VCC
V
OUT
0.5 VCC to 0.5 VCC
V
Output Timing Reference Voltages
Note:
1. Output High-Z is defined as the point where data out is no longer driven.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
63
D a t a
S h e e t
Figure 8.2 AC Measurement I/O Waveform
Input and Output
Timing Reference Levels
Input Levels
0.8 VCC
0.5 VCC
0.2 VCC
8.6
AC Electrical Characteristics
Table 8.1 AC Electrical Characteristics (Sheet 1 of 2)
Spec
Description
Symbol
Alt
Unit
Min
Clock frequency for all instructions except for Read Data
instruction (03h)
3.0V-3.6V VCC and Industrial Temperature (S25FL004K)
Clock frequency for Single/Dual SPI instructions except
for Read Data instruction (03h)
3.0V-3.6V VCC and Industrial Temperature (S25FL008K)
FR
fC
D.C.
80
FR
fC
D.C.
Clock High, Low Time except Read Data (03h)
(S25FL016K)
fR
D.C.
50
MHz
6
tCLH1, tCLL1 (1)
tCH, tCL
4
ns
tCLH, tCLL (1)
6
tCRLH, tCRLL (1)
8
ns
Clock Rise Time peak to peak
tCLCH (2)
0.1
V/ns
Clock Fall Time peak to peak
tCHCL (2)
0.1
V/ns
5
ns
Clock High, Low Time for Read Data (03h) instruction
CS# Active Setup Time relative to CLK
tSLCH
CS# Not Active Hold Time relative to CLK
tCHSL
Data In Setup Time
tDVCH
tDSU
Data In Hold Time
tCHDX
tDH
CS# Active Hold Time relative to CLK
tCHSH
CS# Not Active Setup Time relative to CLK
tSHCH
CS# Deselect Time (for Array Read -> Array Read)
tSHSL1
CS# Deselect Time (for Erase or Program -> Read
Status Registers)
Volatile Status Register Write Time
Output Disable Time
tCSS
tCSH
5
ns
2
ns
5
ns
5
ns
5
ns
10
ns
50
tSHSL2
ns
tCSH
50
tSHQZ (2)
tDIS
tCLQV1
tV1
Clock Low to Output Valid
(S25FL004K)
7
ns
7
Clock Low to Output Valid 2.7V-3.6V / 3.0V-3.6V
(S25FL008K/S25FL016K)
64
MHz
50
Clock High, Low Time for all instructions except Read
Data (03h) (S25FL004K)
Clock High, Low Time except Read Data (03h)
(S25FL008K)
MHz
80 / 104
Clock frequency for Octal Word Read Quad I/O (E3h)
3.0V-3.6V (S25FL0016K)
Clock frequency for Read Data instruction (03h)
Max
104
Clock frequency for all instructions except Read data
(03h) and Octal Word Read(E3h) 2.7V-3.6V / 3.0V-3.6V
(S25FL0016K)
Clock frequency for all instructions except for Read Data
instruction (03h)
2.7V-3.6V VCC and Industrial Temperature
(S25FL004K/ S25FL008K)
Typ
S25FL004K / S25FL008K / S25FL016K
ns
7/6
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
Table 8.1 AC Electrical Characteristics (Sheet 2 of 2)
Spec
Description
Symbol
Alt
Unit
Min
Typ
Clock Low to Output Valid (for Read ID instructions)
(S25FL004K)
Max
7.5
Clock Low to Output Valid (for Read ID instructions)
2.7V-3.6V / 3.0V-3.6V
(S25FL008K/S25FL016K)
tCLQV2
Output Hold Time
tCLQX
tV2
ns
8.5 / 7.5
tHO
0
ns
HOLD# Active Setup Time relative to CLK
tHLCH
5
ns
HOLD# Active Hold Time relative to CLK
tCHHH
5
ns
HOLD# Not Active Setup Time relative to CLK
tHHCH
5
ns
HOLD# Not Active Hold Time relative to CLK
tCHHL
5
ns
HOLD# to Output Low-Z
tHHQX (2)
tLZ
7
ns
HOLD# to Output High-Z
tHLQZ (2)
tHZ
12
ns
Write Protect Setup Time Before CS# Low
tWHSL (3)
20
Write Protect Hold Time After CS# High
tSHWL (3)
100
CS# High to Power-down Mode
ns
ns
tDP (2)
3
µs
CS# High to Standby Mode without Electronic Signature
Read
tRES1 (2)
3
µs
CS# High to Standby Mode with Electronic Signature
Read
tRES2 (2)
1.8
µs
CS# High to next Instruction after Suspend
tSUS (2)
20
µs
15
ms
50
µs
Write Status Register Time
tW
Byte Program Time (First Byte) (4)
(S25FL004K)
Byte Program Time (First Byte) (4)
(S25FL008K/S25FL016K)
10
20
tBP1
30
Additional Byte Program Time (After First Byte) (4)
tBP2
2.5
12
µs
Page Program Time
tPP
0.7
3
ms
Sector Erase Time (4 kB)
tSE
30
200/400
(5)
ms
Block Erase Time (32 kB)
tBE1
120
800
ms
Block Erase Time (64 kB)
tBE2
150
1,000
ms
1
4
2
6
3
10
Chip Erase Time
(S25FL004K)
Chip Erase Time
(S25FL008K)
tCE
Chip Erase Time
(S25FL016K)
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect bit is set to 1.
4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of
bytes programmed.
5. Max Value tSE with <50k cycles is 200 ms and >50k and <100k cycles is 400 ms.
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
65
D a t a
8.7
S h e e t
Serial Output Timing
Figure 8.3 Serial Output Timing
CS#
t CLH
CLK
t CLQV
t CLQX
t CLQX
t CLQV
t CLL
t SHQZ
LSB Out
SO/SIO*
t QLQH
t QHQL
*SIO is an output only for the fast read dual output instructions (3Bh)
8.8
Serial Input Timing
Figure 8.4 Serial Input Timing
tSHSL
CS#
tCHSL
CLK
SIO
SO
8.9
tSLCH
tDVCH
tCHSH
tSHCH
tCLCH
tCHDX
MSB IN
tCHCL
LSB IN
(High Impedance)
Hold Timing
Figure 8.5 Hold Timing
CS#
t CHHL
t HLCH
t HHCH
CLK
t CHHH
t HLQZ
t HHQX
SO
SIO
HOLD#
66
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
9.
S h e e t
Physical Dimensions
9.1
SOA008 narrow — 8-pin Plastic Small Outline Package (150-mils Body Width)
3
0.20 C
4
A-B
H
D
A
5
SEE
DETAIL B
D
WITH
PLATING
3
4
b1
E
E1
9
E1/2
c
h
c1
E/2
(b)
BASE
METAL
h
0.33
INDEX AREA
(0.25D x 0.75E)
e
SECTION A-A
b
B
9
0.25
M C A-B D
0.10
C
5
02
0.07 R MIN.
H
0.10
A2
A
7
C
C
GAUGE PLANE
A
SEATING PLANE
A1
SEATING PLANE
C
A
01
C
L
L2
0
L1
DETAIL B
NOTES:
PACKAGE
JEDEC
SOA 008 (inches)
MS-012(D)AA
1.
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
SOA 008 (mm)
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
MS-012(D)AA
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
SYMBOL
MIN
MAX
MIN
MAX
A
0.0531
0.0688
1.35
1.75
A1
0.0039
0.0098
0.10
0.25
A2
0.052
0.061
1.32
1.55
b
0.012
0.020
0.31
0.51
b1
0.011
0.019
0.27
0.48
c
0.0067
0.0098
0.17
0.25
c1
0.0067
0.009
0.17
0.23
D
0.193 BSC
4.90 BSC
E
0.236 BSC
6.00 BSC
E1
e
L
0.1535 BSC
.050 BSC
0.0161
0.035
3.90 BSC
1.27 BSC
0.41
.041 REF
1.04 REF
L2
.010 BSC
0.25 BSC
8
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
8
h
0.10
0.196
0.25
θ
0˚
8˚
0˚
8˚
θ1
5˚
15˚
5˚
15˚
θ2
4.
0.89
L1
N
.
0˚
0.50
0˚
3528 \ 16-038.03 \ 11.02.05
July 14, 2011 S25FL004K-016K_00_02
S25FL004K / S25FL008K / S25FL016K
67
D a t a
9.2
S h e e t
SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width)
NOTES:
PACKAGE
SOC 008 (inches)
SOC 008 (mm)
JEDEC
SYMBOL
MIN
MAX
MIN
A
0.069
0.085
1.753
2.159
0.002
0.0098
0.051
0.249
A2
0.067
0.075
1.70
1.91
b
0.014
0.019
0.356
0.483
b1
0.013
0.018
0.330
0.457
c
0.0075
0.0095
0.191
0.241
c1
0.006
0.008
0.152
0.203
D
0.208 BSC
5.283 BSC
E
0.315 BSC
8.001 BSC
e
L
0.208 BSC
.050 BSC
0.020
0.030
5.283 BSC
1.27 BSC
0.508
.049 REF
1.25 REF
L2
.010 BSC
0.25 BSC
8
0˚
8˚
0˚
8˚
θ1
5˚
15˚
5˚
15˚
0˚
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
8
θ
θ2
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
0.762
L1
N
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2.
MAX
A1
E1
1.
0˚
3602 \ 16-038.03 \ 9.1.6
68
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011
D a t a
S h e e t
10. Revision History
Section
Description
Revision 01 (June 10, 2011)
Initial release. Combined S25FL004K_00_02, S25FL008K_00_02, and S25FL016K_00_02.
Revision 02 (July 14, 2011)
Global
July 14, 2011 S25FL004K-016K_00_02
Promoted data sheet designation from Preliminary to Full Production
S25FL004K / S25FL008K / S25FL016K
69
D a t a
S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
70
S25FL004K / S25FL008K / S25FL016K
S25FL004K-016K_00_02 July 14, 2011