CDB53L30
Evaluation Board for the CS53L30
Features
Description
• Analog or digital Inputs
The CDB53L30 board is a dedicated platform for testing
and evaluating the CS53L30, a low-power, quad-channel
microphone ADC with TDM output.
— Analog microphone or line inputs via TRS 1/8” jacks
— Digital microphone inputs via stake headers
To allow comprehensive testing of CS53L30 features and
performance, extensive software-configurable options are
available on the CDB53L30.
• Two CS53L30 devices support up to eight channels of
phase-aligned audio
• Onboard master clock generator
Software options, such as register settings for the
CS53L30, are configured with the FlexGUI software, which
communicates with the CDB53L30 via USB from a
Windows®-compatible computer. In addition, digital I/O
headers on the CDB53L30 allow external control signals
(from a host processor, for example) to configure and
interface with the CS53L30 directly without the use of
FlexGUI.
• S/PDIF transmitter interface via RCA and optical jacks
• External digital I/O via stake headers
— Serial audio port I/O
— Control signal I/O
— External I²C™ control port I/O
• Flexible power-supply configuration
The CDB53L30 also serves as the component and layout
reference for the CS53L30.
— USB or external power supply
• FlexGUI software control
Ordering information
— Windows® compatible
CDB53L30
— Predefined and user-configurable scripts
+5V, GND
(Binding Post)
USB
VBUS
Evaluation Board
VA, VP
(Binding Post)
Regulators
Power Source Selection (Headers)
MicroController
Control
Current Sense Resistors for Power Measurement (Bypassable)
I2C and Control I/O
(Header)
Control
Power
MCLK
Generator
MCLK
Serial Audio
CS53L30
#1
S/PDIF Out
(Optical)
CS8406
Power
Serial Audio I/O
(Header)
Control
CS53L30
#2
Mux
S/PDIF Out
(RCA)
Digital Mic In
(Header)
http://www.cirrus.com
Analog In
(1/8" TRS,
Header)
Copyright Cirrus Logic, Inc. 2013
(All Rights Reserved)
Digital Mic In
(Header)
Analog In
(1/8" TRS,
Header)
DS963DB2
JUN '13
CDB53L30
Table of Contents
1 CDB53L30 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Power Supply Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Digital Mic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Serial Audio I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 S/PDIF Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Synchronization I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Control Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Layout Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Quick-Start Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
3
3
3
4
4
4
5
5
5
6
3 System Connections and Jumper Settings . . . . . . . . . . . . . . . 7
4 Software Control Using FlexGUI . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Installation and First-Time Setup . . . . . . . . . . . . . . . . . . . . . 10
4.2 Working with Register Settings . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Using the FlexGUI Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Register Maps Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Performance Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DS963DB2
CDB53L30
1 CDB53L30 System Overview
1 CDB53L30 System Overview
The CDB53L30 evaluation board is a convenient platform for evaluating the CS53L30 low-power, quad-channel
microphone ADC with TDM output. It supports multiple power supply and signal I/O configurations, including the option to
connect directly to the CS53L30 from an external system such as a host processor (while bypassing the onboard control
circuitry). The CDB53L30 has two CS53L30 devices, providing the ability to evaluate the multichip synchronization
protocol. To evaluate the synchronization protocol using four devices, two CDB53L30s can be linked using the SYNC I/O
header. The CDB53L30 also serves as the component and layout reference for the CS53L30.
The following subsections describe the features of the CDB53L30 evaluation board in detail.
1.1 Power Supply Circuitry
The CDB53L30 requires a +5-V power source, supplied either by a +5-V external DC power supply connected to the +5V_
EXT and GND binding posts, or by the VBUS connection from a powered USB port. The +5-V source is selectable via
jumper pin block J31.
Low-dropout regulators (LDOs) step down the +5-V supply to provide clean and stable +3.3-, +3.6-, and +1.8-V rails to all
the onboard circuitry and the CS53L30. Jumper pin block J2 selects the VA power supply source for the CS53L30 supply
pins (either the VA_EXT binding post or the onboard +1.8-V LDO). Jumper pin block J13 selects the VP power supply
source for the CS53L30 supply pins (either the VP_EXT binding post or the onboard +3.6-V LDO).
1.2 Analog Inputs
The CDB53L30 has eight analog input connectors, four per CS53L30 device. The four 1/8” TRS jacks labeled “1.AIN1,"
“1.AIN2," “1.AIN3," and “1.AIN4” are connected to analog inputs 1–4, respectively, of device #1. The four 1/8” TRS jacks
labeled “2.AIN1," “2.AIN2," “2.AIN3," and “2.AIN4” are connected to analog inputs 1–4, respectively, of device #2.
For fully differential input sources, no jumper should be placed at the position marked “IN–” at the Sleeve/AIN– jumper pin
block (J36 on channel 1.AIN1). For single-ended or pseudodifferential input sources, AIN– should be shunted to ground
by placing a jumper at the “IN–” position (Pins 1 and 2).
In addition to the 1/8” TRS jacks, the input source may also be connected directly to the input header (J6 on channel
1.AIN1). The AIN+ and AIN– pins are connected directly to the “tip” and “ring” conductors of the 1/8” TRS jack,
respectively.
By factory default, the sleeve conductor of the TRS cable is shunted to ground by the jumper at the position labeled
“Sleeve”. When using a fully differential input source, it may be desirable for noise reasons to float the sleeve connection
by removing the “Sleeve” jumper. In some cases, this can reduce noise induced by ground loops.
For microphone applications, the CS53L30 microphone bias signals are available at the input headers. Bias can also be
connected to the AIN+ inputs through 1.8-k series bias resistors according to the instructions below:
1. For two-pin microphones (bias connected to AIN+ through a bias resistor): the “Bias to AIN+” jumper should be
shunted and the “Rbias SHORT” jumper should be open.
2. For three-pin microphones (bias not connected to AIN+): the “Bias to AIN+” jumper should be open and the “Rbias
SHORT” jumper should be shunted.
DC blocking capacitors are located between the AIN+/AIN– input connectors and the CS53L30 IN± input pins. These caps
are 0.1 F, providing a typical –3-dB corner frequency of 31.8 Hz when the microphone preamplifier is bypassed (50 k
input impedance) or 1.6 Hz when the the preamplifier is enabled (1-Minput impedance).
1.3 Digital Mic Inputs
The CS53L30 can be configured to accept digital microphone inputs on channels 1 and 3. The digital microphone signals
should be connected directly to the input header (J6 on input 1.AIN1) as described in Table 1-1.
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CDB53L30
1.4 Serial Audio I/O
Table 1-1. Digital Microphone Connections to the Input Header
Header Pin Direction
Description
1.SCLK1
Output Digital mic 1 serial clock from CS53L30 #1
1.SCLK2
Output Digital mic 2 serial clock from CS53L30 #1
2.SCLK1
Output Digital mic 1 serial clock from CS53L30 #2
2.SCLK2
Output Digital mic 2 serial clock from CS53L30 #2
1.DATA1
Input
Digital mic 1 data to CS53L30 #1
1.DATA2
Input
Digital mic 2 data to CS53L30 #1
2.DATA1
Input
Digital mic 1 data to CS53L30 #2
2.DATA2
Input
Digital mic 2 data to CS53L30 #2
1.BIAS1
Output Mic bias 1 from CS53L30 #1 (To supply bias directly to the pin with no series bias
resistor, the “Rbias SHORT” pin jumper should be shunted)
1.BIAS3
Output Mic bias 3 from CS53L30 #1 (To supply bias directly to the pin with no series bias
resistor, the “Rbias SHORT” pin jumper should be shunted)
2.BIAS1
Output Mic bias 1 from CS53L30 #2 (To supply bias directly to the pin with no series bias
resistor, the “Rbias SHORT” pin jumper should be shunted)
2.BIAS3
Output Mic bias 3 from CS53L30 #2 (To supply bias directly to the pin with no series bias
resistor, the “Rbias SHORT” pin jumper should be shunted)
1.4 Serial Audio I/O
Header J29 provides an interface for the I2S and TDM serial audio clocks and data. The header signals are described in
Table 1-2. MCLK routing is controlled by the settings on the “Board Config” tab in the FlexGUI. The direction of the LRCK/
FSYNC and SCLK pins is configured by the “Serial Header Direction” control on the “Board Config” tab. When configured
as Master, LRCK/FSYNC and SCLK are outputs from the CDB53L30. When configured as Slave, LRCK/FSYNC and
SCLK are inputs to the CDB53L30. The logic level for all serial I/O is +1.8 V.
Table 1-2. Serial Header Signal Descriptions
Header Pin
Direction
Description
MCLK IN
Input
Master clock input
MCLK OUT
Output
Master clock output
SCLK
Input/Output I2S or TDM bit clock
LRCK/FSYNC Input/Output I2S left/right clock or TDM frame sync
1.ASP_SDOUT1
Output
ASP_SDOUT1 I2S or TDM data from CS53L30 #1;
In I2S mode, left channel corresponds to 1.AIN1, right channel corresponds to 1.AIN2.
In TDM mode, channel slot location is configurable.
1.ASP_SDOUT2
Output
ASP_SDOUT2 I2S data from CS53L30 #1;
Left channel corresponds to 1.AIN3, right channel corresponds to 1.AIN4.
2.ASP_SDOUT1
Output
ASP_SDOUT1 I2S or TDM data from CS53L30 #2;
In I2S mode, left channel corresponds to 2.AIN1, right channel corresponds to 2.AIN2.
In TDM mode, channel slot location is configurable.
2.ASP_SDOUT2
Output
ASP_SDOUT2 I2S data from CS53L30 #2;
Left channel corresponds to 2.AIN3, right channel corresponds to 2.AIN4.
1.5 S/PDIF Transmitter
The CS8406 S/PDIF transmitter on the CDB53L30 provides a two-channel digital output simultaneously to both the RCA
coaxial connector (J35) and the optical output connector (OPT2). To use the S/PDIF transmitter, the CS53L30 must be
configured for I2S mode, and the CS53L30 MCLK/LRCK ratio must correspond to one of the four ratios supported by the
CS8406: 128x, 256x, 384x, or 512x. Only one SDOUT signal may be chosen for output at any time. The CS8406 clock
ratio and desired SDOUT signal are selected on the “Board Config” tab of the FlexGUI.
1.6 Master Clock
The CDB53L30 includes a fixed-frequency crystal oscillator and CS2300 programmable PLL, facilitating the generation of
an onboard MCLK. The MCLK frequency is configured on the “Board Config” tab of the FlexGUI.
4
DS963DB2
CDB53L30
1.7 Synchronization I/O
The Serial Audio I/O header J29 provides a MCLK input pin and MCLK output pin. The MCLK IN pin can be used to provide
an externally generated MCLK to the board. The MCLK OUT pin provides either a buffered version of the onboard
generated MCLK or a buffered version of the MCLK IN signal. By providing a buffered version of the MCLK IN signal, the
MCLK OUT pin may be used for daisy chaining an additional CDB53L30. This is useful when the external clock source
does not have sufficient output drive capability to support multiple parallel loads. To enable the various MCLK routing
options, use the MCLK buffer control drop-down boxes in the “Board Config” tab in the FlexGUI.
1.7 Synchronization I/O
For applications requiring more than two CS53L30 devices, two CDB53L30 boards may be linked using the Sync I/O
header J33. This will allow up to four CS53L30 devices to be synchronized using the multichip synchronization protocol.
The direction of the sync signal is configured using jumper pin block J37. For more information on enabling the
synchronization protocol, see the CS53L30 data sheet.
1.8 Control Port Interface
The Cirrus Logic FlexGUI software application (downloadable from http://www.cirrus.com/msasoftware) provides users an
easy and intuitive way to configure the CDB53L30. A Windows®-compatible PC with USB connectivity is required to run
FlexGUI.
The CDB53L30’s onboard microcontroller handles the USB communication with FlexGUI and the I2C control port interface
of the CS53L30. The control port interface and the control I/O signals (INT, RST, and MUTE) are routed through jumper
pin block J4. When the pin columns marked “FlexGUI CNTL” are shunted, the microcontroller handles all communication
between the FlexGUI application and the CS53L30. To interface to an external system, the shunts on J4 should be
removed and the external signals should be connected to the pin columns marked “EXT SYS” (note the GND pins on the
right hand side of the header).
The INT, RST, and MUTE control signals for the two CS53L30 devices may be ganged together using the “CONTROL
SHORTS” jumper pin block J34. This allows both devices to share a single set of control signals. To enable ganging of a
control, apply a shunt to the desired signal on J34. When ganging a control, remove one of the associated FlexGUI control
jumpers from J4 to prevent contention between the two ganged control signals from the microcontroller.
1.9 Layout Reference
The CDB53L30 utilizes a six-layer PCB that allows for optimal trace and power routing to the CS53L30 devices and
surrounding circuitry. Local decoupling capacitors for the CS53L30 are placed as close as possible to the device. The
CDB53L30 uses a topside-only component placement without compromise to placement of critical components, but a
double-sided placement is also feasible. Ground fill is used extensively on the component layer to isolate critical nets
where possible.
5
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CDB53L30
2 Quick-Start Guide
2 Quick-Start Guide
This section describes a basic setup procedure for the CDB53L30. After completing the steps in Fig. 2-1, the CDB53L30
will be configured to accept eight single-ended or differential analog line inputs and will output four two-channel I2S
streams at a sample rate of 48 kHz.
5
1
2
3
Return
Returnallalljumpers
jumperstotodefault
the
factory factory
settings.
See See
default
settings.
Table
3-1.3-1.
Table3-2
3-2and
andFig.
Figure
InstallInstall
the FlexGUI
software.
the FlexGUI
See
SectionSee
4.1.Section 4.1.
software.
Connect a +5 V power
supply to the +5V_EXT
and GND binding posts .
Start the FlexGUI software. Using
the “Quick -Setup” drop -down list on
the “Board Config” tab , restore the
factory register configuration called
“2. Analog in – I2S – 48k FS –
12.288M MCLK – Master mode” .
4
Connect a USB cable
from a Windowscompatible PC .
8
Connect
Connect aa serial
serial audio
audio
analyzer
to the
the Serial
Serial
analyzer to
Header.
Header . The
The header
header
signals
described
signals are
are described
inTable
in Table2-1.
2-1.
9
Optional : Connect
an audio analyzer to
the S/PDIF RCA or
optical output . The
stereo pair at these
outputs corresponds
to analog input pair
1.AIN1 and 1.AIN2.
6
7
Connect differential or single ended signals to any of the
eight 1/8" input jacks. Fullscale input corresponds to a
differential voltage of 1.48 Vpp.
When using a single -ended
source, shunt IN– to ground by
placing a jumper at the “IN –“
position (Pins 1 and 2) on the
Sleeve/IN- jumper pin block .
Figure 2-1. CDB53L30 Factory Default Jumper Settings
Table 2-1. Quick-Start Serial Header Signal Descriptions
Header Pin
MCLK IN
MCLK OUT
SCLK
LRCK/FSYNC
1.ASP_SDOUT1
6
Direction
N/A
Output
Output
Output
Output
Frequency
N/A
12.288 MHz
3.072 MHz
48 kHz
N/A
Description
Not used
Master clock
I2S bit clock
I2S left/right clock
ASP_SDOUT1 I2S data from CS53L30 #1;
Left channel corresponds to 1.AIN1, right channel corresponds to 1.AIN2
DS963DB2
CDB53L30
3 System Connections and Jumper Settings
Table 2-1. Quick-Start Serial Header Signal Descriptions (Cont.)
Header Pin
1.ASP_SDOUT2
Direction
Output
2.ASP_SDOUT1
Output
2.ASP_SDOUT2
Output
Frequency
Description
N/A
ASP_SDOUT2 I2S data from CS53L30 #1;
Left channel corresponds to 1.AIN3, right channel corresponds to 1.AIN4
N/A
ASP_SDOUT1 I2S data from CS53L30 #2;
Left channel corresponds to 2.AIN1, right channel corresponds to 2.AIN2
N/A
ASP_SDOUT2 I2S data from CS53L30 #2;
Left channel corresponds to 2.AIN3, right channel corresponds to 2.AIN4
3 System Connections and Jumper Settings
All power and signal I/O connections are listed in Table 3-1. Jumper settings are described in Table 3-2. LED indicator
states are described in Table 3-3. Factory default jumper settings are shown in Fig. 3-1.
Table 3-1. External System Connections
Reference Designator Connection Input/Output
Description
J83
+5V_EXT
Input
+5-V external power supply
J89
GND
Input
Board ground
J9
VA_EXT
Input
CS53L30 VA external supply
J14
VP_EXT
Input
CS53L30 VP external supply
J5
UC FLEX C2
Input
Microcontroller programming header
J94
USB
Input/Output USB connection
J29
SERIAL
Input/Output CS53L30 Audio Serial Port (MCLK IN, MCLK OUT, LRCK/FSYNC, SCLK, ASP_
HEADER
SDOUT1, ASP_SDOUT2)
J4
CONTROL Input/Output CS53L30 control port connections (SDA, SCL, INT, RST, MUTE)
HEADER
• By default, shunts connect the columns marked “FlexGUI CNTL (JUMPER)”. This
connects the onboard microcontroller to the control port of the CS53L30.
• To use external control signals, remove shunts and connect the external controls to the
columns marked “EXT SYS (CABLE)”. Notice the ground connections on Column 3.
J35
S/PDIF OUT
Output
Coaxial S/PDIF digital output
OPT2
S/PDIF OUT
Output
Optical S/PDIF digital output
J53
1.AIN1
Input
Analog mic/line TRS input 1 for CS53L30 #1
J12
1.AIN2
Input
Analog mic/line TRS input 2 for CS53L30 #1
J16
1.AIN3
Input
Analog mic/line TRS input 3 for CS53L30 #1
J20
1.AIN4
Input
Analog mic/line TRS input 4 for CS53L30 #1
J7
2.AIN1
Input
Analog mic/line TRS input 1 for CS53L30 #2
J23
2.AIN2
Input
Analog mic/line TRS input 2 for CS53L30 #2
J26
2.AIN3
Input
Analog mic/line TRS input 3 for CS53L30 #2
J30
2.AIN4
Input
Analog mic/line TRS input 4 for CS53L30 #2
J6
Input header
Input
Analog input 1 and digital mic interface 1 for CS53L30 #1
J17
Input header
Input
Analog input 2 for CS53L30 #1
J19
Input header
Input
Analog input 3 and digital mic interface 2 for CS53L30 #1
J22
Input header
Input
Analog input 4 for CS53L30 #1
J11
Input header
Input
Analog input 1 and digital mic interface 1 for CS53L30 #2
J25
Input header
Input
Analog input 2 for CS53L30 #2
J28
Input header
Input
Analog input 3 and digital mic interface 2 for CS53L30 #2
J32
Input header
Input
Analog input 4 for CS53L30 #2
J33
SYNC I/O Input/Output Synchronization Input/Output for additional CDB53L30
.
Table 3-2. CDB53L30 Jumper Settings
Jumper Pin Block Connection
Purpose
J31
+5 V
Select +5 V main
supply
J2
VA
Select CS53L30 VA
supply source
J13
VP
Select CS53L30 VP
supply source
7
Position
+5V_EXT 1
VBUS
VA EXT
+1.8 V 1
VP_EXT
+3.6 V 1
Function Selected
+5-V supply source from J83
+5-V supply source from USB VBUS
CS53L30 VA supply from J9
CS53L30 VA supply from +1.8 V derived from LDO
CDB53L30 VP supply from J14
CDB53L30 VP supply from +3.6 V derived from LDO
DS963DB2
CDB53L30
3 System Connections and Jumper Settings
Table 3-2. CDB53L30 Jumper Settings (Cont.)
Jumper Pin Block Connection
Purpose
J34
CONTROL Gang control signals of
SHORTS CS53L30 #1 and
CS53L30 #2
J39, J44, J45, J86,
Rbias
Shunt across the
J73, J78, J51, J46
SHORT
1.8 k bias resistor
J38, J43, J42, J85, Bias to AIN+ Connect mic bias to
J72, J77, J50, J41
noninverting input
J36, J3, J15, J18, IN– to GND Connect inverting input
J10, J21, J24, J27
to ground
J36, J3, J15, J18, SLEEVE to Connect TRS sleeve
J10, J21, J24, J27
GND
conductor to ground
J37
SYNC
Configure direction of
DIRECTION synchronization signal
J1
VA I-SENSE CS53L30 VA current
measurement
J8
1. Indicates
VP
I-SENSE
CS53L30 VP current
measurement
Position
Shunted
Open 1
Shunted
Open 1
Shunted
Open 1
Shunted
Open 1
Shunted 1
Open
SYNC IN
SYNC OUT1
Shunted 1
Open
Shunted 1
Open
Function Selected
Control signals are tied.
Control signals are independent.
1.8-k bias resistor is shunted (for three-wire mic connection).
1.8-k bias resistor is not shunted (for two-wire mic connection).
Mic bias tied to AIN+.
Mic bias not tied to AIN+.
IN– tied to ground (for pseudodifferential input).
IN– not tied to ground (for true differential input).
Sleeve tied to ground.
Sleeve floating.
Sync signal is input (from another CDB53L30).
Sync signal is output (to another CDB53L30).
1- current measurement resistor is shorted.
1- current measurement resistor is in series with CS53L30 VA,
allowing direct measurement of VA supply current at J1.
1- current measurement resistor is shorted.
1- current measurement resistor is in series with CS53L30 VP,
allowing direct measurement of VP supply current at J8.
default factory settings.
Table 3-3. LED Indicators
LED
D4
8
Indication
USB present
Status
On
Off
Function
Indicates there is a USB connection to the CDB53L30.
Indicates there is not a USB connection to the CDB53L30.
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CDB53L30
3 System Connections and Jumper Settings
Figure 3-1. CDB53L30 Factory Default Jumper Settings
9
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CDB53L30
4 Software Control Using FlexGUI
4 Software Control Using FlexGUI
The Cirrus Logic FlexGUI application is a graphical user interface that allows users to easily configure software modifiable
options on the CDB53L30, such as the register settings of the CS53L30 and the CS8046 S/PDIF transmitter.
4.1 Installation and First-Time Setup
To set up FlexGUI for use with the CDB53L30, follow these steps:
1. Download the latest version of the FlexGUI control software from www.cirrus.com/msasoftware. Follow the
installation instructions on the download page.
2. Connect the CDB53L30 to the host PC using a USB cable.
3. Apply power to the CDB53L30.
4. Launch FlexGUI. Once the GUI is launched successfully, all registers are set to their default reset states. To start
evaluating the CS53L30 immediately using one of several factory preset configurations, load the predefined
register settings using the Quick Setup drop-down box on the “Board Config” tab.
4.2 Working with Register Settings
Register settings can be restored automatically using factory or user-defined script files. Registers can be modified using
the high-level interface controls, or they may be edited directly in the Register Maps tab of the FlexGUI.
4.2.1
Modifying Individual Register Settings
There are two ways to modify individual register settings:
•
Using the high-level graphical interface, which features intuitive GUI elements such as sliders, check boxes, and
drop-down menus. See Section 4.3 for details on using the high-level interface.
•
Using the low-level Register Maps tab, which displays the entire user configurable register space for each device
on the CDB53L30 in table form. The Register Maps tab allows the user to modify entire registers or individual
register bits. See Section 4.4 for details on the register map.
4.2.2
Save or Restore Register Settings
FlexGUI allows saving the current state of all register settings to a file, which can easily be restored later.
Figure 4-1. Save Register Settings
Figure 4-2. Restore Register Settings
To save the current register settings, click on the File menu, then click “Save Board Registers” (Fig. 4-1). Enter a suitable
file name and click “Save.”
To restore predefined/saved register settings, click on the File menu, then click “Restore Board Registers” (Fig. 4-2).
Choose the desired register setting and click “Open.”
To restore one of several standard configurations predefined at the factory, use the Quick Setup drop-down box on the
“Board Config” tab, or use the Restore Board Registers... command to load any of the configurations starting with
“FACTORY--” in the file name. The file names are meant to be self-explanatory. For example, the script called
“FACTORY--analog_48k_12.288M_master_I2S_dual.fgs” configures the board as I2S master with a 48k sample rate and
12.288 MHz MCLK, using analog input type.
10
DS963DB2
CDB53L30
4.3 Using the FlexGUI Tabs
The factory scripts are written with special consideration to proper sequencing of device settings, for example, enabling a
device’s power down mode before changing its MCLK settings. Register settings saved using the method described in this
section DO NOT include sequencing and may result in unexpected behavior when restored in the FlexGUI.
4.3 Using the FlexGUI Tabs
The FlexGUI features a series of tabs which represent the high- and low-level controls, grouped together according to
function. Fig. 4-3 shows the tabs in the FlexGUI interface.
.
Figure 4-3. FlexGUI Tabs
•
Board Config—Board controls for configuring the MCLK source, S/PDIF transmitter, serial header, and CS53L30
mute signals
•
CS53L30-1 Config, CS53L30-2 Config—Controls for configuring the overall operation of the CS53L30
•
CS53L30-1 ADC, CS53L30-2 ADC—Controls for configuring ADC functionality of the CS53L30 (volume, noise
gate, high-pass filter, etc.)
•
CS53L30-1 TDM, CS53L30-2 TDM—Controls for configuring TDM mode of the CS53L30
•
Register Maps—Allows direct register access to all the devices on the CDB53L30
The subsequent sections, Section 4.3.1 through Section 4.3.4, describe each tab in detail.
11
DS963DB2
CDB53L30
4.3 Using the FlexGUI Tabs
4.3.1
Board Config Tab
The “Board Config” tab contains the controls for configuring the MCLK source, S/PDIF transmitter, serial header, and
CS53L30 mute signals. The individual functions of this tab are described below.
•
Quick Setup—Drop-down box for selecting a factory preset register configuration.
•
MCLK—Settings for onboard MCLK frequency and MCLK routing.
•
S/PDIF Transmitter—Settings for the CS8406 S/PDIF transmitter. See Section 1.5 for more information.
•
Mute Control—Configures the state of the microcontroller I/O pins which drive the CS53L30 MUTE inputs. To
enable these controls, jumper pin block J4 must have the corresponding “FlexGUI CNTL” jumpers placed.
•
Serial Header Direction—Configures the SCLK and LRCK/FSYNC signal direction for the serial audio header, J29.
When configured as Master, SCLK and LRCK/FSYNC are outputs from the CDB53L30. When configured as Slave,
SCLK and LRCK/FSYNC are inputs to the CDB53L30.
•
Device and Revision I.D.—Displays the CS53L30 revision information.
•
Refresh—Reads all registers in all devices and updates the values in the FlexGUI.
•
Reset CS53L30-1—Sends a reset pulse to CS53L30 #1.
•
Reset CS53L30-2—Sends a reset pulse to CS53L30 #2.
Figure 4-4. The “Board Config” Tab
12
DS963DB2
CDB53L30
4.3 Using the FlexGUI Tabs
4.3.2
CS53L30 Config Tab
The “CS53L30-1 Config” and “CS53L30-2 Config” tabs contain the controls for configuring the CS53L30 power down state,
serial port settings, DMIC, mic bias, input pin bias, MUTE pin power down behavior, and multichip synchronization.
•
Power—Configures the power down controls and supply settings.
•
MCLK—Controls for MCLK configuration.
•
ASP—Settings for Audio Serial Port configuration.
•
DMIC—Settings for digital mic configuration.
•
Multichip Sync—Enables the multichip synchronization protocol (see the CS53L30 data sheet for details on using
the sync protocol).
•
Mic Bias—Power down and output voltage controls for the mic bias outputs.
•
MUTE—Configures the polarity of the MUTE input pin and the associated power down states which are active while
MUTE is asserted.
•
Input Pin Bias—Configures the bias for each input pin.
•
Refresh—Reads all registers in all devices and updates the values in the FlexGUI.
•
Reset CS53L30-1—Sends a reset pulse to CS53L30 #1.
•
Reset CS53L30-2—Sends a reset pulse to CS53L30 #2.
Figure 4-5. The “CS53L30 Config” Tab
13
DS963DB2
CDB53L30
4.3 Using the FlexGUI Tabs
4.3.3
CS53L30 ADC Tab
The “CS53L30-1 ADC” and “CS53L30-12 ADC” tabs contain the controls for the ADC settings, including notch filter enable,
high-pass filter configuration, noise gating, volume controls, and input type. The controls on the left correspond to ADC1,
and the controls on the right correspond to ADC2.
•
Disable digital notch filter—Disables the digital notch filter (applies to both channels of the ADC).
•
High-Pass Filter—Controls for the high-pass filter (applies to both channels of the ADC).
•
Noise Gate—Controls for the noise gate.
•
Channel volume controls—Controls for mic preamp gain, PGA volume, digital volume, +20 dB digital boost, and
signal inversion (Channel A and Channel B have independent controls).
•
Input channel type—Configures the CS53L30 for either analog or digital inputs (applies to all input channels).
•
Enable soft ramp on all digital volume changes—Enables an incremental ramp on all digital volume changes
(applies to all input channels).
•
Refresh—Reads all registers in all devices and updates the values in the FlexGUI.
•
Reset CS53L30-1—Sends a reset pulse to CS53L30 #1.
•
Reset CS53L30-2—Sends a reset pulse to CS53L30 #2.
Figure 4-6. The “CS53L30 ADC” Tab
14
DS963DB2
CDB53L30
4.3 Using the FlexGUI Tabs
4.3.4
CS53L30 TDM Tab
The “CS53L30-1 TDM” and “CS53L30-2 TDM” tabs contain the controls for configuring the CS53L30 TDM output. These
controls apply only when the ASP Mode is configured for TDM on the “CS53L30 Config” tab.
•
Shift TDM frame 1/2 SCLK left—Configures the start offset of TDM data after a rising edge of LRCK/FSYNC.
•
LRCK Pulse Width—Configures the LRCK/FSYNC high time in TDM mode. The pulse width can be fixed to 50%
duty cycle or configured for any number of SCLK cycles. The high-level GUI allows the user to select between 1
and 8 SCLK cycles as the programmable high time. To configure the CS53L30 for a programmable high time of
greater than 8 SCLK cycles, the user should write directly to the LRCK_TPWH field in registers 0x1B and 0x1C in
the appropriate CS53L30 register tab.
•
TDM Channel Configuration—Enables TDM output from each of the four ADC channels and configures the
channel’s starting TDM slot location.
•
TDM Slot Enable—Determines into which of the 48 available TDM time slots the CS53L30 can load data. During
time slots which are not enabled, the ASP_SDOUT1 output pin is Hi-Z.
•
Refresh—Reads all registers in all devices and updates the values in the FlexGUI.
•
Reset CS53L30-1—Sends a reset pulse to CS53L30 #1.
•
Reset CS53L30-2—Sends a reset pulse to CS53L30 #2.
Figure 4-7. The “CS53L30 TDM” Tab
15
DS963DB2
CDB53L30
4.4 Register Maps Tab
4.4 Register Maps Tab
The “Register Maps” tab shows the entire user configurable register space for all programmable devices on the
CDB53L30. It is especially useful for reading/writing a device’s register settings directly, one register at a time. For
example, in Fig. 4-8 below, the value for register 0x10 is 0x2F. To modify register 0x10’s value, first navigate to it by
locating the cell at the intersection of row “10” and column “00.” Click on the cell and simply type the desired hexadecimal
value for that register, then press the return key (Enter) on the keyboard.
To modify one bit of a register at a time, navigate to the desired register cell, click it, then click on the applicable bits shown
in the lower part of the register map page to toggle them.
Other useful controls:
•
Reset All—Sends a reset pulse to all devices on the CDB53L30.
•
Reset Device—Sends a reset pulse to the device currently in view in the register map.
•
Released Reset—Holds/releases the device currently in view in the register map in/from reset.
•
Update Register—Refreshes the current selected register value.
•
Update Device—Refreshes all register values of the device currently in view in the register map.
Figure 4-8. The “Register Maps” Tab
16
DS963DB2
CDB53L30
5 Performance Plots
5 Performance Plots
Test conditions (unless otherwise specified): FSext = 48 kHz; MCLKext = 12.2880 MHz; preamp setting: 0 dB (bypassed);
PGA setting: 0 dB; high-pass filter enabled, ADCx_HPF_CF = 00; notch filter disabled; noise gate disabled; MCLK
autoscale enabled; VA = 1.8 V, VP = 3.6 V. THD+N measurement bandwidth = 10 Hz to FSext/2, no weighting. Unless
otherwise specified, the performance data is representative of all channels on both CS53L30 devices.
G
%
)
6
G
%
)
6
N
N
N
N N
+]
G
%
)
6
N
N
N
N N
+]
Figure 5-3. Output FFT, Preamp Setting: +10 dB,
PGA Setting: 0 dB, 1 kHz, –1 dBFS
17
N N
N
N
Figure 5-2. Output FFT, Preamp Setting: 0 dB,
PGA Setting: +12 dB, 1 kHz, –1 dBFS
N
+]
Figure 5-1. Output FFT, Preamp Setting: 0 dB,
PGA Setting: 0 dB, 1 kHz, –1 dBFS
G
%
)
6
N
N
N
N N
+]
Figure 5-4. Output FFT, Preamp Setting: +10 dB,
PGA Setting: +12 dB, 1 kHz, –1 dBFS
DS963DB2
CDB53L30
5 Performance Plots
G
%
)
6
G
%
)
6
N
N
N
N N
+]
G
%
)
6
N
N
N
N N
Figure 5-7. Output FFT, 1 kHz, –60 dBFS
Note: The low-frequency roll-off
is due to the corner frequency set
by the DC blocking cap (0.1 F)
and the input impedance (50 k
when the preamp setting is 0 dB).
N N
7
G
%
)
6
Note: The low-frequency roll-off
is due to the corner frequency set
by the DC blocking cap (0.1 F)
and the input impedance (50 k
when the preamp setting is 0 dB).
N
N
N
N N
+]
Figure 5-9. Frequency Response, Notch Filter Disabled,
Preamp Bypassed (0 dB), –1 dBFS
18
N
N
7
N
Figure 5-8. Output FFT, No Input
+]
+]
G
%
)
6
N N
N
N
Figure 5-6. Output FFT, Preamp Setting: +20 dB,
PGA Setting: +12 dB, 1 kHz, –1 dBFS
N
+]
Figure 5-5. Output FFT, Preamp Setting: +20 dB,
PGA Setting: 0 dB, 1 kHz, –1 dBFS
G
%
)
6
N
N
N
N N
+]
Figure 5-10. Frequency Response, Notch Filter Enabled,
Preamp Bypassed (0 dB), –1 dBFS
DS963DB2
CDB53L30
5 Performance Plots
7
G
%
)
6
G
%
)
6
7
N
N
N
N N
N
Figure 5-11. Frequency Response, Notch Filter Disabled,
Preamp Enabled (+10 or +20 dB), –1 dBFS
N N
7
7
G
%
)
6
Note: The low-frequency roll-off
is due to the corner frequency set
by the DC blocking cap (0.1 F)
and the input impedance (50 k
when the preamp setting is 0 dB).
Note: The low-frequency roll-off
is due to the corner frequency set
by the DC blocking cap (0.1 F)
and the input impedance (50 k
when the preamp setting is 0 dB).
N
Figure 5-12. Frequency Response, Notch Filter Enabled,
Preamp Enabled (+10 or +20 dB), –1 dBFS
G
%
)
6
N
+]
+]
N
N
N N
N
N
N N
+]
+]
Figure 5-13. Frequency Response, FSext = 8 kHz, Notch Filter Figure 5-14. Frequency Response, FSext = 8 kHz, Notch Filter
Disabled, Preamp Bypassed (0 dB), –1 dBFS
Enabled, Preamp Bypassed (0 dB), –1 dBFS
7
G
%
)
6
G
%
)
6
7
+]
N
N
N N
N
N
N N
+]
Figure 5-15. Frequency Response, FSext = 8 kHz, Notch Filter Figure 5-16. Frequency Response, FSext = 8 kHz, Notch Filter
Disabled, Preamp Enabled (+10 or +20 dB), –1 dBFS
Enabled, Preamp Enabled (+10 or +20 dB), –1 dBFS
19
DS963DB2
CDB53L30
5 Performance Plots
Note: The low-frequency distortion
is dominated by the MLCC Class II
DC blocking capacitor (0.1 F). To
reduce this distortion, reduce the
corner frequency by selecting a
larger cap, or choose a different cap
type such as film or MLCC Class I.
G
%
G
%
PGA Setting: +12 dB
PGA Setting: +12 dB
PGA Setting: 0 dB
PGA Setting: 0 dB
N
N
N
N N
N
N
N
N N
+]
+]
Figure 5-17. THD+N (Relative) vs. Frequency,
Preamp Setting: 0 dB, –1 dBFS
Figure 5-18. THD+N (Relative) vs. Frequency,
Preamp Setting: +10 dB, –1 dBFS
G
%
G
%
PGA Setting: +12 dB
PGA Setting: 0 dB
N
N
N
N N
+]
Figure 5-19. THD+N (Relative) vs. Frequency,
Preamp Setting: +20 dB, –1 dBFS
G
%
G
%
G%U
Figure 5-21. THD+N (Relative) vs. Level, Preamp Setting: 0 dB,
PGA Setting: +12 dB, 1 kHz
20
Figure 5-20. THD+N (Relative) vs. Level, Preamp Setting: 0 dB,
PGA Setting: 0 dB, 1 kHz
G%U
G%U
Figure 5-22. THD+N (Relative) vs. Level,
Preamp Setting: +10 dB, PGA Setting: 0 dB, 1 kHz
DS963DB2
CDB53L30
5 Performance Plots
G
%
G
%
G%U
G%U
Figure 5-23. THD+N (Relative) vs. Level,
Preamp Setting: +10 dB, PGA Setting: +12 dB, 1 kHz
Figure 5-24. THD+N (Relative) vs. Level,
Preamp Setting: +20 dB, PGA Setting: 0 dB, 1 kHz
G
%
G
%
)
6
G%U
Figure 5-25. THD+N (Relative) vs. Level,
Preamp Setting: +20 dB, PGA Setting: +12 dB, 1 kHz
21
N
N
N
N N
+]
Figure 5-26. FFT, Adjacent Channel Crosstalk at 10 kHz,
Preamp Setting: +20 dB, PGA Setting: +12 dB, –1 dBFS
DS963DB2
CDB53L30
6 Schematics
6 Schematics
CS53L30-1
TP12
1.ASP_SDOUT1
VA
I2C Address: 0x90
R22
NO POP
CS53L30-1.DMIC1_SCLK
R34
0
R36
0
[2]
0
R62
0
CS53L30-1.ASP_SDOUT1 [4]
CS53L30-1.ASP_SCLK [4]
CS53L30-1.MCLK
TP42
1.MCLK
TP17
1.DMIC1_SCLK
[2] CS53L30-1.DMIC2_SCLK/AD1
TP13
1.ASP_SCLK
R59
[3]
VA
CS53L30.I2C.SDA [2,5]
CS53L30.I2C.SCL [2,5]
TP19
1.DMIC2_SCLK/AD1
R23
10K
R21
NO POP
CS53L30-1.IN1+
CS53L30-1.IN1CS53L30-1.IN2+
CS53L30-1.IN2CS53L30-1.IN3+
CS53L30-1.IN3CS53L30-1.IN4+
CS53L30-1.IN4-
1
2
3
4
5
6
7
8
VA
PAD
0
CS53L30-1.ASP_SDOUT2/AD0 [4]
0
CS53L30-1.ASP_LRCK/FSYNC [4]
R19
10K
VA
IN2+
SCL
IN2ASP_SDOUT2/AD0
IN3+/DMIC2_SD
ASP_LRCK/FSYNC
U5
VA
IN3GNDD
IN4+
CS53L30-QFN32
SYNC
IN4RESET
VA
INT
GNDA
THERM
R9
R29
24
23
22
21
20
19
18
17
VA
C36
X5R
0.1uF
R30
10K
TP20
1.SYNC
CS53L30-1.SYNC [3]
CS53L30-1.RESET
CS53L30-1.INT
[5]
[5]
9
10
11
12
13
14
15
16
C30
X5R
0.1uF
TP16
1.ASP_LRCK/FSYNC
FILT+
VP
MIC1_BIAS
MIC2_BIAS
MIC3_BIAS
MIC4_BIAS
MIC_BIAS_FILT
MUTE
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
IN1IN1+/DMIC1_SD
DMIC2_SCLK/AD1
DMIC1_SCLK
ASP_SDOUT1
ASP_SCLK
MCLK
SDA
32
31
30
29
28
27
26
25
TP15
1.ASP_SDOUT2/AD0
CS53L30-1.MUTE [5]
TP5
1.MIC_BIAS_FILT
TP6
1.FILT+
C29
X5R
4.7UF
VP
C28
X5R
2.2uF
TP7
1.MIC1_BIAS
C31
X5R
0.1uF
CS53L30-1.MIC1_BIAS
CS53L30-1.MIC2_BIAS
CS53L30-1.MIC3_BIAS
CS53L30-1.MIC4_BIAS
C37
X5R
1uF
CS53L30-2
C38
X5R
1uF
C39
X5R
1uF
TP10
1.MIC3_BIAS
C40
X5R
1uF
TP35
2.ASP_SDOUT1
VA
I2C Address: 0x92
R35
NO POP
CS53L30-2.DMIC1_SCLK
R103
0
[2] CS53L30-2.DMIC2_SCLK/AD1
R105
0
TP36
2.ASP_SCLK
R96
0
CS53L30-2.ASP_SDOUT1 [4]
R98
0
CS53L30-2.ASP_SCLK [4]
CS53L30-2.MCLK
[3]
VA
TP40
2.DMIC2_SCLK/AD1
R37
10K
[2]
[2]
[2]
[2]
TP11
1.MIC4_BIAS
TP14
2.MCLK
TP39
2.DMIC1_SCLK
[2]
TP9
1.MIC2_BIAS
CS53L30.I2C.SDA
[2,5]
CS53L30.I2C.SCL
[2,5]
R107
10K
CS53L30-2.IN1+
CS53L30-2.IN1CS53L30-2.IN2+
CS53L30-2.IN2CS53L30-2.IN3+
CS53L30-2.IN3CS53L30-2.IN4+
CS53L30-2.IN4-
1
2
3
4
5
6
7
8
VA
VA
IN2+
SCL
IN2ASP_SDOUT2/AD0
IN3+/DMIC2_SD
ASP_LRCK/FSYNC
U22
VA
IN3GNDD
IN4+
CS53L30-QFN32
SYNC
IN4RESET
VA
INT
GNDA
THERM
24
23
22
21
20
19
18
17
R101
0
CS53L30-2.ASP_SDOUT2/AD0 [4]
R102
0
CS53L30-2.ASP_LRCK/FSYNC [4]
R106
NO POP
VA
C61
X5R
0.1uF
R95
10K
TP41
2.SYNC
CS53L30-2.SYNC
CS53L30-2.RESET
CS53L30-2.INT
[3]
[5]
[5]
9
10
11
12
13
14
15
16
C60
X5R
0.1uF
PAD
TP38
2.ASP_LRCK/FSYNC
FILT+
VP
MIC1_BIAS
MIC2_BIAS
MIC3_BIAS
MIC4_BIAS
MIC_BIAS_FILT
MUTE
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
IN1IN1+/DMIC1_SD
DMIC2_SCLK/AD1
DMIC1_SCLK
ASP_SDOUT1
ASP_SCLK
MCLK
SDA
32
31
30
29
28
27
26
25
TP37
2.ASP_SDOUT2/AD0
CS53L30-2.MUTE [5]
TP29
2.MIC_BIAS_FILT
TP30
2.FILT+
C58
X5R
4.7UF
VP
C57
X5R
2.2uF
TP31
2.MIC1_BIAS
C59
X5R
0.1uF
TP32
2.MIC2_BIAS
CS53L30-2.MIC1_BIAS
CS53L30-2.MIC2_BIAS
CS53L30-2.MIC3_BIAS
CS53L30-2.MIC4_BIAS
C62
X5R
1uF
C63
X5R
1uF
C64
X5R
1uF
C65
X5R
1uF
TP33
2.MIC3_BIAS
[2]
[2]
[2]
[2]
TP34
2.MIC4_BIAS
Figure 6-1. CS53L30
22
DS963DB2
CDB53L30
6 Schematics
CS53L30-1
Input 1 (Analog/Digital)
1.AIN1
T
R
Input 2 (Analog)
1.AIN2
4
2
6
CS53L30-1.MIC1_BIAS
5
3
Rbias
CK-3.5-027A
J53
AINSleeve
J6
HDR5X2
1
2
3
4
5
6
7
8
9
10
R27
1.8K J39
J36
[2]
R
Rbias Short
(Jumper)
J38
C20
C78
0.1uF
X5R
0.1uF
X5R
CS53L30-1.IN1+
[2]
T
R
CS53L30-1.IN1-
[2]
1.AIN4
5
3
J19
HDR5X2
1
2
3
4
5
6
7
8
9
10
Rbias Short
(Jumper)
Bias to AIN+
(Jumper)
J43
C21
1.AIN2+
1.AIN21.BIAS2
C22
0.1uF
X5R
0.1uF
X5R
CS53L30-1.IN2+
[2]
CS53L30-1.IN2-
[2]
Input 4 (Analog)
CS53L30-1.MIC3_BIAS
Rbias
AINSleeve
[2]
CS53L30-1.DMIC1_SCLK [2]
4
2
6
CK-3.5-027A
J16
Rbias
R51
1.8K J44
J3
AINSleeve
J17
HDR3X2
1
2
3
4
5
6
Input 3 (Analog/Digital)
1.AIN3
CS53L30-1.MIC2_BIAS
5
3
CK-3.5-027A
J12
Bias to AIN+
(Jumper)
1.AIN1+
1.AIN11.BIAS1
1.DATA1
1.SCLK1
4
2
6
T
R56
1.8K J45
J15
[2]
R
Rbias Short
(Jumper)
5
3
J42
C23
C24
0.1uF
X5R
0.1uF
X5R
CS53L30-1.MIC4_BIAS
Rbias
CK-3.5-027A
J20
Bias to AIN+
(Jumper)
1.AIN3+
1.AIN31.BIAS3
1.DATA2
1.SCLK2
4
2
6
T
CS53L30-1.IN3+
[2]
CS53L30-1.IN3-
[2]
AINSleeve
J22
HDR3X2
1
2
3
4
5
6
R68
1.8K J86
J18
[2]
Rbias Short
(Jumper)
Bias to AIN+
(Jumper)
J85
C25
1.AIN4+
1.AIN41.BIAS4
C26
0.1uF
X5R
0.1uF
X5R
CS53L30-1.IN4+
[2]
CS53L30-1.IN4-
[2]
CS53L30-1.DMIC2_SCLK/AD1 [2]
CS53L30-2
Input 1 (Analog/Digital)
2.AIN1
T
R
Input 2 (Analog)
2.AIN2
4
2
6
CS53L30-2.MIC1_BIAS
5
3
CK-3.5-027A
J7
Rbias
AINSleeve
J11
HDR5X2
1
2
3
4
5
6
7
8
9
10
R69
1.8K J73
J10
[2]
R
Rbias Short
(Jumper)
J72
C27
C66
0.1uF
X5R
0.1uF
X5R
CS53L30-2.IN1+
[2]
T
R
CS53L30-2.IN1-
[2]
2.AIN4
5
3
J28
HDR5X2
1
2
3
4
5
6
7
8
9
10
Rbias
J24
R168
1.8K J51
[2]
Rbias Short
(Jumper)
Bias to AIN+
(Jumper)
J77
C71
1.AIN2+
1.AIN21.BIAS2
C72
0.1uF
X5R
0.1uF
X5R
Rbias Short
(Jumper)
CS53L30-2.IN2+
[2]
CS53L30-2.IN2-
[2]
C74
CS53L30-2.MIC4_BIAS
5
3
Rbias
CK-3.5-027A
J30
J50
0.1uF
X5R
0.1uF
X5R
4
2
6
T
R
Bias to AIN+
(Jumper)
C73
1.AIN3+
1.AIN31.BIAS3
1.DATA2
1.SCLK2
J21
[2]
Input 4 (Analog)
CS53L30-2.MIC3_BIAS
AINSleeve
R124
1.8K J78
CS53L30-2.DMIC1_SCLK [2]
4
2
6
CK-3.5-027A
J26
Rbias
AINSleeve
J25
HDR3X2
1
2
3
4
5
6
Input 3 (Analog/Digital)
2.AIN3
CS53L30-2.MIC2_BIAS
5
3
CK-3.5-027A
J23
Bias to AIN+
(Jumper)
1.AIN1+
1.AIN11.BIAS1
1.DATA1
1.SCLK1
4
2
6
T
CS53L30-2.IN3+
[2]
CS53L30-2.IN3-
[2]
J32
HDR3X2
1
2
3
4
5
6
AINSleeve
J27
R169
1.8K J46
[2]
Rbias Short
(Jumper)
Bias to AIN+
(Jumper)
J41
C75
1.AIN4+
1.AIN41.BIAS4
C76
0.1uF
X5R
0.1uF
X5R
CS53L30-2.IN4+
[2]
CS53L30-2.IN4-
[2]
CS53L30-2.DMIC2_SCLK/AD1 [2]
DC Blocking Capacitors
The value of the DC blocking capacitor can be modified according
to the desired high-pass corner frequency, determined by the
CS53L30 input impedance. Several example calculations are shown
in the table below.
Preamp
Setting
CS53L30 Input DC Blocking
Impedance
Capacitor
High-Pass
Corner Freq
Bypass
50k
0.1 uF
+10 or +20
1M
0.1 uF
31.8 Hz
1.6 Hz
+10 or +20
1M
0.01 uF
15.9 Hz
Figure 6-2. Inputs
23
DS963DB2
CDB53L30
6 Schematics
Master Clock PLL
+3.3V
I2C Address: 0x9C
+3.3V
C133
X5R
0.1uF
C134
X5R
1uF
6.3V
R143
0
NO POP
To MCLK routing buffers
[3] PLL.CLK_OUT1
R74
22.1
[3] PLL.CLK_OUT2
R70
22.1
PLL_AUX_OUT
+3.3V
R14
U15
CS2300CP-CZZ
1
2
3
4
5
22.1
SDA/CDIN
SCL/CCLK
AD0/CS
FILTN
FILTP
VD
GND
CLK_OUT
AUX_OUT
CLK_IN
10
9
8
7
6
R104
R136
0
0
C135
X5R
0.1uF
UC.I2C.SDA [4,5]
UC.I2C.SCL [4,5]
R142
0
L1
600OHM@100MHZ
R255
0
Y1
24.576MHZ
1
3
TRI-S OUT
4
VDD
2
C85
X5R
1uF
6.3V
R200
22.1
R138
0402
NO POP
GND
C127
COG
1000pF
[4]PLL.LRCK_IN
Optional LRCK reference
(from Serial Audio Header)
Master Clock Routing
All buffer inputs are 5.5V tolerant,
independent of supply voltage.
R127
10K
To Serial Header
U28
[5]
2
A1
1
OE
5
A2
7
OE
HDR_MCLK_OUT_EN
[3] PLL.CLK_OUT2
[5] PLL_MCLK_OUT_EN
R128
10K
Y1
Y2
6
R71
0
3
R72
0
R167
22.1
MCLK_OUT [4]
VA
8
VCC
4
GND
R67
NC7WZ241K8X
NO POP
+1.8V
0
R66
0
C51
X5R
0.1uF
R73
0
From Serial Header
[4]
MCLK_IN
R18
0
R129
10K
U4
2
A1
1
OE
5
A2
7
OE
[5] HDR_MCLK_IN_EN
[3] PLL.CLK_OUT1
[5] PLL_MCLK_EN
R130
10K
Y1
Y2
6
R57
0
3
R58
0
8
VCC
4
GND
NC7WZ241K8X
VA
R26
NO POP
R20
R65
22.1
R99
22.1
R97
22.1
CS53L30-1.MCLK
CS53L30-2.MCLK
CS8406.OMCK
[2]
[2]
[4]
+1.8V
0
0
C49
X5R
0.1uF
Figure 6-3. Master Clock PLL and Routing Buffers
24
DS963DB2
CDB53L30
6 Schematics
Serial Audio Header
VA
+1.8V
R85
NO POP
R92
+1.8V
R126
10K
0
0
R94
C56
X5R
0.1uF
0
C55
X5R
0.1uF
R44
0
NO POP
3
NTR4501NT1G
CS53L30-1.ASP_SCLK
R76
0
[2]
CS53L30-2.ASP_SCLK
R77
0
[4]
SPDIF_TX.SCLK
R162
0
[2] CS53L30-1.ASP_LRCK/FSYNC
R78
[2] CS53L30-2.ASP_LRCK/FSYNC
R79
0
SPDIF_TX.LRCK
R164
0
PLL.LRCK_IN
R135
0
[2]
[4]
[3]
U21
1
VCCA
2
A1
3
A2
4
GND
0
1
8
VCCB
7
B1
6
B2
5
DIR
R91
R90
0
0
2
SERIAL_HDR.M/S
[5]
Q1
R125
10K
SN74LVC2T45DCUR
VA
+1.8V
R87
NO POP
R86
+1.8V
0
0
R88
C54
X5R
0.1uF
0
To Master Clock
Routing Buffers
C42
X5R
0.1uF
U20
[2,4]
[2,4]
8
VCCB
7
B1
6
B2
5
DIR
1
VCCA
2
A1
3
A2
4
GND
CS53L30-1.ASP_SDOUT1
CS53L30-1.ASP_SDOUT2/AD0
[3]
MCLK_OUT
[3]
MCLK_IN
0
0
MCLK OUT 1
MCLK IN 3
SCLK 5
LRCK/FSYNC 7
1.ASP1_SDOUT 9
1.ASP2_SDOUT 11
2.ASP1_SDOUT 13
2.ASP2_SDOUT 15
SN74LVC2T45DCUR
VA
+1.8V
R63
R52
NO POP
Serial Header
J29
R84
R75
+1.8V
0
0
R64
C41
X5R
0.1uF
2
4
6
8
10
12
14
16
0
C34
X5R
0.1uF
U14
[2,4]
[2,4]
8
VCCB
7
B1
6
B2
5
DIR
1
VCCA
2
A1
3
A2
4
GND
CS53L30-2.ASP_SDOUT1
CS53L30-2.ASP_SDOUT2/AD0
R81
R80
0
0
SN74LVC2T45DCUR
External Sync I/O
VA
+1.8V
R93
NO POP
R117
0
0
R122
C80
X5R
0.1uF
0
External
Sync I/O
Header
U25
1
VCCA
2
A1
3
A2
4
GND
[2] CS53L30-1.SYNC
R123
0
[2] CS53L30-2.SYNC
R155
0
8
VCCB
7
B1
6
B2
5
DIR
R120
J33
SYNC I/O
0
SN74LVC2T45DCUR
R119
10K
R116
10K
Sync Direction
Jumper
J37
HDR3X1
SYNC OUT
SYNC IN
R115
10K
Figure 6-4. Serial Audio Header, Sync I/O
DS963DB2
25
26
VA
VA
NO POP
0
0
R49
R50
NO POP
0
0
SPDIF_TX.LRCK
SPDIF_TX.SCLK
R82
R55
C14
X5R
0.1uF
C33
X5R
0.1uF
[2,4]
[2,4]
VA
R10
R31
NO POP
0
0
C12
X5R
0.1uF
CS53L30-2.ASP_SDOUT1
CS53L30-2.ASP_SDOUT2/AD0
+1.8V
[2,4]
CS53L30-1.ASP_SDOUT1
[2,4] CS53L30-1.ASP_SDOUT2/AD0
+1.8V
[4]
[4]
+1.8V
I2C Address: 0x28
1
VCCA
2
A1
3
A2
4
GND
U10
1
VCCA
2
A1
3
A2
4
GND
1
VCCA
2
A1
3
A2
4
GND
SN74LVC2T45DCUR
8
VCCB
7
B1
6
B2
5
DIR
U8
SN74LVC2T45DCUR
8
VCCB
7
B1
6
B2
5
DIR
SN74LVC2T45DCUR
8
VCCB
7
B1
6
B2
5
DIR
U23
R160
R161
C11
X5R
0.1uF
+3.3V
R158
R159
C13
X5R
0.1uF
+3.3V
R156
R157
C32
X5R
0.1uF
+3.3V
0
0
0
0
0
0
R133
1.ASP1_SDOUT
1.ASP2_SDOUT
CS8406.ILRCK
CS8406.ISCLK
2.ASP1_SDOUT
2.ASP2_SDOUT
SPDIF Transmitter
CS8406.SDIN
R134
0
22.1
U12
SN74CB3Q3251PW
16
1
VCC
B4
15
2
B5
B3
14
3
B6
B2
4
13
B1
B7
5
12
A
B8
6
11
NC
S0
7
10
OE
S1
8
9
GND
S2
4x1 SDIN MUX
SPDIF_TX.SDIN_SEL0
SPDIF_TX.SDIN_SEL1
C79
X5R
0.1uF
+3.3V
[5]
[5]
[5] SPDIF_TX.RST
R83
10K
C137
X5R
0.1uF
+3.3V
SDIN
ISCLK
ILRCK
TEST
TEST
RST
TEST
TEST
VD
TEST
RXP
AD2
AD0/CS
U81
SDA/CDOUT
TCBL
TEST
TEST
TEST
INT
U
OMCK
GND
VL
H/S
TXN
TXP
AD1/CKIN
SCL/CCLK
CS8406-CZZ-SOFTWARE MODE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C77
0.01UF
X7R
R131
UC.I2C.SCL [3,5]
UC.I2C.SDA [3,5]
-
+3.3V
-
+
N/C
N/C
N/C
N/C
Q2
SC979-03LF-Z
+
8
7
6
5
15
16
17
18
19 NC
20
21
22
23
3
C138
X5R
0.1uF
+3.3V
C246
X5R
0.1uF
1
2
N.C.
GND
VCC
IN
N.C.
R132
107
1
2
3
4
OPT2
DLT2180A
210
25
CS8406.OMCK [3]
0
R258
24
26
27
28
0
R137
Note:
To use the CS8406 transmitter, the CS53L30 must be configured
for I2S format with a MLCK/LRCK ratio of 128, 256, or 512.
5
4
C53
C0G
22pF
J35
Optical S/PDIF TX
Coaxial S/PDIF TX
CDB53L30
6 Schematics
Figure 6-5. S/PDIF Transmitter
DS963DB2
CDB53L30
6 Schematics
Microcontroller
+3.3V
+3.3V
+3.3V
C83
X5R
4.7UF
C82
X5R
4.7UF
C84
X5R
0.1uF
C118
X5R
0.1uF
R39
1K
SERIAL_HDR.M/S
[4]
R38
1K
U7
6
[3] HDR_MCLK_OUT_EN
To MCLK
[3] PLL_MCLK_OUT_EN
Routing Buffers [3] HDR_MCLK_IN_EN
[3]
PLL_MCLK_EN
[4]
To SPDIF
SDIN Mux
R32
R33
R108
R109
R110
R111
R112
R113
SPDIF_TX.RST
18
17
16
15
14
13
12
11
0
0
0
0
0
0
0
0
REGIN
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
10
P3.0/C2D
9
RST/C2CK
[4] SPDIF_TX.SDIN_SEL0
[4] SPDIF_TX.SDIN_SEL1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
8
VBUS
5
D4
D+
[5] UC.P3.0/C2D
[5] UC.RST/C2CK
[5,6]
[5]
[5]
VDD
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
3
USB.VBUS
USB.DUSB.D+
GND
7
1
2
32
31
30
29
28
27
SCL
SDA
R182
R183
0
0
UC.I2C.SCL
UC.I2C.SDA
[3,4,5]
[3,4,5]
MOSI
NSS
TX
RX
I2C
SPI
26 SW/HW R139
25
NC
24
R60
23
R28
22
R180
21
R179
20
R177
19
R181
0
UC.SW/HW [5]
0
0
0
0
0
0
UC.CS53L30-1.RESET
UC.CS53L30-1.INT
UC.CS53L30-1.MUTE
UC.CS53L30-2.RESET
UC.CS53L30-2.INT
UC.CS53L30-2.MUTE
[5]
[5]
[5]
[5]
[5]
[5]
C8051F320-GQ
FlexGUI USB Connection
R89
0
R100
0
C140
0402
NO POP
USB.D+
[5]
USB.D-
[5]
C146
0402
NO POP
J94
5
600OHM@100MHZ
1
2
L2
C90
X5R
0.1uF
C96
X5R
10uF
C196
X5R
10uF
NO POP
2
4
C139
C0G
22pF
R435
D6
1
292304-1
3
C93
COG
1000pF
6
GND
R163
0
USB.VBUS [5,6]
2
1
+5V
2
D3
D+
4
GND
C198
X5R
0.1uF
C211
COG
1000pF
D4
GREEN
1
GND
USB PRESENT
0
R5
1K
1%
SP0503BAHTG
Reset and C2 Header
+3.3V
R46
1K
R47
1K
S11
1
3
5
UC FLEX RESET
C123
X5R
1uF
J5
UC FLEX C2
1
2
3
4
5
6
7
8
9
10
R48
1K
C97
X5R
0.1uF
UC.P3.0/C2D
[5]
UC.RST/C2CK
[5]
Board ID EEPROM
+3.3V
C35
[3,4,5]
UC.I2C.SCL
1
R114
0
2
[3,4,5]
UC.I2C.SDA
3
R121
0
0.1uF
X5R
SCL
VCC
VSS
NC
5
4
SDA
U13
24LC00-I/OT
Figure 6-6. Microcontroller
DS963DB2
27
CDB53L30
6 Schematics
Level Shifters and Control I/O Header
VA
R153
11.5K
1%
NO POP
[5] UC.SW/HW
OE1
[5]
2
UC.CS53L30-1.RESET
+1.8V
1
A1 Y1
6
R145
0
R147
NO POP
Optional
Voltage
Supervisor
R144
11.5K
1%
+3.3V
+3.3V
U24
MIC2774L-31YM5
0
R151
10K
U27-B
1
NC7WZ126K8X
4
VDD
RST
MR
IN
[5] UC.SW/HW
5
3
GND
OE2
5
[5] UC.CS53L30-2.RESET
7
A2 Y2
3
R146
0
R148
NO POP
R154
2.49K
1%
0
U27-C
0805
VTH= 1.69V
NC7WZ126K8X
+1.8V
+3.3V
V 8
C81
X5R
0.1uF
R152
NO POP
2
R54
0
U27-A
+3.3V
NC7WZ126K8X
VA
R140
0
NO POP
G4
C45
X5R
0.1uF
+1.8V
U19
VA
R42
0
+3.3V
C46
X5R
0.1uF
R43
0
NO POP
C43
X5R
0.1uF
8
VCCB
7
B1
6
B2
5
DIR
1
VCCA
2
A1
3
A2
4
GND
R118
10K
R141
10K
SN74LVC2T45DCUR
C44
X5R
0.1uF
R149
10K
R150
10K
U11
8
VCCB
7
B1
6
B2
5
DIR
1
VCCA
2
A1
3
A2
4
GND
[5] UC.CS53L30-1.INT
[5] UC.CS53L30-2.INT
SN74LVC2T45DCUR
Place jumpers
for FlexGUI control
J4
+1.8V
1.RESET
VA
TP21
1.RESETb
TP22
1.INTb
TP23
1.MUTE
1.INT
1.MUTE
+3.3V
R1
0
2.RESET
R2
0
NO POP
2.INT
2.MUTE
C47
X5R
0.1uF
SDA
C48
X5R
0.1uF
TP24
2.RESETb
SCL
TP25
2.INTb
CS53L30-1.RESET
[2,5]
CS53L30-1.INT
[2,5]
CS53L30-1.MUTE
[2,5]
CS53L30-2.RESET
[2,5]
CS53L30-2.INT
[2,5]
CS53L30-2.MUTE
[2,5]
TP26
2.MUTE
U6
[5] UC.CS53L30-1.MUTE
[5] UC.CS53L30-2.MUTE
8
VCCB
7
B1
6
B2
5
DIR
1
VCCA
2
A1
3
A2
4
GND
Attach ribbon cable for
external system connection
VA
VA
SN74LVC2T45DCUR
+1.8V
R166
1K
NO POP
VA
R165
1K
NO POP
TP27
SDA
R45
0
+3.3V
R53
0
NO POP
Optional pull-ups for
external bus master
CS53L30.I2C.SDA
[2]
CS53L30.I2C.SCL
[2]
TP28
SCL
+3.3V
C7
X5R
0.1uF
[3,4,5] UC.I2C.SDA
[3,4,5] UC.I2C.SCL
C8
X5R
0.1uF
8
1
VCCB
VCCA
6
SDAB
7
SCLB
R24
1K
R25
1K
R40
10K
3
SDAA
2
SCLA
5
EN
[2,5]
[2,5]
[2,5]
GND
4
U9
PCA9517DP
Optional Control Signal Shorts
CS53L30-1.RESET
CS53L30-1.INT
CS53L30-1.MUTE
J34
HDR3X2
1.RESET 1
2
1.INT
3
4
1.MUTE 5
6
2.RESET
2.INT
2.MUTE
CS53L30-2.RESET
CS53L30-2.INT
CS53L30-2.MUTE
[2,5]
[2,5]
[2,5]
R41
NO POP
0402
Figure 6-7. Level Shifters, Control I/O Header
28
DS963DB2
CDB53L30
6 Schematics
Power Supply Binding Posts
+5V_EXT
+5V
J83
1
+5V_EXT
1
J89
2
[5]
TP18
+5V
USB.VBUS
C244
TANT
100uF
10V
Z4
P6SMB6.8AT3G
6.8Vbr
J31
1
GND
VA_EXT
J9
1
J1
2
VA
+1.8V
1
VA_EXT
C3
TANT
100uF
10V
Z1
P6SMB6.8AT3G
6.8Vbr
R3
TP1
VA
1
current sense
J2
VP_EXT
J14
1
J8
2
VP
+3.6V
1
VP_EXT
VP I-SENSE
C1
TANT
100uF
10V
Z3
P6SMB6.8AT3G
6.8Vbr
R4
TP3
VP
1
current sense
J13
+5.0V to +3.3V LDO: Digital
+5V
R17
10K
1%
+5V
U2-A
LP3878SD-ADJ
4
INPUT
3
GND
2
N/C
1
BYPASS
C69
X5R
10uF
5
OUTPUT
6
ADJ
7
N/C
8
SHUTDOWN
+3.3V
TP8
+3.3V
C70
COG
1000pF
C67
X7R
0.01UF
R6
2.32K
1%
C68
X5R
10uF
6.3V
9
THERM
LP3878SD-ADJ
U2-B
C2
TANT
100uF
10V
R7
1K
1%
+5.0V to +1.8V LDO: VA
+5V
+5.0V to +3.6V LDO: VP
+5V
+5V
U3-A
LP3878SD-ADJ
+5V
U1-A
LP3878SD-ADJ
C6
X5R
10uF
4
INPUT
3
GND
2
N/C
1
BYPASS
5
OUTPUT
6
ADJ
7
N/C
8
SHUTDOWN
C4
X7R
0.01UF
9
THERM
LP3878SD-ADJ
U1-B
R16
10K
1%
+3.6V
C17
X5R
10uF
C9
COG
1000pF
R8
2.61K
1%
C5
X5R
10uF
6.3V
C10
TANT
100uF
10V
R11
1K
1%
4
INPUT
3
GND
2
N/C
1
BYPASS
5
OUTPUT
6
ADJ
7
N/C
8
SHUTDOWN
C15
X7R
0.01UF
9
THERM
LP3878SD-ADJ
U3-B
R12
10K
1%
+1.8V
C18
COG
1000pF
R13
1.62K
1%
C16
X5R
10uF
6.3V
C19
TANT
100uF
10V
R15
1K
1%
R61
1K
1%
Figure 6-8. Power Supply
DS963DB2
29
CDB53L30
7 Layout
7 Layout
Figure 7-1. Assembly Drawing (Top Side)
30
DS963DB2
CDB53L30
7 Layout
Figure 7-2. Layer 1 (Component, Signal—Top)
DS963DB2
31
CDB53L30
7 Layout
Figure 7-3. Layer 2 (Ground)
32
DS963DB2
CDB53L30
7 Layout
Figure 7-4. Layer 3 (+3.3 V, +1.8 V, VP)
DS963DB2
33
CDB53L30
7 Layout
Figure 7-5. Layer 4 (Signal)
34
DS963DB2
CDB53L30
7 Layout
Figure 7-6. Layer 5 (VA)
DS963DB2
35
CDB53L30
7 Layout
Figure 7-7. Layer 6 (Signal—Bottom)
36
DS963DB2
CDB53L30
8 Revision History
8 Revision History
Revision
Changes
DB1
Initial release
DB2
Updated pin name references to match CS53L30 data sheet Rev F1.
Updated Fig. 2-1 and Fig. 3-1 to match CDB53L30 Rev B.
Updated GUI tab figures in Section 4.
Updated schematic figures in Section 6 to match CDB53L30 Rev B.
Updated Fig. 7-1 and Fig. 7-7 to match CDB53L30 Rev B.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
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to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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I2C is a trademark of Philips Semiconductor.
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DS963DB2
37