AN312 CobraNet® Clocking Modes 1. INTRODUCTION In most cases, a CobraNet® system is used with its default audio clocking mode (0x00). This allows automatic synchronization of audio clocks network wide. However, the clocking circuitry of a CobraNet device can be configured to operate in a number of ways that are specified by the values written to the syncConductorClock and syncPerformerClock Management Interface (MI) variables. These two MI variables are used independently to set the clocking mode of an interface depending on whether it is operating as a Conductor or a Performer. These variables can be set by using SNMP or the Host Management Interface (HMI). Please see the CobraNet Programmer's Reference Manual and the CobraNet Hardware User's Manual for more information on the variables, SNMP, and the Host Management Interface. 2. IMPORTANT CONCEPTS REGARDING CobraNet CLOCKING All devices in a CobraNet network must operate within the same clock domain. It is therefore a requirement that, regardless of clock mode, all audio clocks on the network should be derived from the same master clock to ensure that they remain synchronized. This is accomplished automatically when using the default clock mode, 0x00, and when any digital devices attached to the CobraNet interface receive their audio clocks from the CobraNet interface. • Any CobraNet interface that uses one of the external clocking modes must use external clocks that are synchronous with the network audio clock. • A digital audio device that does not receive its audio clocks from the CobraNet interface must be connected to the CobraNet interface using a sample rate converter. For instance, all digital audio devices connected to CobraNet devices must be in the same audio clock domain as the CobraNet network. • Any clock mode that uses the external word clock (REFCLK_IN) will not work unless the REFCLK_IN pin is first enabled by clearing the second bit (bit 1) of the syncBuddyLinkControl MI variable. 3. CORE CLOCK CIRCUITRY OF A CobraNet INTERFACE The core clock circuitry of a CobraNet interface is depicted in Figures 1 and 2. Note that not all inputs and outputs to the clock module are used at the same time in all modes. Operation of the circuitry, and activity on each path, are dependent on the clock mode selected. These different clocking modes can be used in many ways, depending on the requirements of a particular application. Common usage of the different modes is described in this document. The user-available external clock connections are REFCLK, MCLK_IN, MCLK_OUT, FS1, and SCLK. The other connections are internal to the interface and utilized by the interface's firmware in response to the particular mode in use. The five audio clock modes are: • 0x00 - Internal (Normal Default Mode) • 0x10 - Internal with External Sample Synchronization • 0x01 - External Word Clock • 0x04 - External Master Clock • 0x14 - External Master Clock with External Sample Synchronization http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) MAY ‘08 AN312REV2 AN312 MCLK_OUT (master) control DAC VCXO 24.576MHz +/- 100 PPM Clock Out FS1 (word) Audio Clock Generator MCLK MUX MCLK_IN MCLK_SEL SCK (bit) Sample Phase Counter REFCLK_Enable Edge Detect REFCLK_Polarity RST Phase Detector Loop Filter REFCLK Beat MUX Beat Received Clock Config Signal Path Control Path Hardware FPGA Software Figure 1. - CobraNet Clock Circuit for CM-1 Module M C L K _ O U T (m a s ter) c o n tro l DAC VCXO 2 4 .5 76 M H z + /- 1 0 0 P P M C lo c k O ut F S 1 (w o rd ) A u d io C lo c k G e n e ra to r M C LK MUX M C LK _ IN S C K (b it) S a m p le Phase C o u n ter Phase D e te c to r M C LK_SEL Loop F ilte r R EFC LK B e a t R e c e iv e d Beat MUX C lo ck C o nfig S ig n a l P a th C o n tro l P a th E x te rn a l H a rd w a re C o b ra N e t P ro ce s s o r S o ftw a re Figure 2. CobraNet Clock Circuit for CM-2 Module and Semiconductors 2 AN312REV2 AN312 3.1 CobraNet Clock Modes This section describes each of the CobraNet clock modes. 3.1.1 0x00 Mode - Internal Mode (Default) The 0x00 Mode is the default clock mode of a CobraNet interface. When operating in this mode: • As Conductor: The master audio clock (MCLK) is generated by the VXCO parked at its center frequency. Word clock (FS1) and bit clock (SCLK) are derived directly from MCLK. • As Performer: The master audio clock (MCLK) is generated by the VXCO, which receives frequency adjustments from the beat packets received from the Conductor node over the network interface, insuring that the Performer's clock is in sync with the Conductor. Word clock (FS1) and bit clock (SCLK) are derived from MCLK. MCLK_OUT (Master Audio Clock) FS1 (LR clock) CobraNet Interface DAC or ADC SCLK (Bit clock) Figure 3. 0x00 Mode Typical Connections M C LK_O UT (m aster) control DAC VCXO 24.576 M H z +/- 100 PPM C lock O ut FS1 (word) Audio Clock G enerator M CLK MUX M C LK_IN M C LK_SEL SC K (bit) Sam ple Phase Counter R EFC LK_Enable Edge Detect R EFC LK _Polarity RST Phase Detector Loop Filter REFCLK Beat M UX Beat Received C lock C onfig Signal Path Control Path Active Signal Path Hardw are FPG A Software Figure 4. Clock Circuit as Used by 0x00 Mode with CM-1 Module AN312REV2 3 AN312 M C L K _ O U T (m a s te r ) c o n tro l DAC VCXO 2 4 .5 7 6 M H z + /- 1 0 0 P P M C lo c k O ut F S 1 (w o rd ) A u d io C lo c k G e n e ra to r M C LK MUX M C L K _ IN S C K (b it) S a m p le Phase C o u n te r Phase D e te c to r M C LK_SEL Loop F ilte r R EFC LK Beat MUX B e a t R e c e iv e d C lo c k C o n fig S ig n a l P a th C o n tro l P a th E x te rn a l H a rd w a re A c tiv e S ig n a l P a th C o b ra N e t P ro c e s s o r S o ftw a re Figure 5. Clock Circuit as Used by Mode 0x00 with CM-2 and Semiconductors 3.1.2 0x10 Mode - Internal Mode with External Sample Synchronization Note: This will not work properly with CM-2 modules or semiconductor-based designs due to the absence of the edge detect circuit in the semiconductor. This mode is similar to Internal Mode (0x00), but allows synchronization of the derived SCLK and FS1 signals with external clock circuits. It is typically used when it is necessary to synchronize CobraNet clocks with existing external clock circuitry. When operating in this mode: • As Conductor: MCLK, FS1, and SCLK are all generated as in 0x00 Mode. However, the REFCLK input is used to align the clock edges of the generated MCLK, insuring that the audio clocks generated externally are kept in sync with the CobraNet interface's audio clocks. This mode does not alter the clock frequency and implies that the REFCLK input should be derived from the MCLK_OUT supplied by the CobraNet interface (see Figure 6). • As Performer: MCLK is generated by the VXCO, which receives frequency adjustments from the beat packets received over the network interface as in 0x00 Mode. FS1 and SCLK are derived from MCLK. As above in Conductor Mode, the REFCLK input is used to ensure that the external and CobraNet generated audio clocks are in sync. Clock Circuit 24.576 MHz Clock In MCLK_OUT FS1 SCLK FS1 CobraNet Interface REFCLK Figure 6. 0x10 Mode Typical Connections (Sync of CobraNet Clocks with External Clock Circuitry) 4 AN312REV2 AN312 3.1.3 0x01 Mode - External Word Clock External Word Clock Mode allows synchronization of all CobraNet clocks with an externally supplied word clock. The external clock can be any integral division of FS1 from 750 Hz to 48 kHz. This is most often used to synchronize a CobraNet network with a house sync signal whereby the Conductor will supply the network clock and operate in this mode with Performer Nodes operating in 0x00 Mode. When operating in this mode: • As Conductor: The VCXO generating MCLK is steered to synchronize with REFCLK. FS1 and SCLK are derived from MCLK. • As Performer: The VCXO generating MCLK is steered to synchronize with REFCLK. FS1 and SCLK are derived from MCLK. FS1 SCLK MCLK_OUT From house sync CobraNet Interface (External Word Clock Mode) (conductor) REFCLK Figure 7. 0x01 Mode Typical Connection (External Sync Attached to Conductor) Note: Connection used to provide synchronized audio clocks via Ethernet FS1 SCLK MCLK_OUT From house sync CobraNet Interface (External Word Clock Mode) (conductor) REFCLK Figure 8. 0x01 Mode Typical Connection - External Sync AN312REV2 5 AN312 FS1 FS1 SCLK FS1 SCLK CobraNet Interface (External Word Clock Mode) MCLK_OUT SCLK MCLK_OUT REFCLK CobraNet Interface (External Word Clock Mode) CobraNet Interface (External Word Clock Mode) MCLK_OUT REFCLK REFCLK 48 kHz House Sync Figure 9. 0x01 Mode Typical Connection - Synchronization of All Nodes Note: All nodes should be on house synch. MCLK_OUT (master) control DAC VCXO 24.576MHz +/- 100 PPM Clock Out FS1 (word) Audio Clock Generator MCLK MUX MCLK_IN MCLK_SEL SCK (bit) Sample Phase Counter REFCLK_Enable Edge Detect REFCLK_Polarity RST Phase Detector Loop Filter REFCLK Beat MUX Beat Received Clock Config Signal Path Control Path Active Signal Path Hardware FPGA Software Figure 10. Mode 0x01 Clock Circuit Used with CM-1 Modules 6 AN312REV2 AN312 M C L K _ O U T (m a s te r) c o n tro l DAC VCXO 2 4 .5 7 6 M H z + /- 1 0 0 P P M C lo c k O ut F S 1 (w o rd ) A u d io C lo c k G e n e ra to r M C LK MUX M C L K _ IN S C K (b it) S a m p le Phase C o u n te r P hase D e te c to r M C LK_SEL Loop F ilte r R E FC LK Beat MUX B e a t R e c e iv e d C lo c k C o n fig S ig n a l P a th C o n tro l P a th E x te rn a l H a rd w a re A c tiv e S ig n a l P th C o b ra N e t P ro c e s s o r S o ftw a re Figure 11. Clock Circuit as Used by Mode 0x01 with CM-2 and Semiconductors 3.1.4 0x04 Mode - External Master Clock In External Master Clock Mode, all clocks are derived from an externally supplied master clock of 24.576 MHz. This mode is provided because it is easy to accomplish using the existing clock circuitry. It is most useful when trying to synchronize one or more CobraNet devices to a distributed Master Clock. However, it has little practical utility because it is difficult to properly distribute a clock of this frequency and does not provide a means to ensure synchronization of the audio clocks (SCLK, FS1). Note that MCLK_OUT is not a copy of MCLK_IN. MCLK_OUT is derived from the VCXO, which is not controlled in this mode and is not synchronous with the supplied MCLK_IN. When operating in this mode: • As Conductor: MCLK is sourced directly from MCLK_IN. FS1 and SCLK are derived from MCLK_IN. • As Performer: MCLK is sourced directly from MCLK_IN. FS1 and SCLK are derived from MCLK_IN. FS1 (LR clock) SCLK (Bit clock) 24.576 MHz CobraNet Interface MCLK_IN Figure 12. 0x04 Mode Typical Connection (Synchronization to an Externally-Supplied Master Clock) AN312REV2 7 AN312 M C LK_O UT (m aster) control DAC VCXO 24.576M Hz +/- 100 PPM Clock O ut FS1 (word) Audio C lock G enerator M CLK M UX M C LK_IN M C LK_SEL SCK (bit) Sam ple Phase Counter R EFC LK_Enable Edge D etect R EFC LK _Polarity R ST Phase D etector Loop Filter REFCLK Beat MUX Beat Received C lock C onfig Signal Path Control Path H ardware Active Signal Path FPG A Software Figure 13. Clock Circuit as Used by Mode 0x04 with CM-1 Module M C L K _ O U T (m a s te r) c o n tro l DAC VCXO 2 4 .5 7 6 M H z + /- 1 0 0 P P M C lo c k O ut F S 1 (w o rd ) A u d io C lo c k G e n e ra to r M C LK MUX M C L K _ IN S C K (b it) S a m p le P hase C o u n te r Phase D e te c to r M C LK _S EL Loop F ilte r R E FC LK Beat MUX B e a t R e c e iv e d C lo c k C o n fig S ig n a l P a th C o n tro l P a th A c tiv e S ig n a l P a th E x te rn a l H a rd w a re C o b ra N e t P ro c e s s o r S o ftw a re Figure 14. Clock Circuit as Used by Mode 0x04 with CM-2 and Semiconductors 8 AN312REV2 AN312 3.1.5 0x14 Mode - External Master Clock with External Sample Clock Synchronization Note: This mode operates differently depending on use of the CM-1 or CM-2 CS1810xx/CS4961xx chip-based products. 3.1.5.1 0x14 Mode for CM-1 In this mode, all clocks are derived from an externally supplied master clock of 24.576 MHz. This mode is provided primarily to allow synchronization of multiple CobraNet interfaces within the same chassis. It can also be used, as in 0x10 Mode, to synchronize external clock circuitry derived from an external master clock. Note that MCLK_OUT is generated by the VCXO in this mode and is not a copy of MCLK_IN. When operating in this mode: • As Conductor: MCLK is supplied by the MCLK_IN input. FS1 and SCLK are derived from MCLK_IN. As in 0x10 Mode, REFCLK is used to synchronize the clocks. • As Performer: MCLK is supplied by the MCLK_IN input. FS1 and SCLK are derived from MCLK_IN. As in 0x10 Mode, REFCLK is used to synchronize the clocks. FS1 (LR clock) SCLK (Bit clock) CobraNet Interface 24.576 MHz MCLK_IN LR Clock REFCLK Figure 15. 0x14 Mode Typical Connection (Synchronization to an Externally-Supplied Master Clock and Word Clock when Using CM-1) AN312REV2 9 AN312 FS1 (LR clock) MCLK_OUT 24.576 MHz CobraNet Interface (Master) Typically Mode 0x00 SCLK (Bit clock) FS1 FS1 (LR clock) FS1 (LR clock) SCLK (Bit clock) SCLK (Bit clock) CobraNet Interface (Slave) Mode 0x14 MCLK_IN CobraNet Interface (Slave) Mode 0x14 MCLK_IN REFCLK REFCLK Figure 16. 0x14 Mode Typical Connection (Master and Reference Clock Supplied to Slave Interfaces within Same Chassis when Using CM-1) M C LK_O U T (m aster) control D AC VC XO 24.576 M H z +/- 100 PPM C lock O ut FS1 (w ord) Audio Clock G enerator M CLK MUX M C LK_IN M CLK_SEL SC K (bit) Sam ple Phase C ounter R EFCLK_Enable Edge Detect R EFC LK_Polarity R ST Phase D etector Loop Filter R EFCLK Beat MUX Beat R eceived C lock Config Signal Path C ontrol Path Active Signal Path H ardw are FPG A Softw are Figure 17. Clock Circuit as Used by Mode 0x14 with CM-1 Module 10 AN312REV2 AN312 3.1.6 0x14 Mode for CM-2/CS1810xx/CS4961xx-Based Devices Note: The 0x14 clock mode only works with devices running Rev. 2.11.6 firmware or later. Mode 0x14 for CM-2 and CobraNet chips is primarily intended to allow complete audio clock slaving of one or more CobraNet devices to a master CobraNet device within the same chassis. MCLK, SCLK, and FS1 are all supplied to the slave device by the master device. External divide by 2 logic must also be used on DAI1_SCLK when using 16x16 channel chips. Changing to this mode dynamically has not proven to work well consistently. The CNCustom firmware modification program should be used to create slave device firmware with the Conductor and Performer clock modes set to values of 0x14 so that the slave device(s) will boot up in mode 0x14. The hardware should be designed so that the slave device(s) will always be supplied by all required clocks and will always operate in mode 0x14. The internal clock circuitry for the master device will be as that shown and described elsewhere in this document for the master clock mode in use. A description of the internal clock circuitry is not applicable for the slave device(s) as all clocks are supplied to them directly. 24.576 MHz VCXO MCLK_IN (8) MCLK_IN (8) 3.072 / 6.144 MHz DAO1_SCLK (20) DAI1_SCLK (137) DAO1_SCLK (20) DAI1_SCLK (137) 48 / 96 kHz DAO1_LRCLK (22) DAI1_LRCLK (138) DAO1_LRCLK (22) DAI1_LRCLK (138) CobraNet Interface (Slave) Mode 0x14 CobraNet Interface (Master) (Typically Mode 0) Figure 18. Clock Circuit as Used by Mode 0x14 with CM-2 or Chips with 2x2 or 8x8 Audio Channels VCXO DAO1_SCLK (20) 24.576 MHz 6.144 MHz DAI1_SCLK (137) /2 MCLK_IN (8) DAO1_LRCLK (22) DAI1_LRCLK (138) DAO2_LRCLK (14) CobraNet Interface (Master) (Typically Mode 0) 3.072 MHz 96 kHz 48 kHz MCLK_IN (8) DAO1_SCLK (20) DAI1_SCLK (137) DAO2_SCLK (12) DAO1_LRCLK (22) DAI1_LRCLK (138) DAO2_LRCLK (14) CobraNet Interface (Slave) Mode 0x14 Figure 19. Clock Circuit as Used by Mode 0x14 with CM-2 or Chips with 16x16 Audio Channels AN312REV2 11 AN312 4. USING 0x10 MODE WITH CS1810XX, CS4961XX OR CM-2 0x10 Mode is used when the designer wishes to synchronize the CobraNet clocks with an externally supplied word clock (FS1). This is not possible with CM-2 and Silicon-based designs. The best that can be achieved is to use the circuitry below to ensure that the audio clocks of the CobraNet interface are in phase with the audio clocks of the existing circuit. In this case, the master clock is derived from the CobraNet device by using the circuitry shown in Figure 20, with the interface set to operate in clock mode 0x00. Any clocks required by the design can be taken from the loadable counter taps, and these clocks will be in phase with the audio clocks (FS1 and SCLK) generated by the CobraNet device. The Data In load value can be adjusted to ensure phase alignment if necessary. Load AND D Q Loadable Counter Q D D Flop D Flop Clock In Clock In FS1 CobraNet Interface MCLK_OUT Clock In 24.576 MHz Data In SCLK = 0x002 FS1 Figure 20. 0x10 Mode Circuitry for Use with CM-2, CS1810xx or CS4961xx 5. REFERENCES 1. CobraNet Programmer's Reference Manual, http://www.cirrus.com 2. CobraNet Hardware User's Manual, http://www.cirrus.com 12 AN312REV2 AN312 6. REVISION HISTORY Release Changes Revision 1 Initial Release. Revision 2 Added more detail to Figures 18 and 19. Clarified language in Section 3.1.6 on page 11. AN312REV2 13 AN312 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs and CobraNet are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 14 AN312REV2