DCR490J65 Phase Control Thyristor DS5830-3 June 2014 (LN31677) KEY PARAMETERS FEATURES Double Side Cooling High Surge Capability VDRM IT(AV) ITSM dV/dt* dI/dt 6500V 490A 6600A 1500V/µs 200A/us * Higher dV/dt selections available APPLICATIONS High Power Drives High Voltage Power Supplies Static Switches VOLTAGE RATINGS Part and Ordering Number Repetitive Peak Voltages VDRM and VRRM V DCR490J65* DCR490J60 DCR490J55 6500 6000 5500 Conditions Tvj = -40°C to 125°C, IDRM = IRRM = 100mA, VDRM, VRRM tp = 10ms, VDSM & VRSM = VDRM & VRRM + 100V respectively Lower voltage grades available. 0 0 *6200V @ -40 C, 6500V @ 0 C ORDERING INFORMATION Outline type code: J (See Package Details for further information) Fig. 1 Package outline When ordering, select the required part number shown in the Voltage Ratings selection table. For example: DCR490J65 Note: Please use the complete part number when ordering and quote this number in any future correspondence relating to your order. 1/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR CURRENT RATINGS Tcase = 60°C unless stated otherwise Symbol Parameter Test Conditions Max. Units 490 A Double Side Cooled IT(AV) Mean on-state current IT(RMS) RMS value - 770 A Continuous (direct) on-state current - 730 A IT Half wave resistive load SURGE RATINGS Symbol ITSM 2 It Parameter Surge (non-repetitive) on-state current Test Conditions Max. Units 10ms half sine, Tcase = 125°C 6.6 kA VR = 0 0.22 MA s Min. Max. Units 2 I t for fusing 2 THERMAL AND MECHANICAL RATINGS Symbol Rth(j-c) Rth(c-h) Parameter Thermal resistance – junction to case Thermal resistance – case to heatsink Test Conditions Double side cooled DC - 0.0379 °C/W Single side cooled Anode DC - 0.0745 °C/W Cathode DC - 0.0797 °C/W Double side - 0.0072 °C/W - .0144 °C/W - 125 °C Clamping force 11.5kN (with mounting compound) Blocking VDRM / VRRM Single side Tvj Virtual junction temperature Tstg Storage temperature range -55 125 °C Fm Clamping force 10 13 kN 2/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR DYNAMIC CHARACTERISTICS Symbol IRRM/IDRM Parameter Test Conditions Min. Max. Units Peak reverse and off-state current At VRRM/VDRM, Tcase = 125°C - 100 mA dV/dt Max. linear rate of rise of off-state voltage To 67% VDRM, Tj = 125°C, gate open - 1500 V/µs dI/dt Rate of rise of on-state current From 67% VDRM to 2x IT(AV) Repetitive 50Hz - 100 A/µs Gate source 30V, 10, Non-repetitive - 200 A/µs tr < 0.5µs, Tj = 125°C VT(TO) rT tgd Threshold voltage – Low level 50A to 400A at Tcase = 125°C - 0.912 V Threshold voltage – High level 400A to 1600A at Tcase = 125°C - 1.108 V On-state slope resistance – Low level 50A to 400A at Tcase = 125°C - 2.157 m On-state slope resistance – High level 400A to 1600A at Tcase = 125°C - 1.647 m VD = 67% VDRM, gate source 30V, 10 - 3 µs 550 1100 µs Delay time tr = 0.5µs, Tj = 25°C tq Turn-off time IT = 500A,Tj = 125°C, VR = 100V, dI/dt = 5A/µs, dVDR/dt = 20V/µs linear QS Stored charge IT = 500A, Tj = 125°C, dI/dt = 5A/µs, 1800 2600 µC IRR Reverse recovery current IT = 500A, Tj = 125°C, dI/dt = 5A/µs, 77 90 A IL Latching current Tj = 25°C, VD = 5V - 3 A IH Holding current Tj = 25°C, RG-K = , ITM = 500A, IT = 5A - 300 mA 3/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR GATE TRIGGER CHARACTERISTICS AND RATINGS Symbol Parameter Test Conditions Max. Units VGT Gate trigger voltage VDRM = 5V, Tcase = 25°C 1.5 V VGD Gate non-trigger voltage At 50% VDRM, Tcase = 125°C 0.4 V IGT Gate trigger current VDRM = 5V, Tcase = 25°C 350 mA IGD Gate non-trigger current At 50% VDRM, Tcase = 125°C 15 mA CURVES Instantaneous on-state current, IT - (A) 1600 1200 800 25°C min 25°C max 125°C min 125°C max 400 0 1.0 2.0 3.0 4.0 Instantaneous on-state voltage, VT - (V) Fig.2 Maximum & minimum on-state characteristics VTM EQUATION VTM = A + Bln (IT) + C.IT+D.IT Where A = 0.542452 B = 0.065613 C = 0.001318 D = 0.015356 these values are valid for Tj = 125°C for IT 50A to 1600A 4/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR 130 15 120 Maximum case temperature, T case ( oC ) 16 Mean power dissipation - (kW) 14 13 12 11 10 9 8 7 180 120 90 60 30 6 5 4 3 2 110 100 90 80 70 60 50 40 30 20 10 1 0 0 0 500 1000 1500 0 2000 100 200 300 400 500 600 700 800 Mean on-state current, IT(AV) - (A) Mean on-state current, IT(AV) - (A) Fig.3 On-state power dissipation – sine wave Fig.4 Maximum permissible case temperature, double side cooled – sine wave 130 180 120 90 60 30 120 110 100 12 11 Mean power dissipation - (kW) Maximum heatsink temperature, T Heatsink - ( oC ) 180 120 90 60 30 90 80 70 60 50 40 30 20 10 10 9 8 7 6 5 d.c. 180 120 90 60 30 4 3 2 1 0 0 100 200 300 400 500 600 700 Mean on-state current, IT(AV) - (A) Fig.5 Maximum permissible heatsink temperature, double side cooled – sine wave 0 0 500 1000 1500 2000 2500 Mean on-state current, IT(AV) - (A) Fig.6 On-state power dissipation – rectangular wave 5/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR 130 d.c. 180 120 90 60 30 120 110 100 d.c. 180 120 90 60 30 120 Maximum heatsik temperature Theatsink - (oC) Maximum permissible case temperature , Tcase - (°C) 130 90 80 70 60 50 40 30 20 10 110 100 90 80 70 60 50 40 30 20 10 0 0 200 400 600 800 1000 0 1200 0 Mean on-state current, IT(AV) - (A) 200 400 Fig.7 Maximum permissible case temperature, double side cooled – rectangular wave 1000 Anode side cooled Cathode side cooled Anode Cooled 2 9.3503 3 10.6963 0.0087759 0.053099 0.4497246 1.395 2.8091 9.5576 11.3564 50.6136 0.0097443 0.0591913 0.4759179 6.5548 2.9507 9.4031 11.0771 56.0405 0.0100391 0.0606056 0.4732916 7.228 Ri (°C/kW) Ti (s) Double Side Cooled 1 2.4256 Ri (°C/kW) Ti (s) 90 Thermal impedance -Zth ( °C/kW ) 800 Fig.8 Maximum permissible heatsink temperature, double side cooled – rectangular wave Double side cooled 80 600 Mean on-state current, IT(AV) - (A) Ri (°C/kW) Ti (s) 4 15.3758 i 4 70 Zth [Ri (1 exp(T / Ti )] Cathode Cooled Zth = 60 [Ri x ( 1-exp. (t/ti))] [1] i 1 50 Rth(j-c) Conduction Tables show the increments of thermal resistance R th(j-c) when the device operates at conduction angles other than d.c. 40 30 20 10 0 0.001 0.01 0.1 1 10 100 ° 180 120 90 60 30 15 Double side cooling Zth (z) sine. rect. 4.43 3.01 5.13 4.30 5.89 5.03 6.58 5.81 7.12 6.67 7.36 7.13 ° 180 120 90 60 30 15 Anode Side Cooling Zth (z) sine. rect. 4.39 2.99 5.07 4.26 5.81 4.97 6.48 5.74 7.00 6.57 7.24 7.01 Cathode Sided Cooling Zth (z) sine. rect. ° 180 4.37 2.98 120 5.05 4.25 90 5.79 4.96 60 6.45 5.72 30 6.97 6.54 15 7.20 6.98 Time ( s ) Fig.9 Maximum (limit) transient thermal impedance – junction to case (°C/kW) 6/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR Fig.10 Multi-cycle surge current Fig.11 Single-cycle surge current 7000 180 Reverse recovery current, Irr - (A) Stored Charge, Qs - (uC) 160 Q s max = 2565.9*(di/dt) 0.3569 6000 5000 4000 3000 Q s min = 1572.7*(di/dt) 0.4435 Conditions: Tj = 125°C, V peak ~ 3900V Vrm ~ 2450V snubber as appropriate to control reverse voltage 2000 1000 IRRmax = 38.391*(di/dt) 0.6454 140 120 100 IRRmin = 31.453*(di/dt) 0.691 80 Conditions: Tj = 125°C, V peak ~ 3900V Vrm ~ 2450V snubber as appropriate to control reverse voltage 60 40 20 0 0 0 2 4 6 8 10 Rate of decay of on-state current, di/dt - (A/us) Fig.12 Stored charge vs di/dt 12 0 2 4 6 8 10 12 Rate of decay of on-state current, di/dt - (A/us) Fig.13 Reverse recovery current vs di/dt 7/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR 10 9 Gate trigger voltage, V GT - (V) 8 7 Upper Limit 6 5 Preferred gate drive 4 3 Tj = -40oC 2 Lower Limit Tj = 25oC 1 Tj = 125oC 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Gate trigger current I GT , - (A) Fig14 Gate Characteristics 30 Lower Limit Upper Limit 5W Gate trigger voltage, VGT - (V) 25 10W 20W 50W 20 100W 150W -40C 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 Gate trigger current, I GT - (A) Fig. 15 Gate characteristics 8/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR PACKAGE DETAILS For further package information, please contact Customer Services. All dimensions in mm, unless stated otherwise. DO NOT SCALE. 3rd ANGLE PROJECTION DO NOT SCALE IF IN DOUBT ASK HOLE Ø3.60 X 2.00 DEEP (IN BOTH ELECTRODES) 20° OFFSET (NOM.) TO GATE TUBE Device DCR880J22 DCR780J28 DCR640J42 DCR570J52 DCR490J65 DCR390J85 Maximum Minimum Thickness Thickness (mm) (mm) 34.465 33.915 34.54 33.99 34.77 34.22 34.89 34.34 35.15 34.6 35.51 34.96 Ø57.0 MAX Ø33.95 NOM Ø1.5 CATHODE GATE ANODE Ø33.95 NOM FOR PACKAGE HEIGHT SEE TABLE Clamping force: 11.5 kN ±10% Lead length: 420mm Lead terminal connector: M4 ring Package outline type code: J Fig.16 Package outline 9/10 www.dynexsemi.com DCR490J65 SEMICONDUCTOR IMPORTANT INFORMATION: This publication is provided for information only and not for resale. The products and information in this publication are intended for use by appropriately trained technical personnel. Due to the diversity of product applications, the information contained herein is provided as a general guide only and does not constitute any guarantee of suitability for use in a specific application.The user must evaluate the suitability of the product and the completeness of the product data for the application. The user is responsible for product selection and ensuring all safety and any warning requirements are met. Should additional product information be needed please contact Customer Service. Although we have endeavoured to carefully compile the information in this publication it may contain inaccuracies or typographical errors. The information is provided without any warranty or guarantee of any kind. This publication is an uncontrolled document and is subject to change without notice. When referring to it please ensure that it is the most up to date version and has not been superseded. The products are not intended for use in applications where a failure or malfunction may cause loss of life, injury or damage to property. The user must ensure that appropriate safety precautions are taken to prevent or mitigate the consequences of a product failure or malfunction. The products must not be touched when operating because there is a danger of electrocution or severe burning. Always use protective safety equipment such as appropriate shields for the product and wear safety glasses. Even when disconnected any electric charge remaining in the product must be discharged and allowed to cool before safe handling using protective gloves. Extended exposure to conditions outside the product ratings may affect reliability leading to premature product failure. Use outside the product ratings is likely to cause permanent damage to the product. In extreme conditions, as with all semiconductors, this may include potentially hazardous rupture, a large current to flow or high voltage arcing, resulting in fire or explosion. Appropriate application design and safety precautions should always be followed to protect persons and property. Product Status & Product Ordering: We annotate datasheets in the top right hand corner of the front page, to indicate product status if it is not yet fully approved for production. The annotations are as follows:Target Information: Preliminary Information: No Annotation: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. The product design is complete and final characterisation for volume production is in progress.The datasheet represents the product as it is now understood but details may change. The product has been approved for production and unless otherwise notified by Dynex any product ordered will be supplied to the current version of the data sheet prevailing at the time of our order acknowledgement. All products and materials are sold and services provided subject to Dynex’s conditions of sale, which are available on request. Any brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. HEADQUARTERS OPERATIONS CUSTOMER SERVICE DYNEX SEMICONDUCTOR LIMITED Doddington Road, Lincoln, Lincolnshire, LN6 3LF United Kingdom. Phone: +44 (0) 1522 500500 Fax: +44 (0) 1522 500550 Web: http://www.dynexsemi.com Phone: +44 (0) 1522 502753 / 502901 Fax: +44 (0) 1522 500020 e-mail: [email protected] Dynex Semiconductor Ltd. Technical Documentation – Not for resale. 10/10 www.dynexsemi.com