TM September 2013 • Consumers in the mass market are driving demand for seamless integration of their smart-devices to bring personal content into the vehicle • OEM software costs continue to rise due to increased resource and development needed to support higher level of integration as well as future software upgrade needs • Rearview camera systems in all passenger vehicles driving the need for cost-effective solution to meet upcoming governmental safety mandates • The need to isolate the vehicle from consumer device threats adds an additional layer of complexity to the design of driver information systems TM 2 Gen 3 Portfolio Power Architecture® and ARM® Gap and architecture break Qorivva MPC5645 ARM v7 i.MX6xx Dual/Quad i.MX 6Solo Vybrid R Series Next Gen Cluster / Gauge Cluster / Gauge Qorivva MPC5606 8-,16- and 32bit MCUs 32-bit MCU/MPUs and GPUs based on ARM TM 3 Cluster / Gauge Next Gen Cluster / Gauge Bridge, Scale and Unify i.MX5xx Gen 4 Portfolio Today’s Connected Radio Vybrid Automotive Solutions Collection of discrete ICs • Many external components: MCU, MPU, ADC, DRAM, PMIC • Cost-optimized solution integrates: ─ MCU + MPU ─ Video ADC ─ On-chip SRAM ─ Single 3.3V supply • Additional assembly steps and compromised reliability • Higher total system cost • Improved reliability, fewer components, and reduced system complexity • Simple, cost-effective package TM 4 AUTOMOTIVE Feature Integration VF5xxR - Cortex A5+M4, 400MHz, 364BGA OpenVG, TFT, MLB, USBx2, VideoADC, DDR3 VF3xxR - Cortex A5+M4, 266MHz, 176LQFP OpenVG, TFT , MLB, USB, VideoADC Production Performance TM 5 NEON optimized CODECS/Libraries Cortex-M4 Up to 166MHz 16KB/16KB L1 HMI Tools Comm Stacks Royalty-free RTOS Cortex-A5 Multimedia Connectivity Up to 400MHz NEON/FPU 32KB/32KB L1 Power Management USB OTG + Phy USB OTG + Phy - single 3.3V supply - low voltage reset 1.5MB SRAM CAN x2 System and General Purpose System Connectivity Audio I/O DMA UART/LIN x6 HAB 4.1 Security Tamper Detect ESAI x1 (i2s x6) SPI x3 Watchdog Timer Other Timers (x8) SP/DIF Receiver/Transmitter Media Local Bus 3-wire Real Time Clock Sample Rate Convertor 10/100 Ethernet Pulse Width Modulator GPIO SAI x4 (i2s x4) DRAM (16-bit) LP , DDR3 2x 12-bit SAR ADC Dual Quad-SPI Flash (SDR and DDR) 2x 12-bit DAC With Tone Generation Segment Display Controller (4x40) Internal Temperature Monitor TM • Display I/O 2D-ACE x2 Animation &Comp Engine OpenVG GPU (GC355) External Memory • eMMC/SD x2 I2C x4 NAND/NOR Flash 8/16b • • • Camera Input, 18-bit + Composite (4 to 1)) 6 Unique dual-core architecture with apps processor to run highlevel OS (i.e. Linux) and control processor to run RTOS (i.e. MQX) Ability to segment tasks that need predictable latencies to execute on the M4 and execute graphical and connectivity tasks on A5 Secure boot and cryptographic algorithm acceleration for sensitive applications Multimedia hardware IP that offloads pixels processing from the cores Real time sub-system including PWM and ADC for motor control AUTOMOTIVE Feature TM 3xxR Family 5xxR Family CPU 266MHz Cortex-A5 133MHz Cortex-M4 400MHz Cortex-A5 133MHz Cortex-M4 On-chip memory 1.5MB (512K ECC) 1.5MB (512K ECC) OR 1MB & 512K L2 cache Serial Flash interface Dual QuadSPI Dual QuadSPI NAND Yes (8-bit) Up to 32-bit HW ECC Yes (16-bit) Up to 32-bit HW ECC FlexBus interface (parallel NOR) Yes (addr / data mux’d) Yes, (addr / data mux’d plus 8-bit dedicated data) DRAM interface No 16-bit LPDDR2/DDR3 Display interface TFT & 40x4 Segmented LCD OR 2x TFT up to WQVGA TFT & 40x4 Segmented LCD OR 2x TFT up to WVGA Video ADC / Camera Input 2x Composite 24-bit parallel 4x Composite 24-bit parallel 10/100 Ethernet w/ IEEE1588 1 2 10-channel 12-bit ADC Yes Yes USB 1x USB OTG HS 2x USB OTG HS Audio interface SAI x3 (i2s x3) ESAI x1 (2 Tx, 4 Tx or Rx) SAI x4 (i2s x4) ESAI x1 (2 Tx, 4 Tx or Rx) UART, DSPI, I2C 4, 3, 4 6, 4, 4 SD/MMC interface 1 2 CAN 2x FlexCAN 2x FlexCAN MOST 1x MLB50 1x MLB50 GPIO Up to 115 Up to 136 Package 176LQFP 364BGA 7 AUTOMOTIVE S V F 3 1 1 R 3 K1 C MK 2 Speed (A5 core) 2 = 266MHz 4 = 400MHz Qualification Status P = engineering samples S = automotive qualified Brand: V = Vybrid Package KU = 176LQFP MK = 364BGA Series: F = current Family 3 = Standard 5 = Advanced Temp Spec C = -40 to +85C Ta Core 1 = Cortex A5 2 = Cortex A5 + M4 3 = M4 Primary Graphics 1 = No Open VG 2 = Open VG Revision K1 = Rev 1.1 Memory Option 3 = Standard (1.5MB SRAM) 2 = Optional (1MB SRAM and 512K L2 Cache) Version R = Auto Not all combinations are available. Please refer to part number list TM 8 AUTOMOTIVE Part Number Sample Part Number (Superset) Package SVF311R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, 176LQFP-EP SVF312R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, OpenVG GPU, 176LQFP-EP SVF321R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4, 176LQFP-EP SVF322R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4, OpenVG GPU, 176LQFP-EP SVF332R3K1CKU2 PVF332R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4 Primary, OpenVG GPU, 176LQFPEP SVF511R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, 364BGA SVF512R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, OpenVG GPU, 364BGA SVF521R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4, 364BGA SVF522R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4, OpenVG GPU, 364BGA SVF532R3K1CMK4 PVF532R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, OpenVG GPU, 364BGA SVF522R2K1CMK4 N/A MAP 364 17*17*1.5 P0.8 A5-400, M4, L2 Cache, OpenVG GPU, 364BGA Description Part numbers highlighted bold are supersets TM 9 OpenVG GPU • • • • • 2D-ACE (DCU) • 2D Graphics Accelerator Accelerates cluster needles at 60fps Rendering of true-type fonts with 16x AA Warping for Head Up Display applications Graphics acceleration for dual display systems • • • TM Display controller with 2D acceleration features 6 layer blend & 64 layer support Enables low memory footprint GFx Inline Run Length Encode VideoADC • • • • • Composite Video (CVBS) Decoder & AFE PAL / NTSC Y/C Separation 2D Comb Filtering Interfaces to VIU3 for VIU3 • • • • • 10 Digital Video Interface Supports ITU656, RGB, YUV input formats Image Up/Downscaling Video Deinterlacing Brightness and contrast adjustment QuadSPI • • • • • Serial Flash Controller. 66MHz Dual DDR serial flash interface: 133MByte/sec Flexible buffering Support for multiple flash vendors Graphics storage and eXecute-inPlace (XIP) 1. Cost-optimized for Connected Radios − − − QFP-versions for lower board costs/complexity On-chip SRAM and RTOS option for running without DRAM Market specific integration 2. Added value through software and enablement − − “Foundation” software suite (productiongrade/terms) provided Pre-integrated/tested software “accessories” available from Freescale 3. 2D Animation & Composition Engine (2D-ACE) − − − Dramatically reduces VRAM requirements for large color displays Delivers 60fps animation w/ very low CPU load 2D GPU for line-drawing, transformations, raster ops 4. Cortex A5 CPU & peripheral reuse enables scalability to i.MX6 family TM 11 Ideal as connected, displaybased radio and graphics processor for cluster and Multi-Function Display Delivers eye-catching graphics with very efficient use of system resources • • • • • MCU handles CAN + system wake-up MPU/DSP for Media Connectivity/Display/ UI Radio DSP for radio baseband & Audio I/O Add-on modules for DAB / HD Radio External ADC for analog back-up camera TM •Board Space •PCB Complexity •Cost of components 12 • • • • • • Vybrid handles all connectivity, media playback, vehicle communications and power-up/down with A5 + M4 architecture No ext DRAM for many use-cases No need for complex PMIC No external Video ADC Radio DSP for radio baseband & Audio I/O Add-on modules for DAB / HD Radio TM •Reduce PCB size and Complexity •Fewer components •Production Grade Connectivity SW 13 TM • • Impresario is a Connected Radio software platform targeted for the Vybrid. The platform is made up of functional blocks to deliver automotive connected radio functionality Scalable feature set from Entry Level to Advanced solutions. Customer Application Impresario API Impresario Middleware OS (MQX/Linux) Drivers Vybrid Silicon TM 15 The Connected Radio software platform is being developed for the Faraday silicon. The platform is made up of functional blocks to deliver automotive connected radio functionality. • Multimedia Framework with Radio Tuner and CD Support − Support • • • • • for industry standard audio CODECs CE Device Connectivity (iAP, USB, SD) HMI Framework Bluetooth Stack and Profiles with AEC/NS (HFP, A2DP, AVRCP) Automotive Communication Stacks (CAN, LIN, MOST) Advanced Connected Radio Functionality − Text to Speech − Speech Recognition − MirrorLink / iPod Out TM 16 Which Operating Systems will be supported? − The Connected Radio platform leverages the Freescale Operating System Abstraction layer to provide a Connected Radio Platform on MQX and Linux* − Through extensions to the OSA, Connected Radio can be modified to work with any modern operating system that supports common OS primitives (memory management, signals, mutexes, etc) TM 17 • Underpinned by Freescale MQX and Linux platform support and Commercial terms − Standard Warranty and Indemnification − Available Support and Maintenance • CE Device Connectivity (iPhone, USB, SD) • HMI Framework optimized for on-chip graphics resources (2D-ACE, OpenVG GPU) • Multimedia Framework with Radio Tuner and CD Player • Bluetooth Stack and Profiles • Automotive Communication Stacks • Advanced Connected Radio Functionality − Text to Speech, Speech Recognition − iPod Out, Terminal Mode TM 18 Which hardware will the Connected Radio platform support? − Production level code with full peripheral support will be available only on the Faraday reference hardware Which Compilers will the Connected Radio platform support? − Connected Radio will provide support for the following compilers − GNU Support for porting of Connected Radio to a new compiler can be provided by the Freescale Professional Services Team TM 19 • Pre-integrated key technologies from industry-leading partners help you get to market faster • Proven, tested, production-ready code ready for evaluation and integration • Specifically optimized for Vybrid performance and memory footprint • Partners for HMI tools, Bluetooth, and AEC/NS TM 20 Sybase iAnywhere Cybercom blueGO Alango Technologies • Bluetooth protocol stack Bluetooth software framework Voice Communication Package • Industry leader in Bluetooth and active SIG leadership • Multi-profile Bluetooth SW application framework • Signal processing enabling high quality voice communications • Certified Bluetooth compliance with 12 years of maturity • “We love making Bluetooth easy” • AEC / NS TM 21 − Acoustic Echo Canceller − Noise Suppressor TM 22 • The 2D-ACE is an advanced graphics control module that directly drives an external TFT LCD − Allows full flexibility of TFT display sizes − Fetches bit-mapped “sprites” from on-chip or off-chip memory and places them on graphic layers − Blends the layers using − Has support for a cursor separate from the “sprite” graphics − Supports multiple graphic formats in RGB and YUV format and with and without alpha and run length encoding 16bpp RGB565, RGB1555, RGB4444, 24bpp RGB888 and 32bpp ARGB8888 Indexed colors with variable bit depths from 1 bit per pixel (bpp) to 8bpp and APAL8 YUV format - YCbCr422 − Adjusts the gamma of the graphics to match the TFT in use and dither pixel colors on panels with less than 24-bit color − Displays a test signal to allow calibration of panel and system test TM 23 Static objects Any memory eDMA Dynamic objects RAM Any Anymemory memory GPU RAM RAM 64 obj 2D-ACE Color conv pre blend. RLE exp. 32bpp Animate. Alpha, Pos, Obj … TM Blend Color key • Pipelined operation up to 90MHz pixel clock • Memory size optimized • Per obj. ani. frame rate Dither. Gamma corr CRC check 6 planes 24 • The DCU combines layers or “sprites” to create the final content − − − − − There are up to 66 different sources of content possible 64 programmable layers that contain source graphics A cursor layer 1 layer as a default color for the background Layers are in a fixed priority to each other For each pixel position the DCU fetches a pixel from the topmost layer placed there AND a pixel from the next layer in the priority and pixels from up to four further layers (dependent on user configuration) If indexed colors are used these are converted to 32bpp before processing The fetched pixels are then blended to give the display content for that position. − − The blending attributes are determined per layer and the lowest priority pixel’s blending attributes are ignore Each resulting pixel can be gamma corrected The output format is 8-bits per channel(24bpp) TM 25 • A layer is the mechanism by which graphics are displayed on the panel • The DCU has a set of 9 registers to configure each layer • The layer registers configure − Height & width of layer (pixels) − Signed position on panel (x,y) − Pointer to graphic (32-bit) − Graphic coding (bpp) & CLUT, blending, type, tile & safety − Chroma limits (max & min) − Tile size − Transparency mode colors TM x 26 y TM 27 Layer 20: 16x480 (0,0) YCbCr Alpha:100% Serial flash TM 28 Layer 20: 800x480 (0,0) YCbCr Alpha:100% Tile size: 16x480 Serial flash TM 29 Layer 12: 800x430 (0,50) 8BPP Alpha:100% Simple chroma DRAM TM 30 Layer 10: 52x34 (350,70) 4BPP Alpha:100% SRAM TM 31 Layer 9: 60x60 (80,348) 8BPP Alpha:100% Simple Chroma SRAM TM Layer 8: 80x80 (100,350) 8BPP Alpha:100% Simple Chroma Serial flash 32 Layer 6: 40x40 (400,30) 4BPP Alpha:100% Simple Chroma DRAM Layer 6: 40x40 (5,120) 4BPP Alpha:100% Simple Chroma Serial flash TM 33 TM 34 TM 35 • Full fixed function hardware vector graphics GPU • Hardware Tessellation Minimum CPU involvement • • • • • • • 16X FSAA Photorealistic quality No performance degradation Multi-format rendering sRGB color transformation Video image conversion • High-quality vector font rendering support • Dedicated GPU for QoS requirements TM 36 • • • Vector graphics are drawn and stored as mathematical vector formulae Each vector and fill is assigned a color value, instead of assigning color to each separate pixel A black circle can be represented as: = r cos θ y = r sin θ or: − r2 = x2+ y2 − With color value 0000 for black −x • Benefits – – – Infinitely scalable Independent of screen resolution Saves data memory TM 37 GC355 GPU Core • Fully HW accelerated OpenVG pipeline − − − − − − − − • − − Memory Controller Graphics Pipeline Front End Vector Graphics Pipeline Vector Graphics Engine Imaging Engine VG Pixel Engine Entire OpenVG pipeline hardware accelerated Continuous high frame rates; Outstanding 16X MSAA quality, Very low OpenVG CPU driver load Native rendering of true-type fonts, w/16x Anti-Aliasing Additional graphics acceleration for dual display systems Also used in i.MX6D/Q TM AXI Host Interface Benefits: − • Stage 1: Path, Transformation, Stroke, &Paint Stage 2: Stroked Path Generation Stage 3: Transformation Stage 4: Rasterization Stage 5: Clipping and Masking Stage 6: Paint Generation Stage 7: Image Interpolation Stage 8: Blending and Antialiasing AHB 38 The “Video Subsystem” Digital out: YUV888 Video Analogue Front End (AFE) Decoder (VDEC) Mux Analogue In: CVBS Digital Path YUV888,RGBnnn, or ITU656 TM 39 Graphics VIU Memory TFT DCU LCD • Integrated LCD driver with support up to 40 front-planes and 8 back-planes − 160 LCD segments − Adjustable for 3V3 only operation − Operation can continue of stop mode if required • Contrast adjustable in two ways − VLCD control − Contrast adjustment phases for electronic control of contrast • Configurable for a wide range of LCDs − Individual enables for front- and back-plane signals − Bias voltage adjustable − Ability to reconfigure BP and FP signals on the interface to adjust ratio of FP and BP TM 40 TM 41 Simple power supply – No PMIC needed • Only two levels of power sequencing • − Controlled − • by Vybrid via NPN transistor In Low Power modes external NPN is turned off Need regulators for: − 3.3V for main power − 1.5V/.75V for DDR3; 1.2V/0.6V for LPDDR2 − 5V for USB Host TM 42 • Run Mode − High • frequency using PLLs, all peripherals operational Low Power Modes Power Run (LPRUN) Mode – PLLs OFF, Sys clock is 24 MHz − Ultra Low Power Run (ULPRUN) Mode – PLLs OFF, Sys clock is 32 kHz − WAIT Mode – Both the CA5 and CM4 cores are halted − Low Optionally can keep core clocked to debug in WAIT mode Mode – Cores halted, Peripheral clocks are gated off, Optional Regulator Power down, Deep Sleep option − STOP • Power Gated Modes − LPSTOP[3-1] - Peripheral clocks are gated off, power domains are deenergized, and some (or all) SysRam is lost TM 43 Power Mode Current Consumption Run Mode (@ A5=396 MHz, M4=132 MHz) - Full Tower using TWR-LCD-RGB and TWR-SER w/ Ethernet, DDR 600 mA (Measured on 3.3V supply for system) Run Mode (@ A5=396 MHz, M4=132 MHz) - Linux (150 Threads, 24FPS, 63% CPU) using TWR-LCD-RGB + TWR-SER2, DDR 775 mA (Measured on 3.3V supply for system) LPRUN (FIRC; with no PLLs) 16 mA ULPRUN (Slow XOSC) 8 mA STOP (with Well Bias) 4 - 5 mA LPS3 (48K memory retained) 270 uA LPS2 (16K memory retained) 250 uA LPS1 (FIRC disabled, no memory retained) 40 uA TM 44 TM 45 • Vybrid has no onboard flash. In order to store important nonvolatile, constant information we use fuses. • For example: Serial No., MAC Address, Boot information • Various Boot Interfaces Supported − Quad SPI (QSPI[0:1]) − NOR Flash (FlexBus) − SD/eSD/MMC/eMMC − NAND Flash (NFC) − FlexCAN[0:1] − Serial (ESDHC[0:1]) (using Serial Download Protocol) Flash (I2C[0:3]/DSPI[0:3]) (Recovery Boot) − USB − UART[0:3] TM 46 • Various Boot Interfaces Supported − Quad SPI (QSPI[0:1]) − NOR Flash (FlexBus) − SD/eSD/MMC/eMMC − NAND Flash (NFC) − FlexCAN[0:1] − Serial • (ESDHC[0:1]) (using Serial Download Protocol) Flash (I2C[0:3]/DSPI[0:3]) (Recovery Boot) Serial Download Interfaces − USB − UART[0:3] TM 47 BootROM SPI Flash SDCard NAND NOR U-Boot with boot header – u-boot.imx BootROM changes Program Counter to NOR/QuadSPI region. UBoot starts executing there. BootROM retrieves code to SRAM, then change program counter to SRAM for U-Boot to start executing TM QuadSPI Flash 48 • Serial Flash: − − − − • Communications interface between MCU and external flash memory Interface similar to standard SPI but optionally utilises 2 or 4 data lines to transfer Can optionally support DDR to further increase throughput Command driven interface Supports both 24- and 32-bit addressing. Quad Mode SDR Read Command Sequence: TM 49 • Dual QuadSPI architecture supports: − − − − • 2 external Serial Flashes per QuadSPI module SDR and DDR Serial Flash Programmable Sequence Engine for compatibility to any Serial flash Supports XIP (Execute-In-Place) QuadSPI can control 2 x 4-bit serial flashes : − − Accessed separately or…. Parallel mode enabling ‘octal flash’ with data recombination internally in QuadSPI • 66MHz clock => 132MByte/sec peak bandwidth • Flexible Buffering Scheme: − − − − Sub-buffers allocated to specific masters. Master prioritization Pre-fetch capability Suspend & resume for lower priority masters TM 50 TM