Data Sheet - Freescale Semiconductor

Freescale Semiconductor, Inc.
Data Sheet: Technical Data
KV10P48M75
Rev 4, 02/2015
Kinetis V Series KV10, 32/16 KB
Flash
75 MHz Cortex-M0+ Based Microcontroller
The Kinetis V Series KV1x MCU family is the entry point into the
V Series and provides a high-performance, cost-competitive
solution for 3-phase sensorless BLDC and PMSM motor control.
Built upon the ARM® Cortex®-M0+ based core running at 75
MHz with hardware square root and divide capability, it delivers a
35% increase in performance versus comparable MCUs allowing
it to target BLDC as well as PMSM motors.
Additional features include:
• dual 16-bit analog-to-digital controllers (ADCs) sampling at
up to 1.2 MS/s in 12-bit mode.
• multiple motor control timers, up to 32 KB of flash memory
and a comprehensive enablement suite from Freescale
• third-party resources including reference designs, software
libraries and powerful motor configuration tools
Performance
• Up to 75 MHz ARM Cortex-M0+ based core
Memories and memory interfaces
• Up to 32 KB of program flash memory
• Up to 8 KB of RAM
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• 4-channel DMA controller
• SWD interface and Micro Trace buffer
• Bit Manipulation Engine (BME)
• External watchdog timer
• Advanced independent clocked watchdog
• Memory Mapped Divide and Square Root (MMDVSQ)
module
MKV10Z32VLC7
MKV10Z32VFM7
MKV10Z32VLF7
MKV10Z16VLC7
MKV10Z16VFM7
MKV10Z16VLF7
32 QFN
5 x 5 x 0.9 mm Pitch
0.5 mm
32 LQFP
7 x 7 x 1.4 mm Pitch
0.8 mm
48 LQFP
7 x 7 x 1.4 mm Pitch 0.5 mm
Communication interfaces
• One 16-bit SPI module
• One I2C module
• Two UART modules
Timers
• Programmable delay block
• One 6-channel FlexTimer (FTM) for motor control/
general purpose applications
• Two 2-channel FlexTimers (FTM) with quadrature
decoder functionality
• 16-bit low-power timer (LPTMR)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Clocks
• 32 to 40 kHz or 3 to 32 MHz crystal oscillator
• Multipurpose clock generator (MCG) with frequencylocked loop referencing either internal or external
reference clock
Analog modules
• Two 16-bit SAR ADCs
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Security and integrity modules
• 80-bit unique identification (ID) number per chip
• Hardware CRC module
Human-machine interface
• General-purpose I/O
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2014–2015 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MKV10Z32VLC7
32
8
28
MKV10Z32VFM7
32
8
28
MKV10Z32VLF7
32
8
40
MKV10Z16VLC7
16
8
28
MKV10Z16VFM7
16
8
28
MKV10Z16VLF7
16
8
40
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KV10PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV10P48M75RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document
Chip Errata
The chip mask set Errata provides additional or corrective information for KV10Z_1N81H1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
QFN 32-pin: 98ASA00473D1
LQFP 32-pin: 98ASH70029A1
LQFP 48-pin: 98ASH00962A1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Figure 1. KV10 block diagram
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................8
2.2.3 Voltage and current operating behaviors.............9
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications..................................................... 19
2.4.1 Thermal operating requirements......................... 19
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 20
3.1.1 SWD Electricals ..................................................20
3.2 System modules.............................................................. 21
3.3 Clock modules................................................................. 21
3.3.1 MCG specifications..............................................21
3.3.2 Oscillator electrical specifications........................23
3.4 Memories and memory interfaces................................... 25
3.4.1 Flash electrical specifications.............................. 25
3.5 Security and integrity modules........................................ 26
3.6 Analog............................................................................. 27
3.6.1
ADC electrical specifications............................... 27
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Freescale Semiconductor, Inc.
4
5
6
7
8
3.6.2 CMP and 6-bit DAC electrical specifications....... 31
3.6.3 12-bit DAC electrical characteristics....................33
3.7 Timers..............................................................................36
3.8 Communication interfaces............................................... 36
3.8.1 DSPI switching specifications (limited voltage
range).................................................................. 36
3.8.2 DSPI switching specifications (full voltage
range).................................................................. 38
3.8.3 I2C....................................................................... 40
3.8.4 UART...................................................................40
Dimensions............................................................................. 40
4.1 Obtaining package dimensions....................................... 40
Pinout...................................................................................... 41
5.1 Signal Multiplexing and Pin Assignments........................ 41
5.2 KV10 Pinouts................................................................... 43
Ordering parts......................................................................... 46
6.1 Determining valid orderable parts....................................46
Part identification.....................................................................46
7.1 Description.......................................................................47
7.2 Format............................................................................. 47
7.3 Fields............................................................................... 47
7.4 Example...........................................................................47
Terminology and guidelines.................................................... 48
8.1 Definition: Operating requirement....................................48
8.2 Definition: Operating behavior......................................... 48
8.3 Definition: Attribute.......................................................... 48
8.4 Definition: Rating............................................................. 49
8.5 Result of exceeding a rating............................................ 49
8.6 Relationship between ratings and operating
requirements....................................................................50
8.7 Guidelines for ratings and operating requirements..........50
8.8 Definition: Typical value...................................................51
8.9 Typical Value Conditions................................................. 52
9 Revision history.......................................................................52
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human-body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105 °C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
1.4 Voltage and current operating ratings
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Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
VIO
ID
VDDA
0.31
mA
Digital pin input voltage (except open drain pins)
–0.3
VDD +
Open drain pins (PTC6 and PTC7)
–0.3
5.5
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
Analog supply voltage
V
1. Maximum value of VIO (except open drain pins) must be 3.8 V.
2 General
Electromagnetic compatibility (EMC) performance depends on the environment in
which the MCU resides. Board design and layout, circuit topology choices, location,
characteristics of external components, and MCU software operation play a significant
role in EMC performance.
See the following applications notes available on freescale.com for guidelines on
optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
Input Signal
High
Low
VIH
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VIH
VIL
Notes
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
Pin negative DC injection current—single pin
• VIN < VSS–0.3V
1
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IICcont
Description
Contiguous pin DC injection current—regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
VRAM
VDD voltage required to retain RAM
Min.
Max.
Unit
–25
—
mA
1.2
—
V
Notes
1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed, then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/IICIO.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±60
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±40
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
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Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Min.
Max.
Unit
VDD – 0.5
—
V
VDD – 0.5
—
V
VDD – 0.5
—
V
VDD – 0.5
—
V
—
100
mA
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
1
IIN
Input leakage current (total all pins) for full
temperature range
—
41
μA
1
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
VOH
Description
Notes
Output high voltage — Normal drive pad
All port pins, except PTC6 and PTC7
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VOH
Output high voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
IOHT
Output high current total for all ports
VOL
Output low voltage — Normal drive pad
All port pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
VOL
Output low voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
IOLT
2
1. Measured at VDD = 3.6 V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
General
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 75 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
—
—
300
μs
—
106
115
μs
—
106
115
μs
—
47
53
μs
—
4.5
4.8
μs
—
4.5
4.8
μs
Notes
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
2.2.5 Power consumption operating behaviors
NOTE
The maximum values stated in the following table represent
characterized results equivalent to the mean plus six times the
standard deviation (mean + 6 sigma).
Table 5. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
—
—
5
mA
Run mode current — all peripheral clocks
disabled, code executing from flash
• at 1.8 V 50 MHz (25 MHz Bus)
Notes
1
Target IDD
—
5
6.3
mA
Table continues on the next page...
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Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
Table 5. Power consumption operating behaviors (continued)
Symbol
IDD_RUN
Description
Min.
Typ.
Max.
Unit
• at 3.0 V 50 MHz (25 MHz Bus)
—
5
6.3
mA
• at 1.8 V 75 MHz (25 MHz Bus)
• at 3.0 V 75 MHz (25 MHz Bus)
—
6.5
7.8
mA
—
6.5
7.5
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
• at 1.8 V 50 MHz
• at 3.0 V 50 MHz
• at 1.8 V 75 MHz
• at 3.0 V 75 MHz
Notes
Target IDD
—
7.1
8.2
mA
—
7.1
8
mA
—
9.4
10.9
mA
—
9.4
10.6
mA
IDD_WAIT
Wait mode high frequency 75 MHz current at
3.0 V — all peripheral clocks disabled
—
4
5.2
mA
—
IDD_WAIT
Wait mode reduced frequency 50 MHz current
at 3.0 V — all peripheral clocks disabled
—
3.4
4.7
mA
—
IDD_VLPR
Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks disabled
—
215
437
μA
4 MHz
CPU
speed, 1
MHz bus
speed.
IDD_VLPR
Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks enabled
—
313
570
μA
4 MHz
CPU
speed, 1
MHz bus
speed.
IDD_VLPW
Very-Low-Power Wait mode current at 3.0 V —
all peripheral clocks disabled
—
149
303
μA
4 MHz
CPU
speed, 1
MHz bus
speed.
IDD_VLPW
Very-Low-Power Wait mode current at 3.0 V —
all peripheral clocks enabled
—
244
347
μA
4 MHz
CPU
speed, 1
MHz bus
speed.
IDD_STOP
Stop mode current at 3.0 V
• -40 °C to 25 °C
—
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-Low-Power Stop mode current at 3.0 V
• -40 °C to 25 °C
• at 50 °C
—
248
280
—
261
315
—
278
333
—
307
435
—
381
510
μA
—
—
2.2
4.3
—
4.2
9.9
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• at 70 °C
—
8.8
24
μA
• at 85 °C
—
16.2
59
• at 105 °C
—
36.7
82
IDD_VLLS3 Very-Low-Leakage Stop mode 3 current at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-Low-Leakage Stop mode 1 current at 3.0 V
• -40°C to 25°C
• at 50°C
• at 70°C
• at 85°C
• at 105°C
μA
—
1.3
5.7
—
1.9
6.1
—
3.3
7.4
—
5.8
11.2
—
13
18
—
0.8
3.0
—
1.2
4.9
—
2.2
7.0
—
4
12.5
—
9.4
29.0
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
0.279
0.7
—
0.638
1.2
—
1.63
2.5
—
3.4
4.5
—
8.9
12.0
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
0.098
0.485
—
0.448
0.788
—
1.4
2.29
—
3.19
4.14
—
8.47
11.8
Notes
—
μA
—
μA
—
μA
2
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. No brownout
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Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
440
490
540
560
570
580
VLLS1
440
490
540
560
570
580
VLLS3
510
560
560
560
610
680
VLPS
510
560
560
560
610
680
22
22
22
22
22
22
µA
66
66
66
66
66
66
µA
214
237
246
254
260
268
66
66
66
66
66
66
214
237
246
254
260
268
nA
STOP
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
ISPI
SPI peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
II2C
µA
I2C peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
66
66
66
66
66
66
214
237
246
254
260
268
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
IFTM
FTM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
µA
µA
150
150
150
150
150
150
300
300
300
320
340
350
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366
366
366
366
366
366
µA
66
66
66
66
66
66
µA
214
237
246
254
260
268
IWDOG
WDOG peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode (except for 75 MHz which is in FEE mode), and BLPE
for VLPR mode
• No GPIOs toggled
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Run Mode Current vs Core Frequency
Temp (C)=25,VDD=3.6V,CACHE=ENABLE,Code Residence=Flash
10.00E-03
9.00E-03
8.00E-03
Current Consumption on VDD (A)
7.00E-03
6.00E-03
All Peripheral Clk Gates
5.00E-03
ALLOFF
ALLON
4.00E-03
3.00E-03
2.00E-03
1.00E-03
000.00E+00
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-2-2
'1-3-3
1
2
4
6.25
12.5
25
50
75
Clk Ratio
Core-Bus-Flash
Core Freq (Mhz)
Figure 3. Run mode supply current vs. core frequency
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
General
Very Low Power Run (VLPR) Current vs Core Frequency
Temp (C)=25,VDD=3.6V,CACHE=ENABLE,Code Residence=Flash
350.00E-06
300.00E-06
Current Consumption on VDD (A)
250.00E-06
200.00E-06
All Peripheral Clk Gates
ALLOFF
ALLON
150.00E-06
100.00E-06
50.00E-06
000.00E+00
'1-2-2
'1-1-1
1
'1-2-2
'1-4-4
2
4
Clk Ratio
Core-Bus-Flash
Core Freq (Mhz)
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
15
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
17
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
12
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
4
dBμV
IEC level
0.15–1000
M
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
16
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 75 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
48
MHz
fBUS
Bus clock
—
24
MHz
fFLASH
Flash clock
—
24
MHz
fLPTMR
LPTMR clock
—
24
MHz
High Speed run mode
fSYS
System and core clock
—
75
MHz
fBUS
Bus clock
—
25
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
General
Table 9. Device clock specifications (continued)
Symbol
fFTM
Description
FTM clock
Min.
Max.
Unit
—
75
MHz
Notes
VLPR mode
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock
—
25
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
—
16
MHz
—
16
MHz
fLPTMR_pin
fLPTMR_ERCL LPTMR external reference clock
K
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
3
Fast slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
—
8
ns
—
7
ns
—
15
ns
—
25
ns
Port rise and fall time
Slow slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (low drive) is 25pF.
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
General
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
NOTE
Maximum TA can be exceeded only if the user ensures that
TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + θJA x chip power dissipation.
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type
Symbol
Description
48 LQFP 32 LQFP
32 QFN
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to
ambient (natural convection)
81
85
98
°C/W
1
Four-layer (2s2p)
RθJA
Thermal resistance, junction to
ambient (natural convection)
57
57
34
°C/W
Single-layer (1S)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
68
72
82
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
51
50
28
°C/W
—
RθJB
Thermal resistance, junction to
board
35
33
14
°C/W
2
—
RθJC
Thermal resistance, junction to
case
25
25
2.5
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
7
7
8
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD Electricals
Table 13. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 5. Serial wire clock input timing
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Notes
1
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Δfdco_t
Δfdco_t
fintf_ft
Δfintf_ft
fintf_t
Min.
Typ.
Max.
Unit
Notes
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0 - 70 °C
—
± 0.4
± 1.5
%fdco
1, 2
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
4
—
MHz
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±3
%fintf_ft
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
48
MHz
60
62.915
75
MHz
—
23.99
—
MHz
2
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS = 00,
DMX32 = 0)
3, 4
640 × ffll_ref
Mid range (DRS = 01,
DMX32 = 0)
1280 × ffll_ref
Mid range (DRS = 10,
DMX32 = 0)
1920 x ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS = 00,
DMX32 = 1)
5
6
732 × ffll_ref
Mid range (DRS = 01,
DMX32 = 1)
—
47.97
—
MHz
–
71.991
–
MHz
—
180
—
ps
7
—
—
1
ms
8
1464 × ffll_ref
Mid range (DRS = 10,
DMX32 = 1)
2197 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 75 MHz
tfll_acquire
FLL target frequency acquisition time
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Peripheral operating requirements and behaviors
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or there is a change from FLL disabled (BLPE, BLPI) to FLL enabled
(FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 4 MHz
—
500
—
μA
• 8 MHz
—
600
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
2, 4
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
RS
Description
Min.
Typ.
Max.
Unit
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Notes
1, 2
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Peripheral operating requirements and behaviors
Table 16. Oscillator frequency specifications (continued)
Symbol
tcst
Description
Min.
Typ.
Max.
Unit
Notes
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 17. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
52
452
ms
1
1. Maximum time based on expectations at cycling end-of-life.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1.2
Flash timing specifications — commands
Table 18. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
ms
—
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3
Flash high voltage current behaviors
Table 19. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 20. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
26
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ADC electrical specifications
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
3.6.1.1
16-bit ADC operating conditions
Table 21. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input
capacitance
• 16-bit mode
—
8
10
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
RADIN
RAS
Input resistance
Analog source
resistance
Notes
kΩ
13-bit / 12-bit modes
3
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
24.0
MHz
4
fADCK
ADC conversion 16-bit mode
clock frequency
2.0
—
12.0
MHz
4
Crate
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
5
20.000
—
1200
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
27
Freescale Semiconductor, Inc.
ADC electrical specifications
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 7. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
ADC
asynchronous
clock source
fADACK
Conditions1.
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
1.2
2.4
3.9
2.4
4.0
6.1
3.0
5.2
7.3
4.4
6.2
9.5
MHz
MHz
MHz
MHz
• ADLPC = 0, ADHSC =
1
Sample Time
tADACK =
1/fADACK
See Reference Manual chapter for sample times
Table continues on the next page...
28
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ADC electrical specifications
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
TUE
DNL
INL
EFS
EQ
ENOB
Description
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN =
VDDA5
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
–1.1 to
+1.9
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
• <12-bit modes
—
±0.5
–0.7 to
+0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• 16-bit modes
—
–1 to 0
—
• ≤13-bit modes
—
—
±0.5
Integral nonlinearity
Full-scale error
Quantization
error
Effective number 16-bit differential mode
of bits
• Avg = 32
• Avg = 4
–0.3 to 0.5
–2.7 to
+1.9
LSB4
6
12.8
14.5
—
bits
11.9
13.8
—
bits
12.2
13.7
—
bits
11.4
13.1
—
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16-bit differential mode
6.02 × ENOB + 1.76
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
7
—
–97
—
dB
—
–91
—
dB
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
EIL
dB
Input leakage
error
7
82
100
—
dB
78
92
—
dB
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
29
Freescale Semiconductor, Inc.
ADC electrical specifications
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Conditions1.
Description
Min.
Typ.2
Max.
Unit
Notes
and
current
operating
ratings)
VTEMP25
Temp sensor
slope
Across the full temperature
range of the device
1.55
1.62
1.69
mV/°C
8
Temp sensor
voltage
25 °C
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode
30
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ADC electrical specifications
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 23. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, high-speed mode (EN = 1, PMODE
= 1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN = 1, PMODE =
0)
—
—
20
μA
VAIN
Analog input voltage
VSS
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator
hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20
35
200
ns
tDLS
Propagation delay, low-speed mode (EN = 1,
PMODE = 0)
80
100
600
ns
Analog comparator initialization delay2
—
—
40
μs
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
31
Freescale Semiconductor, Inc.
ADC electrical specifications
Table 23. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
IDAC6b
Description
6-bit DAC current adder (enabled)
Min.
Typ.
Max.
Unit
—
7
—
μA
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
CMP Hysteresis vs Vinn
90.00E-03
80.00E-03
CMP Hysteresis (V)
70.00E-03
60.00E-03
HYSTCTR
Setting
50.00E-03
0
1
2
3
40.00E-03
30.00E-03
20.00E-03
10.00E-03
000.00E+00
0.1
0.4
0.7
1
1.3
1.6
1.9
Vinn (V)
2.2
2.5
2.8
3.1
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
32
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ADC electrical specifications
CMP Hysteresis vs Vinn
180.00E-03
160.00E-03
CMP Hysteresis (V)
140.00E-03
120.00E-03
HYSTCTR
Setting
100.00E-03
0
1
2
3
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00
0.1
0.4
0.7
1
-20.00E-03
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1
Symbol
12-bit DAC operating requirements
Table 24. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
1
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2
Symbol
12-bit DAC operating behaviors
Table 25. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
—
100
200
μs
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
33
Freescale Semiconductor, Inc.
ADC electrical specifications
Table 25. 12-bit DAC operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
1
—
μs
1
—low-power mode
—
—
5
μs
1
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance (load = 3 kΩ)
—
—
250
SR
Slew rate -80h→ F7Fh→ 80h
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08)—high-speed mode
VOFFSET Offset error
EG
PSRR
BW
6
Ω
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
3dB bandwidth
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
1.
2.
3.
4.
5.
6.
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
34
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Freescale Semiconductor, Inc.
ADC electrical specifications
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 12. Typical INL error vs. digital code
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
35
Freescale Semiconductor, Inc.
ADC electrical specifications
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature °C
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
36
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ADC electrical specifications
3.8.1 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 26. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
17
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS4
DS8
First data
DSPI_SOUT
DS1
DS2
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 14. DSPI classic SPI timing — master mode
Table 27. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
Table continues on the next page...
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
37
Freescale Semiconductor, Inc.
ADC electrical specifications
Table 27. Slave mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
21
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
15
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
15
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 15. DSPI classic SPI timing — slave mode
3.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 28. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
Table continues on the next page...
38
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ADC electrical specifications
Table 28. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
–7.8
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
24
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS1
DS2
DS4
DS8
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 16. DSPI classic SPI timing — master mode
Table 29. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
—
27.5
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.5
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
22
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
22
ns
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
39
Freescale Semiconductor, Inc.
Dimensions
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 17. DSPI classic SPI timing — slave mode
3.8.3 I2C
See General switching specifications.
3.8.4 UART
See General switching specifications.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
32-pin QFN
98ASA00473D
32-pin LQFP
98ASH70029A
48-pin LQFP
98ASH00962A
40
Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Pinout
5 Pinout
5.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, PTD7
are high current pins.
• PTC6 and PTC7 have open drain outputs
48
32
32
LQFP QFN LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
1
1
1
VDD
VDD
VDD
2
2
2
VSS
VSS
VSS
3
3
3
PTE16
ADC0_SE1/
ADC0_DP1/
ADC1_SE0
ADC0_SE1/
ADC0_DP1/
ADC1_SE0
PTE16
SPI0_PCS0/
SS_b
UART1_TX
FTM_CLKIN0
FTM0_FLT3
4
4
4
PTE17
ADC0_SE5/
ADC0_DM1/
ADC1_SE5
ADC0_SE5/
ADC0_DM1/
ADC1_SE5
PTE17
SPI0_SCK
UART1_RX
FTM_CLKIN1
LPTMR0_
ALT3
5
5
5
PTE18
ADC0_SE6/
ADC1_SE1/
ADC1_DP1
ADC0_SE6/
ADC1_SE1/
ADC1_DP1
PTE18
SPI0_SOUT
UART1_
CTS_b
I2C0_SDA
SPI0_SIN
6
6
6
PTE19
ADC0_SE7/
ADC1_SE7/
ADC1_DM1
ADC0_SE7/
ADC1_SE7/
ADC1_DM1
PTE19
SPI0_SIN
UART1_
RTS_b
I2C0_SCL
SPI0_SOUT
7
—
—
PTE20
ADC0_SE0/
ADC0_DP0
ADC0_SE0/
ADC0_DP0
PTE20
FTM1_CH0
UART0_TX
8
—
—
PTE21
ADC0_SE4/
ADC0_DM0
ADC0_SE4/
ADC0_DM0
PTE21
FTM1_CH1
UART0_RX
9
7
7
VDDA
VDDA
VDDA
10
7
7
VREFH
VREFH
VREFH
11
8
8
VREFL
VREFL
VREFL
12
8
8
VSSA
VSSA
VSSA
13
—
—
PTE29
CMP1_IN5/
CMP0_IN5
CMP1_IN5/
CMP0_IN5
PTE29
FTM0_CH2
FTM_CLKIN0
14
9
9
PTE30
ADC1_SE4/
CMP0_IN4/
CMP1_IN4/
DAC0_OUT
ADC1_SE4/
CMP0_IN4/
CMP1_IN4/
DAC0_OUT
PTE30
FTM0_CH3
FTM_CLKIN1
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
ALT7
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Freescale Semiconductor, Inc.
Pinout
48
32
32
LQFP QFN LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
15
10
10
PTE24
DISABLED
PTE24
16
11
11
PTE25
DISABLED
PTE25
17
12
12
PTA0
SWD_CLK
PTA0
UART0_
CTS_b
FTM0_CH5
18
13
13
PTA1
DISABLED
PTA1
UART0_RX
FTM2_CH0
CMP0_OUT
FTM2_QD_
PHA
FTM1_CH1
19
14
14
PTA2
DISABLED
PTA2
UART0_TX
FTM2_CH1
CMP1_OUT
FTM2_QD_
PHB
FTM1_CH0
20
15
15
PTA3
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
FTM2_FLT0
EWM_OUT_b
SWD_DIO
21
16
16
PTA4
NMI_b
PTA4/
LLWU_P3
FTM0_CH1
FTM0_FLT3
NMI_b
22
—
—
VDD
VDD
VDD
23
—
—
VSS
VSS
VSS
24
17
17
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
25
18
18
PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
26
19
19
PTA20
RESET_b
27
20
20
PTB0
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
28
21
21
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
I2C0_SDA
FTM1_CH1
FTM0_FLT2
29
—
—
PTB2
ADC0_SE10/ ADC0_SE10/ PTB2
ADC1_SE10/ ADC1_SE10/
ADC1_DM2 ADC1_DM2
I2C0_SCL
UART0_
RTS_b
FTM0_FLT1
30
—
—
PTB3
ADC1_SE2/
ADC1_DP2
I2C0_SDA
UART0_
CTS_b
31
—
—
PTB16
DISABLED
PTB16
UART0_RX
FTM_CLKIN2
EWM_IN
32
—
—
PTB17
DISABLED
PTB17
UART0_TX
FTM_CLKIN1
EWM_OUT_b
33
—
—
PTC0
ADC1_SE11
ADC1_SE11
PTC0
SPI0_PCS4
PDB0_
EXTRG
34
22
22
PTC1
ADC1_SE3
ADC1_SE3
PTC1/
LLWU_P6
SPI0_PCS3
UART1_
RTS_b
FTM0_CH0
FTM2_CH0
35
23
23
PTC2
ADC0_SE11/ ADC0_SE11/ PTC2
CMP1_IN0
CMP1_IN0
SPI0_PCS2
UART1_
CTS_b
FTM0_CH1
FTM2_CH1
36
24
24
PTC3
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
37
25
25
PTC4
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0/
SS_b
UART1_TX
FTM0_CH3
38
26
26
PTC5
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
39
27
27
PTC6
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
40
28
28
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
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Freescale Semiconductor, Inc.
FTM0_FLT0
FTM0_CH0
I2C0_SCL
EWM_OUT_b
FTM0_CH1
I2C0_SDA
EWM_IN
ALT7
SWD_CLK
LPTMR0_
ALT1
PTA20
ADC1_SE2/
ADC1_DP2
CMP1_IN1
PTB3
RESET_b
EWM_IN
FTM1_QD_
PHA
UART0_RX
FTM1_QD_
PHB
UART0_TX
FTM0_FLT3
FTM0_FLT0
CMP0_OUT
FTM0_FLT0
SPI0_PCS0/
SS_b
CMP1_OUT
CMP0_OUT
FTM0_CH2
UART0_RX
I2C0_SCL
UART0_TX
I2C0_SDA
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Pinout
48
32
32
LQFP QFN LQFP
Pin Name
Default
41
—
—
PTD0
DISABLED
42
—
—
PTD1
ADC0_SE2
43
—
—
PTD2
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
PTD0/
LLWU_P12
SPI0_PCS0/
SS_b
UART0_
CTS_b
FTM0_CH0
UART1_RX
PTD1
SPI0_SCK
UART0_
RTS_b
FTM0_CH1
UART1_TX
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART0_RX
FTM0_CH2
ADC0_SE2
ALT6
I2C0_SCL
44
—
—
PTD3
DISABLED
PTD3
SPI0_SIN
UART0_TX
FTM0_CH3
45
29
29
PTD4
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM0_CH4
FTM2_CH0
EWM_IN
46
30
30
PTD5
ADC0_SE3
ADC0_SE3
PTD5
SPI0_PCS2
UART0_
CTS_b
FTM0_CH5
FTM2_CH1
EWM_OUT_b
47
31
31
PTD6
ADC1_SE6
ADC1_SE6
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH0
FTM1_CH0
FTM0_FLT0
48
32
32
PTD7
DISABLED
UART0_TX
FTM0_CH1
FTM1_CH1
FTM0_FLT1
PTD7
ALT7
I2C0_SDA
5.2 KV10 Pinouts
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6
PTC5
PTC4
48
47
46
45
44
43
42
41
40
39
38
37
Pinout
PTE20
7
30
PTB3
PTE21
8
29
PTB2
VDDA
9
28
PTB1
VREFH
10
27
PTB0
VREFL
11
26
PTA20
VSSA
12
25
PTA19
24
PTB16
PTA18
31
23
6
VSS
PTE19
22
PTB17
VDD
32
21
5
PTA4
PTE18
20
PTC0
PTA3
33
19
4
PTA2
PTE17
18
PTC1
PTA1
34
17
3
PTA0
PTE16
16
PTC2
PTE25
35
15
2
PTE24
VSS
14
PTC3
PTE30
36
13
1
PTE29
VDD
Figure 18. 48 LQFP Pinout Diagram
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
PTD7
PTD6
PTD5
PTD4
PTC7
PTC6
PTC5
PTC4
32
31
30
29
28
27
26
25
Pinout
21
PTB1
PTE18
5
20
PTB0
PTE19
6
19
PTA20
VDDA VREFH
7
18
PTA19
VREFL VSSA
8
17
PTA18
PTE24
PTE30
16
4
PTA4
PTE17
15
PTC1
PTA3
22
14
3
PTA2
PTE16
13
PTC2
PTA1
23
12
2
PTA0
VSS
11
PTC3
PTE25
24
10
1
9
VDD
Figure 19. 32 QFN Pinout Diagram
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
45
Freescale Semiconductor, Inc.
PTD7
PTD6
PTD5
PTD4
PTC7
PTC6
PTC5
PTC4
32
31
30
29
28
27
26
25
Ordering parts
21
PTB1
PTE18
5
20
PTB0
PTE19
6
19
PTA20
VDDA VREFH
7
18
PTA19
VREFL VSSA
8
17
PTA18
PTE24
PTE30
16
4
PTA4
PTE17
15
PTC1
PTA3
22
14
3
PTA2
PTE16
13
PTC2
PTA1
23
12
2
PTA0
VSS
11
PTC3
PTE25
24
10
1
9
VDD
Figure 20. 32 LQFP Pinout Diagram
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the MKV10 device numbers.
7 Part identification
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KV## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KV##
Kinetis family
• KV10
M
Key attribute
• Z = M0+ core
FFF
Program flash memory size
• 32 = 32 KB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
•
•
•
•
•
•
•
•
CCC
Maximum CPU frequency (MHz)
• 7 = 75 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
FK = 24 QFN (4 mm x 4 mm)
LC = 32 LQFP (7 mm x 7 mm)
FM = 32 QFN (5 mm x 5 mm)
LF = 48 LQFP (7 mm x 7 mm)
FT = 48 QFN (10 mm x 10 mm)
LH = 64 LQFP (10 mm x 10 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
7.4 Example
This is an example part number:
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
Terminology and guidelines
MKV10Z32VLF7
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Digital I/O weak pullup/ 10
pulldown current
48
Freescale Semiconductor, Inc.
Min.
Max.
130
Unit
µA
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Terminology and guidelines
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Max.
1.2
Unit
V
49
Freescale Semiconductor, Inc.
Terminology and guidelines
8.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
8.6 Relationship between ratings and operating requirements
g(
g
tin
era
Op
in
rat
i
(m
nt
me
n.)
mi
g
tin
era
Op
n.)
e
uir
req
g
tin
era
Op
t
en
em
uir
q
re
ax
(m
.)
x
ma
g(
g
tin
era
in
rat
.)
Op
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
dli
n
Ha
ng
x.)
n.)
mi
g(
in
rat
li
nd
Ha
ng
a
(m
ing
rat
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
Handling (power off)
∞
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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Freescale Semiconductor, Inc.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
Terminology and guidelines
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Freescale Semiconductor, Inc.
Revision history
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.05
1.00
1.10
VDD (V)
8.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
9 Revision history
The following table provides a revision history for this document.
Table 30. Revision history
Rev. No.
Date
3
02/2014
4
02/2015
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Freescale Semiconductor, Inc.
Substantial Changes
Initial public release
• Updated the section "Power consumption operating behaviors"
• Added a note below the "Thermal operating requirements" table.
Kinetis V Series KV10, 32/16 KB Flash, Rev4, 02/2015.
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Information in this document is provided solely to enable system and
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Freescale reserves the right to make changes without further notice to
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the suitability of its products for any particular purpose, nor does
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including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
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©2014-2015 Freescale Semiconductor, Inc.
Document Number KV10P48M75
Revision 4, 02/2015