RENESAS RD30LDT3595FPH0

RD30LDT3595
24–bit Serial–in Parallel–out LED Driver IC
REJ03D0896-0300
Rev.3.00
Jun 16, 2008
Description
The RD30LDT3595 has twenty-four edge trigger D–type Flip–Flops with twenty-four latches in 36–pin package. Data
is input to the serial data input and the clock pulse is input to the clock input. When the clock is changed from ”L”
to ”H”, the signal of the data input enters an internal shift register. The data of the shift register is shifted one by one. In
addition, output load circuit is added so that power supply prevents a wrong action in on/off. When Vcc is less than a
fixed level, the output (Q1 to Q24) compulsorily is off state. Low–voltage and high–speed operation is suitable for
battery–powered product (e.g., notebook computers), and the low–power consumption extends the battery life.
Features
•
•
•
•
•
•
Supply voltage range : 4.5 to 5.5 V, VO = 30 V
Output current : IO = 100 mA (@VCC = 5 V)
All the logical input has hysteresis voltage for the slow transition.
Input with pull-up resistance. (Enable, Latch terminal)
Input with pull-down resistance. (CLK, S-in terminal)
Ordering Information
Part Name
RD30LDT3595FPH0
Package Type
SSOP-36 pin
REJ03D0896-0300 Rev.3.00 Jun 16, 2008
Page 1 of 6
Package Code
(Previous Code)
PRSP0036GA-A
(36P2R-A)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
H (1,000 pcs/reel)
Surface
Treatment
0 (Sn-Cu)
RD30LDT3595
Pin Arrangement
Enable
1
36 VCC
Q12
2
35 Q13
Q11
3
34 Q14
Q10
4
33 Q15
Q9
5
32 Q16
Q8
6
31 Q17
Q7
7
30 Q18
GND
8
29 GND
GND
9
28 GND
GND 10
27 GND
Q6 11
26 Q19
Q5 12
25 Q20
Q4 13
24 Q21
Q3 14
23 Q22
Q2 15
22 Q23
Q1 16
21 Q24
S-in 17
20 S-out
CLK 18
19 Latch
(Top view)
Logic Diagram
VCC
S-in
CLK
D
L
Q
D
D
L
Q
D
Output wrong action
protection circuit
Q1
CK
Q
VCC
Latch
Q24
VCC
CK
Q
Enable
S-out
REJ03D0896-0300 Rev.3.00 Jun 16, 2008
Page 2 of 6
RD30LDT3595
Function Table
Inputs
S-in
L
L
H
H
H
*1
CLK
IN
IN
IN
IN
IN
*1
Outputs
Enable
L
L
L
L
H
Latch
L
H
L
H
H
Q1 to Q24
t-1
Z
t-1
L
Z
S-out
L
L
H
H
H
IN : Input the following signal in CLK
1
2
23
24
H : High level
L : Low level
Z : High impedance
t - 1 : Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range
Output voltage range *1,
VO
Continuous output current
IO
Ratings
-0.5 to 7
–0.5 to VCC + 0.5
–0.5 to 30
–0.5 to VCC + 0.5
100
Pd
1.9
W
Tstg
–65 to 150
°C
Maximum power dissipation
*2
at Ta = 25°C (in still air)
Storage temperature
Symbol
VCC
VI
Unit
V
V
V
V
mA
Test Conditions
Output : Z (OFF)
S-out
VO = 0 to VCC
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore no two of
which may be realized at the same time.
1. This value is limited to 30 V maximum.
2. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Supply voltage range
Output voltage range
Symbol
VCC
VO
Min
4.5
—
Max
5.5
30
Unit
V
V
Output current (per pin)
IO
—
100
mA
Operating free-air temperature
Ta
–40
85
°C
Note:
Unused or floating inputs must be held high or low.
REJ03D0896-0300 Rev.3.00 Jun 16, 2008
Page 3 of 6
Conditions
Q1 to Q24 : Z (OFF)
Q1 to Q24 : ON
(duty cycle ≤ 50%)
RD30LDT3595
Electrical Characteristic
Item
Symbol VCC (V) *
Ta = 25°C
Ta = –40 to 85°C
Min
Typ
Max
Min
Typ
Max
2.0
—
VCC
2.0
—
VCC
Unit
Test condition
VIH
4.5 to 5.5
VIL
4.5 to 5.5
0
—
0.8
0
—
0.8
V
IIH
5.5
—
—
25
—
—
30
µA
VIH = 5.5 V
IIL
5.5
—
—
–25
—
—
–30
µA
VIL = 0 V
VOH
5.0
4.9
—
—
4.9
—
—
V
IOH = –1 µA
VOL
5.0
—
—
0.1
—
—
0.1
V
IOL = 1 µA
Output voltage
(Q1 to Q24)
VOL
5.0
—
—
0.55
—
—
0.77
V
IOL = 100 mA
Output leakage current
IOLK
5.5
—
—
50
—
—
100
µA
VO = 30 V
(Output : Z (OFF))
ICC1
5.5
—
—
300
—
—
500
µA
Input : Open
All driver output :
OFF
ICC2
5.5
—
—
300
—
—
500
µA
Driver output one
circuit : ON
VT+
—
2.9
3.4
3.9
2.9
3.4
3.9
V
VT-
—
2.6
3.1
3.6
2.6
3.1
3.6
V
Input voltage
Input current
Output voltage
(S-out)
Quiescent supply
current
Driver output wrong
action protection voltage
Note:
V
For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Timing Characteristics
(VCC = 5 V, CL = 15 pF, RL (S-out) = ∞, RL (Qn) = 100 Ω, tr = tf = 20 ns)
Ta = 25°C
Typ
Max
Ta = –40 to 85°C
Min
Typ
Max
Item
Symbol
Maximum clock frequency
fmax
—
—
12.5
—
—
12.5
MHz
Pulse width
Pulse width
Setup time
Hold time
Setup time
Clock pulse rise time
Clock pulse fall time
tW
tW
tsu
th
tsu
tr
tf
30
30
30
20
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
30
30
30
20
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
ns
ns
ns
ns
ns
ns
ns
Min
Unit
Test condition
Duty cycle =
45 % to 55 %
CLK
Latch
S-in to CLK
S-in to CLK
Latch to CLK
Switching Characteristics
(VCC = 5 V, CL = 15 pF, RL (S-out) = ∞, RL (Qn) = 100 Ω, tr = tf = 20ns)
Item
Propagation delay time
Symbol
Ta = 25°C
Ta = –40 to 85°C
Min
Typ
Max
Min
Typ
Max
tPLH
—
—
60
—
—
60
tPHL
—
—
60
—
—
60
tPLH
—
—
70
—
—
70
tPHL
—
—
70
—
—
70
tPLH
—
—
70
—
—
70
tPHL
—
—
70
—
—
70
REJ03D0896-0300 Rev.3.00 Jun 16, 2008
Page 4 of 6
Unit
FROM
TO
(Input) (Output)
ns
CLK
S-out
ns
CLK
Qn
ns
Enable
Qn
RD30LDT3595
Test Circuit
VCC
Input
See Function Table
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
RL
VCC
Output
Qn
CLK
CL
S-in
Latch
RL
Enable
S-out
Output
GND
CL
Notes: 1. Input waveform : PRR ≤ 1MHz, Duty Cycle = 50%, tr ≤ 20ns, tf ≤ 20ns
2. CL includes probe and jig capacitance.
Waveforms
• Waveform – 1
tf
tr
3V
90 %
1.5 V
Input CLK
1.5 V
10 %
10 %
0V
t PLH
t PHL
VOH
Output S-out
50 %
50 %
VOL
tf
tr
10 %
10 %
t PLH
3V
90 %
1.5 V
90 %
1.5 V
Input Enable
t PLH
t PHL
t PHL
0V
VOH
Output Qn
50 %
50 %
50 %
50 %
VOL
• Waveform – 2
tr , tf
90 %
Input S-in
10 %
tr , tf
90 %
1.5 V
10 %
90 %
3V
90 %
1.5 V
10 %
t su
0V
tf
tr
th
3V
90 %
Input CLK
1.5 V
1.5 V
10 %
10 %
tw
Input Latch
t su
tf
tr
3V
90 %
1.5 V
90 %
1.5 V
10 %
10 %
tw
Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 20 ns, tf ≤ 20 ns
2. The output are measured one at a time with one transition per measurement.
REJ03D0896-0300 Rev.3.00 Jun 16, 2008
Page 5 of 6
0V
0V
RD30LDT3595
Application Data
Duty Cycle − Output Current Characteristics
Ta=25°C
90
80
70
60
50
40
30
• Output current values represent
the current per circuit.
• Repeated frequency ≥ 10Hz
• The value the circle represents the value
of the simultaneously - operated circuit.
20
10
0
0
Ta=85°C
100
1 ~ 24
Output Current IOL (mA)
Output Current IOL (mA)
100
Duty Cycle − Output Current Characteristics
90
18
80
21
70
24
60
50
40
30
• Output current values represent
the current per circuit.
• Repeated frequency ≥ 10Hz
• The value the circle represents the value
of the simultaneously - operated circuit.
20
10
0
10 20 30 40 50 60 70 80 90 100
1 ~ 14
15
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
Duty Cycle (%)
Package Dimensions
JEITA Package Code
P-SSOP36-8.4x15-0.80
RENESAS Code
PRSP0036GA-A
Previous Code
36P2R-A
MASS[Typ.]
0.5g
E
19
*1
HE
36
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
18
Index mark
c
*2
D
A1
A
A2
*3
y
bp
L
e
Detail F
REJ03D0896-0300 Rev.3.00 Jun 16, 2008
Page 6 of 6
Reference Dimension in Millimeters
Symbol
D
E
A2
A
A1
bp
c
HE
e
y
L
Min Nom Max
14.8 15.0 15.2
8.2 8.4 8.6
2.0
2.4
0.05
0.35 0.4 0.5
0.13 0.15 0.2
0°
10°
11.63 11.93 12.23
0.65 0.8 0.95
0.15
0.3 0.5 0.7
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