SFX-400G Synchronous Clock Generators - Connor

SFX-400G
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Applications
• SONET / SDH / ATM
• DWDM / FDM
• FEC (Forward Error Correction)
Features
• Available as a 3.3V High Precision PLL
• Two User Selectable PECL or CMOS Input
References Frequencies
• Four User Selectable PECL Output Frequencies
• Jitter Generation OC-192 Compliant
• 1.2” x 1.0” x 0.285”, Surface Mount
• ROHS Compliant
Bulletin
Page
Revision
Date
Issued By
SG144
1 of 8
00
6 JUNE 08
ENG
General Description
The SFX-400G is a high precision frequency translator that
translates one of two inputs, greater than 1MHz, to one of four
selectable output frequencies between 10 MHz and 945 MHz.
The SFX-400G supports all major FEC rates such as 15/14,
255/237 etc.
SFX-400G is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH,
SONET and SDH network equipment. The SFX-400G provides
a jitter filtered, wander following output signal synchronized to
a superior Stratum or peer input reference signal.
The SFX-400G includes a lock detect alarm output. The
PLL control voltage is brought out through a 470 kΩ resistor
and can be used to determine when the pull range limits are
reached. The LVPECL outputs may be disabled for external
testing purposes by asserting a high signal to the Enable/
Disable pin.
The SFX-400G package typical dimensions are 1.2" x 1.0"
x 0.285". Parts are assembled using high temperature solder
to withstand surface mount reflow process.
Functional Block Diagram
Figure 1
SFX-400G
LD
(Pin 10)
470 kΩ
Monitor
(Pin 11)
Input A
Input B
In
(Pin 1)
Frequency
Loop
PECL
CIn
Divider
Filter
VCXO
(Pin 2)
Q
(Pin 12)
Q
(Pin 14)
Frequency
Divider
In Sel
(Pin 7)
Microprocessor
Out Sel 1
(Pin 8)
Out Sel 2
(Pin 4)
Disable
(Pin 16)
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
Vcc
Power Supply Voltage (OptionD)
VI
Ts
Input Voltage
Storage Temperature (OptionF)
Storage Temperature (OptionC)
Nominal
Maximum
Units
-0.3
3.8
Volts
-0.2
Vcc
Volts
-55
-40
125
85
°C
°C
Data Sheet #: SG144
Page 2 of 8
Rev: 00
Notes
Date: 6/6/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Specifications
Table 2
Symbol
Parameter
Minimum
fIN
Input Frequencies (Comp PECL)
Nominal
Maximum
Units
1
800
MHz
Input Frequencies (HCMOS )
0.008
100
MHz
fOUT
Output Frequencies (Comp PECL)
10
945
MHz
Vcc
Supply Voltage (D = 3.3 VDC)
3.15
3.45
Volts
ICC
Supply Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
1.68
V
TR/TF
Rise/Fall Time (20% - 80%)
350
ps
SYM
Output Symmetry
55
%
JGEN
Jitter Generation RMS
(12 kHz - 20 MHz)
1
ps
JTRAN
Jitter Transfer
0.1
dB
APR
Input Frequency Tracking
TOP
Operating Temperature
85
70
°C
°C
3.3
180
2.0
mA
2.275
V
45
0.5
±50
F=
C=
Notes
-40
0
1.0
ppm
NOTES: 1.0: GR-253-CORE, Sec. 5.6.2.1.2
2.0: CIN (Pin 2) is not used internally. It is AC coupled and loaded with a 180Ω resistor to ground.
Pin Description
Table 3
Pin #
Connection
Description
1
In
Input Frequency, Signal is AC coupled
2
CIn
Complementary Input Frequency, Signal is AC coupled
3
GND
Ground
4
Out Sel 2
Output Frequency Select 2
5
NC
Do Not Connect
6
NC
Do Not Connect
7
In Sel
Input Frequency Select - Logic “0” = Input Freq. A, Logic “1” = Input Freq. B
8
Out Sel 1
Output Frequency Select 1
9
Vcc
Supply Voltage
10
LD (Output)
Lock Detect
Logic “1” indicates that the unit is locked to the input reference
Logic “0” indicates that the reference is lost or out of lock range
11
Monitor (Output)
Control voltage level for the PECL oscillator and is brought out through
a 470kΩ resistor
12
Q
PECL Output (Low when Disabled)
13
GND
Ground
14
Q
PECL Complemetary Output (High when Disabled)
15
GND
Ground
16
Disable (Input)
Logic “0” (or no connect) = PECL Outputs are Enabled
Logic “1”
= PECL Outputs are Disabled
Data Sheet #: SG144
Page 3 of 8
Rev: 00
Date: 6/6/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Output Load and Power Supply Filtering Recommendations
Figure 2
*
*
* It is highly recommended
*
that either a linear regulator
or bypass capacitors be
used. Typical values would
be 10 uF, 0.1 uF, 100 pF.
VCC -2 VDC
SFX-400G
LD
(Pin 10)
470 kΩ
Monitor
50Ω
50Ω
(Pin 11)
In
Input A
Input B
(Pin 1)
Frequency
Loop
PECL
CIn
Divider
Filter
VCXO
(Pin 2)
Q
(Pin 12)
(FOUT)
Q
(Pin 14)
Frequency
Divider
In Sel
(Pin 7)
Microprocessor
Out Sel 1
(Pin 8)
Out Sel 2
(Pin 4)
Disable
(Pin 16)
Output Select Table
Table 4
Out Sel 2
Out Sel 1
Output Freq. Selected
0
0
Output Freq. 1
0
1
Output Freq. 2
1
0
Output Freq. 3
1
1
Output Freq. 4
Data Sheet #: SG144
Page 4 of 8
Rev: 00
Date: 6/6/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 3
300
Peak Temp.
245°-255°C for 15 sec Typ.
250
221°C
Temp (°C)
200
Reflow Zone
30/90 sec
(Min/Max)
150
Soaking Zone
60-90 sec Typ.
(2 min Max)
100
50
Ramp Slope not
to exceed
±3°C/sec
0
0
50
100
150
200
250
300
350
Time (sec)
Package Dimensions
Recommended Footprint Dimensions
Figure 4
Figure 5
1.000
[25.40mm]
0.150
[3.81mm]
0.700
[17.78mm]
9 10 11 12 13 14 15 16
16
9
1
8
1.200
[30.48mm]
8 7 6 5 4 3 2 1
Pin 1
0.980
[24.89mm]
0.100
[2.54mm]
0.279
[7.09mm]
(0.285" MAX)
Data Sheet #: SG144
Page 5 of 8
Rev: 00
Date: 6/6/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Standard Frequencies
1.0240 MHz
1.5440 MHz
2.0480 MHz
4.0960 MHz
6.4800 MHz
8.1920 MHz
10.0000 MHz
12.8000 MHz
13.0000 MHz
15.0000 MHz
16.3840 MHz
19.4400 MHz
20.0000 MHz
20.1416 MHz
20.4800 MHz
B2
B3
B4
B5
C2
C3
C4
D2
D3
D4
D5
D6
E2
E3
E4
22.2171 MHz
26.0000 MHz
27.0000 MHz
29.4912 MHz
32.7680 MHz
37.0560 MHz
38.8800 MHz
44.4343 MHz
44.7360 MHz
51.8400 MHz
61.4400 MHz
65.5360 MHz
77.7600 MHz
78.1250 MHz
78.6432 MHz
E5
F3
F4
F5
H3
H4
H5
J2
J3
J4
J5
J6
K2
K3
K5
82.9440 MHz
112.0000 MHz
114.0000 MHz
125.0000 MHz
139.2640 MHz
155.5200 MHz
156.2500 MHz
161.1328 MHz
166.6286 MHz
167.3316 MHz
168.0407 MHz
311.0400 MHz
622.0800 MHz
624.7048 MHz
K6
L2
L3
L4
L5
M2
M3
M4
M5
N2
N3
P1
P2
P6
625.0000 MHz
627.3596 MHz
644.5312 MHz
666.5143 MHz
669.1281 MHz
669.3266 MHz
672.1627 MHz
690.5692 MHz
710.9486 MHz
719.7344 MHz
777.6000 MHz
No 2nd Input Freq.
Input Freq. not listed
Output Freq. not listed
P3
P7
P4
P5
R2
R3
R5
R4
T2
T3
T4
XX
SS
SS
Ordering Information
SFX-400G- D F C - D6 D6 P2 P4 P5 R3
Supply Voltage
D = 3.3 VDC
Output Frequency 1- 4 (F3 to T4)
Output Logic
F = Comp. PECL
Temperature Range
C = 0˚C to 70˚C
F = -40˚C to 85˚C
Input Frequency A (B2 to T4)
See standard frequencies chart above.
* If the desired frequency is not listed, enter
SS in this block and add the frequency after
the part number. Consult a sales representative
for availabilty of additional frequencies.
** Input A must be less than Input B
See standard frequencies chart above.
* If the desired frequency is not listed, enter
SS in the corresponding block and add the frequency
after the part number. Consult a sales representative
for availabilty of additional frequencies.
** From left to right, desired frequencies should
be listed in ascending order such that
Freq. 1<Freq. 2<Freq. 3<Freq. 4.
Input Frequency B (B3 to T4)
See standard frequencies chart above. If a
second input frequency is not required, place XX
in this location.
* If the desired frequency is not listed, enter
SS in this block and add the frequency after
the part number. Consult a sales representative
for availabilty of additional frequencies.
** Input B must be greater than Input A
Data Sheet #: SG144
Page 6 of 8
Rev: 00
Date: 6/6/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG144
Page 7 of 8
Rev: 00
Date: 6/6/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Revision
Revision Date
Note
00
6/6/08
Preliminary Release