CONNOR-WINFIELD SCG4521

SCG4521
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Features
• Dual 19.44 MHz Input References
• Primary 155.52 MHz LVPECL Outputs with Disable Function
• Secondary 51.84 MHz CMOS Output
• Phase Locked Output Frequency Control
• Intrinsically Low Jitter Crystal Oscillator
• LOR & LOL Alarm
• Force Free Run Function
• Automatic Free Run operation on loss of both References A & B
• Input Duty Cycle Tolerant
• 3.3V dc Power Supply
Bulletin
Page
Revision
Date
Issued By
SG036
1 of 16
A02
25 Oct 01
MBatts
• Small Size: 1 Square Inch
General Description
Package Outline
The SCG4521 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled.
The SCG4521 can lock to one of two external
references, which is selectable using the SELAB input
select pin. The unit has a fast acquisition time of about
1.5 seconds and it is tolerant of different reference duty
cycles.
The SCG4521 provides two types of output logic.
The primary output is a differential LVPECL output at
155.52 MHz. The secondary output is a CMOS output
at 51.84 MHz that is derived from the LVPECL output.
Both outputs are phase aligned to the selected input
reference.
The SCG4521 includes an alarm output that
indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FRstatus
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to ±20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1” x 1” x .45” on a 6
layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Figure 1
Block Diagram
Figure 2
ALARM
REFA
REFB
DPFD
8 KHz PHASE
ALIGNER
ANALOG
FILTER
LOW JITTER
155.52 MHz
VCXO
1/N
SELAB
Advance Data Sheet #: SG036
Page 2 of 16
Q
QN
CMOS
Output
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
Vcc
Power Supply Voltage
-0.5
-
+4.0
Volts
1.0
Vi
Input Voltage
-0.5
-
+5.5
Volts
1.0
Ts
Storage Temperature
-65.0
-
+100
°C
1.0
Operating Specifications
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
Vcc
Power Supply Voltage
3.135
3.3
3.465
Volts
2.0
Icc
Power Supply Current
170
250
320
mA
5.0
To
Temperature Range
0
-
70
°C
FREF
External Reference Frequency
Ffr
Free Run Frequency
-20
-
FLV
LVPECL Differential Output Frequency
155.52
MHz
FCM
CMOS Output Frequency
51.84
MHz
Fcap
Capture/pull-in range
-25
-
25
ppm
Fbw
Jitter Filter Bandwidth
-
-
10
Hz
Tjtol
Input Jitter Tolerance
-
-
6.25
µs
Taq
Acquisition Time
-
1
-
s
4.0
Trf
Output Rise and Fall Time (20% 80%)
100
225
350
ps
5.0
LVDC
LVPECL Output Duty Cycle
40
60
%
CMDC
CMOS Output Duty Cycle
40
60
%
LVS
LVPECL Output Jitter (OC-48)
<1
psRMS
6.0
CMS
CMOS Output Jitter
5
psRMS
6.0
MTIEsr
MTIE at Synchronization Rearrangement
19.44
3
MHz
20
ppm
GR-253-CORE.1999 R5-136
3.0
7.0, 7.1
NOTES:
1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF)
3.0 3db loop response.
4.0 From a 20 PPM step in reference frequency at 25°C @ 3.3V
5.0 50-ohm load biased to 1.3 volts.
6.0 Jitter based on SONET OC-48 bandwidth. (12KHz to 20 MHz)
7.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.
7.1 If the selected reference is removed system response to the ALARM must be less than 10µs.
Advance Data Sheet #: SG036
Page 3 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input And Output Characteristics
Table 3
Symbol
Parameter
Minimum
Nominal
Maximum
Units
CMOS Input and Output Characteristics
Vih
High Level Input Voltage
2.0
-
5.5
V
Vil
Low Level Input Voltage
0.0
-
0.8
V
Tio
I/O to Output Valid
-
-
10
ns
Cl
Output Capacitance
-
-
10
pF
Voh
High Level Output Voltage
2.4
-
-
V
Vol
Low Level Output Voltage
-
-
0.4
V
Tir
Input Reference Pulse Width
12.5
-
-
ns
2.27
2.34
2.52
V
PECL Output Characteristics
Voh
High Level PECL Voltage
Vol
Low Level PECL Voltage
1.49
1.51
1.68
V
Cl
Output Capacitance
-
-
10
pF
Tskew
Differential Output Skew
-
50
-
ps
Notes
Input Selection / Output Response
Table 4
ENABLE
SELAB
INPUTS
REFA
REFB
FR
FRstatus
OUTPUTS
ALARM
Q
QN
1
0
X
X
X
X
1
X
X
X
X
1
X
X
X
X
X
X
0
1
0
0
X
X
X
1
1
X
X
X
FR
0
0
0
A
A
0
0
0
X
X
RA
0
0
1
A
A
0
0
0
X
X
RB
0
0
0
NA
A
0
0
1
X
X
U
0
0
1
NA
A
0
0
0
X
X
RB
0
0
1
A
NA
0
0
1
X
X
U
0
0
0
A
NA
0
0
0
X
X
RA
0
0
X
NA
NA
0
1
1
X
X
FR
RESET
NOTE
FR
NOTES:
A
Active
FR Free Run Mode
NA Not Active
RA Locked to Reference A
RB Locked to Reference B
U
Unstable (due to conditions shown, switch to active reference or Free Run)
X
Don’t care
Advance Data Sheet #: SG036
Page 4 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE Measurement
Figure 3
Typical TDEV Measurement
Figure 4
Advance Data Sheet #: SG036
Page 5 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of
Reference A, No Modulation.
Figure 5
Advance Data Sheet #: SG036
Page 6 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Pin Description
Table 5
Pin #
Pin Name
Pin Information
Note
1
ENABLE
VCXO Enable. (Enable = 0, Disable = 1)
9.0
2
TCK
No Connection, Internal Factory Programming Input.
8.0
3
TDO
No Connection, Internal Factory Programming Input.
8.0
4
REFA
CMOS Reference Frequency Input. (19.44 MHz)
5
SELAB
Input Reference Select Pin. (REFA = 0, REFB = 1)
9.0
6
RESET
RESET. (RESET = 1)
9.0
7
REFB
CMOS Reference Frequency Input. (19.44 MHz)
8
Vee
Ground.
9
FRstatus
Free Run Status. (FR = 1)
10
Vcc
Supply Voltage relative to ground.
11
CMOS Output
CMOS Output (51.84 MHz)
12
ALARM
Loss of Reference / Lock alarm. (Alarm = 1)
13
FR
Force Free Run. (Phase Lock = 0, Free Run = 1)
9.0
14
TDI
No Connection, Internal Factory Programming Input.
8.0
15
TMS
No Connection, Internal Factory Programming Input.
8.0
16
QN
LVPECL Complementary Output.
17
Vee
Ground.
18
Q
LVPECL Output.
NOTES
8.0 Do not connect pin
9.0 Input pulled to ground
Circuit Board Footprint Recommendations
Figure 6
Advance Data Sheet #: SG036
Page 7 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when both are good signals
Figure 7
Ref A
Ref B
LOL portion of
Alarm is
Blanked
Alarm
0.5 sec
Sel A/B
New Reference
Qualification time
Switch from A to B when Reference B is lost
Figure 8
Ref A
Ref B
~5ns
Alarm
Sel A/B
Advance Data Sheet #: SG036
Page 8 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B after Reference A is lost
Figure 9
Ref A
Ref B
Alarm
Blanked
Alarm
125 - 250 µ s
Sel A/B
New Reference
Qualification time
Switch from A to B when A is out of range
Figure 10
Ref A
Out of
Range
Ref B
In
Range
Alarm
Alarm
Blanked
Sel A/B
New Reference
Qualification time
Advance Data Sheet #: SG036
Page 9 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when B is out of range
Figure 11
Switch from A to B when B is out of range
Ref A
In
Range
Ref B
Out of
Range
Alarm
Blanked
Alarm
SEL A/B
New Reference
Qualification time
Advance Data Sheet #: SG036
Page 10 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended PECL Termination
Figure 12
3.3 VDC
3.3 VDC
3.3 VDC
130
82
Vcc
Vcc
Q
D
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
50 OHM Transmission Line
GND
GND
130
82
3.3 VDC
3.3 VDC
Vcc - 2 VDC
3.3 VDC
50
Vcc
Vcc
Q
D
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
50 OHM Transmission Line
GND
GND
50
Vcc - 2 VDC
3.3 VDC
3.3 VDC
150
Vcc
Vcc
Q
50
SCGxxx
LVPECL
OUTPUT
D
50 OHM Transmission Line
LVPECL
INPUT
100
50
QN
DN
50 OHM Transmission Line
GND
GND
150
If PECL outputs do not drive a long line (< 0.5”),
a single 150Ω termination resistor to ground may be used for each pin.
Advance Data Sheet #: SG036
Page 11 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Tape and Reel Packaging
Figure 13
Advance Data Sheet #: SG036
Page 12 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 14
250
200
Temp
(C˚)
150
100
50
0
1
2
3
4
5
6
7
8
Time(minutes)
Recommended Reflow Profile
Peak Temp:217C˚
MaxRiseSlope:1.5 C˚/Sec
Time Above150C˚:100Sec
Advance Data Sheet #: SG036
Page 13 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Advance Data Sheet #: SG036
Page 14 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Advance Data Sheet #: SG036
Page 15 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Revision
Revision Date
Note
A00
9/4/01
Advance Information Release
A01
10/9/01
Changed PECL phase noise spec and
max current spec.
A02
10/25/01
Added input reference frequency to
table 2
Data Sheet #: SG036
Page 16 of 16
Rev: A02
Date: 10/25/01
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice