Semicustom Products UT130nHBD Hardened-by-Design (HBD) Standard Cell Advanced Data Sheet August 2010 www.aeroflex.com/RadHardASIC FEATURES PRODUCT DESCRIPTION Up to 15,000,000 usable equivalent gates using standard cell architecture The high-performance UT130n HBD Hardened-by-Design ASIC standard cell family features densities up to 15,000,000 equivalent gates and will be available in multiple quality assurance levels such as MIL-PRF-38535, QML V and Q, military, industrial grades and non-RadHard versions. Toggle rates up to 1.5 GHz Advanced 130nm silicon gate CMOS processed in a commercial fab Operating voltage 3.3V I/O and 1.2V core Multiple product assurance levels to be available in QML Q and V, military and industrial Radiation hardened from 100 krads(Si) to 300 krads (Si) total dose available using Aeroflex Colorado Springs’s (Aeroflex) RadHard techniques SEU-immune to less than 1.0x10-10 errors/bits-day available using special library cells Special I/O offering: HSTL, Class I and II, LVDS Robust Aeroflex Design Library of cells and macros Support for Verilog and VHDL design languages on Sun and Linux workstations Cell models validated in Mentor Graphics® and SynopsysTM design environments Full complement of industry standard IP cores Wide selection of SP/DP SRAMs with optional MBIST and EDAC Low power dissipation of 18nW/MHz/gate at 1.2V VDDQ Operating temperature range of -55oC to +125oC Package pin count of up to 624 for wire bond and 1248 for Flip-Chip (in development) For those designs requiring stringent radiation hardness, Aeroflex's 130nm process employs a special technique that enhances the total dose radiation hardness to 300 krads(Si) while maintaining circuit density and reliability. In addition, the process uses epitaxial wafers for greater transient radiation hardness and latch-up immunity. The UT130nHBD ASIC family uses highly efficient standard cell architecture for internal cell instantiation developed using Aeroflex's patented architectures. Combined with state-of-the-art, timing driven placement and routing tools, the area utilization and signal routing of transistors is maximized using six metal interconnect routing layers. Table 1, 2 and 3 summarizes some of the most important aspects of the 130nm ASIC Library. The UT130nHBD ASIC family is supported by an extensive cell library that includes standard logic functions, Phase Lock Loop (PLL) and SRAM with optional MBIST and EDAC. Aeroflex's IP library includes the following functions: • Intel 80C31® equivalent • Intel 80C196® equivalent • MIL-STD-1553 functions (BRCTM, RTI, RTMP) • MIL-STD-1750 microprocessor • RISC microcontroller • Aeroflex Gaisler - LEON3 and other IP can be reviewed at www.gaisler.com 1 Table 1: Library Overview CHARACTRISTICS Technology Logic Density Supply Voltages Typical Power Dissipation Standard Cells Intrinsic Gate Delay (na02nd2) Fastest Core Frequency I/O's VALUE TSMC 130G - 130nm Bulk CMOS, 8 metal layers 86K gates/mm2 = ~15M gates 3.3V, 2.5V (planned) & 1.8V I/O; 1.2V core ~ 18nW/gate-MHz @ 1.2V ~ 300 multi-VT cells (high VT, standard VT and low VT) 50ps 570 MHz (10 levels of logic) 3.3V, 2.5V (planned); 4, 8, 12, 24mA outputs; LVCMOS, LVTTL, Schmitt trigger; bidirectional, programmable, configurable pull up/ down Single & Dual-port SRAM & Register file compiler HSTL (250MHz), LVDS (400Mbps), PLL's (100-500MHz), SerDes (3.125Gbps - in development) -55°C to 125°C 1kV Wirebond: CQFP, CCGA, CBGA. Flip Chip (in development) Memories Macros Rated Temp Range ESD (Human Body Model) Packaging Options ABSOLUTE MAXIMUM RATINGS 1 (All supplies referenced to ground) SYMBOL PARAMETER LIMITS VDDIO2 I/ODC supply voltage -0.3V to 3.3V +30% VDDQ2 Core DC supply voltage -0.3V to 1.2V + 30% TSTG Storage temperature -65°C to +150°C TJ Maximum junction temperature +150°C ILU Latchup immunity +150mA II DC input current +10mA TLS Lead temperature (soldering 5 sec) +300°C Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.The recommended "power-on" sequences is VDDQ voltage supply applied first, followed by the VDDIO voltage supply. The recommended "power-off" sequence is the reverse. Remove VDDIO voltage supply, followed by removing VDDQ voltage supply. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDDIO IO DC supply voltage 3.0V + 0.3 VDDQ Core DC supply voltage 1.2V+ 0.1 2 LOW-NOISE DEVICE AND PACKAGE SOLUTIONS Separate on-chip power and ground buses are provided for internal cells and output drivers which further isolate internal design circuitry from switching noise. In addition, Aeroflex offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring builtin isolated power and ground planes (Table 2). These planes provide lower overall resistance/inductance through power and ground paths which minimize voltage drops during periods of heavy switching. These isolated planes also help sustain supply voltage during dose rate events, thus preventing rail span collapse. Flatpacks are available with up to 352 leads. PGAs are available with up to 299 pins and LGAs/CCGAs up to 624 pins. Aeroflex's flatpacks feature a non-conductive tie bar that helps maintain lead integrity through test and handling operations. In addition to the packages listed in Table 2, Aeroflex offers custom package development and package tooling modification services for individual requirements. For ASIC's that require high signal I/O count, Aeroflex is developing flip chip packaging solutions. Table 2: Packaging TYPE Flatpack PGA TOTAL PINS Up to 352 299 472,624 LGA4 Note: 1.Contact Aeroflex for specific package drawings. 2. External chip capacitor attachment available to space quality levels (for improved SSO response). 3. Aeroflex supports all JEDEC outline package designs. 4. LGA package formats can be provided with Solder Columns. EXTENSIVE CELL LIBRARY The UT130nHBD ASIC family is supported by an extensive cell library that includes standard logic functions, Phase Lock Loop (PLL) and SRAM with optional MBIST and EDAC. User-selectable options for cell configurations include scan and radiation hardness (SEU) levels for all register elements, as well as output drive strength. Phase-Locked Loop (PLL) macro cell is derived from the SerDes PLL and is capable of covering a frequency range of 100MHz to 500MHz. The PLL supports a power-down mode and phase lock indicator. Refer to Aeroflex's UT130nHBD Design Manual for complete cell listing and details. I/O BUFFERS The UT130nHBD family offers a high number of specialized I/O's. For any specific design, signal availability is affected by package selection and IO type. The LVCMOS I/O cells can be configured by the user to serve as input, output, bidirectional or threestate. Output drive options range from 4, 8, 12 and 24mA. To drive larger off-chip loads output drivers may be combined in parallel to provide additional drive up to 48mA. Other I/O buffer features and options include: • Internally Configurable weak pull-up and pull-down devices • Schmitt trigger • LVDS • HSTL LVDS transmitter (Tx) and receiver (Rx) buffers are enhanced versions of the Aeroflex Standard Products UT54LVDS031LV LVDS driver and UT54LVDS032LV receiver products. They provide the same >400Mbps (200MHz) switching rates, 340mV nominal differential signaling levels, transmitter enable and receiver fail-safe circuitry. Each supports a power-down mode that 3 configures the I/O buffers into their lowest power state. A unique Aeroflex reference circuit improves performance matching between multiple Tx buffers and multiple Rx buffers. Aeroflex's ASIC HSTL bidirect, tristate and input buffers are based on the EIA/JEDEC Standard EIA/JESD8-6 (August 1995) Class-1 and -2. They provide switching rates of 250MHz and all support a power-down mode. JTAG BOUNDARY-SCAN The UT130nHBD family allows for insertion of a test access port and boundary-scan that conforms to the IEEE Standard 1149.1 (JTAG). Some of the benefits of this capability are: • Easy test of complex assembled printed circuit boards • Gain access to and control of internal scan paths • Initiation of Built-In Self Test CLOCK DRIVER DISTRIBUTION Aeroflex design tools provide methods for balanced clock distribution that maximize drive capability and minimize relative clock skew between clocked devices. SPEED AND PERFORMANCE Aeroflex specializes in high-performance circuits designed to operate in harsh military and radiation environments. Typically the propagation delay for a CMOS device is a function of its fanout loading, input slew, supply voltage, operating temperature and processing radiation tolerance. In a radiation environment additional performance variances must be considered. The UT130nHBD simulation models account for all of these effects to accurately determine circuit performance for its particular set of use conditions. POWER DISSIPATION Power consumption of internal gates and I/O buffers is based on many factors including switching frequency, loading, voltage, temperature and transistor leakage characteristics. Aeroflex's radiation-tolerant process exhibits power dissipation that is typical of commercial CMOS processes. The UT130nHBD cell library supports a low power design methodology by providing high threshold voltage VT versions of the core cells to reduce leakage current. Additionally the library contains clock gating cells that can be used to reduce switching activity in designs. For rigorous power estimation methodology refer to the Aeroflex UT130nHBD Design manual or consult with an Aeroflex Applications Engineer. ASIC DESIGN SOFTWARE Using a combination of state-of-the-art third-party and proprietary design tools Aeroflex delivers the CAE support and capability to handle complex, high-performance ASIC designs from design concept through design verification and test. Aeroflex's flexible circuit creation methodology supports high level design methodology by providing synthesis libraries in Liberty syntax. Compiled technology files are provided for Synopsys synthesis and design analysis tools. Design verification is performed in any VHDL or Verilog simulation environment using Aeroflex's robust libraries. Aeroflex also supports Automatic Test Program Generation and Memory BIST to improve design testing. AEROFLEX HDL DESIGN SYSTEMS Aeroflex offers a Hardware Description Language (HDL) design system supporting both VHDL and Verilog that allows easy access to Aeroflex's RadHard capabilities. Both the VHDL and Verilog libraries provide sign-off quality models and robust tools. 4 The VHDL libraries are VITAL 3.0 compliant and the Verilog libraries are OVI 1.0 compliant. With the library capabilities Aeroflex provides, you can use High Level Design methods to synthesize your design for simulation. Aeroflex also provides tools to verify that your HDL design will result in successful implementations. RTL RTL Synthesis Synthesis DC Ultra DC Ultra Analysis / Fi xing (DC Graphical & ICC-DP) Netlist 95-100% Don e Final Flow RTL LEF/DEF Reviews P&R Iterations ICC Place & Route DC Ultra Analysi s / Fixing (DC Graphi cal & ICC-DP ) Netlist Netlist ICC Floor plan & Global Route Synthesis RTL/Synthe sis Itera tions Synthesis / P&R Scripts ICC Place & Route P&R Iterations Liberty FRAM TLU-Pl us 85% Done Floor Planning RTL/Synthe sis Iter ations RTL Development 70% Done Sign-off & Tape out Figure 1: Design Plan ADVANTAGES OF THE AEROFLEX HDL DESIGN SYSTEMS • The Aeroflex HDL Design System gives you the freedom to use tools from Synopsys, Mentor Graphics, Cadence and other vendors to help you synthesize and verify a design. • Aeroflex's Logic Rules Checker and Tester Rules Checker allow you to verify partial or complete designs for compliance with Aeroflex design rules. • Aeroflex HDL Design System accepts back-annotation of timing information through SDF. XDTSM (EXTERNAL DESIGN TRANSLATION) Through Aeroflex's XDT services, customers can convert an existing non-Aeroflex design to Aeroflex's UT130nHBD platform for increased power/speed performance. The XDT capability is particularly useful for converting an FPGA to an Aeroflex radiationtolerant technology. The XDT translation tools convert industry standard netlist formats and 3rd party vendor libraries to Aeroflex formats and libraries. Industry standard netlist formats supported by Aeroflex include: • VHDL • Verilog HDL • FPGA source files (Actel, Altera, Xilinx) • EDIF • Third-party netlists supported by Synopsys 5 TOOLS SUPPORTED BY AEROFLEX Aeroflex supports libraries for: • Mentor Graphics − ModelSim − Tessent FastScan - Tessent Memory • Synopsys - Design Compiler (with PowerCompiler) - PrimeTime - PrimePower - VCS for Verilog and VHDL - Formality - TetraMax • VITAL-compliant VHDL Simulation Tools • OVI-compliant Verilog Simulation Tools TRAINING AND SUPPORT Aeroflex personnel conduct training classes tailored to meet individual needs. These classes can address a wide mix of engineering backgrounds and specific customer concerns. Applications assistance is also available through all phases of ASIC Design. PHYSICAL DESIGN By using five layers of metal interconnect Aeroflex achieves optimized layouts that maximize speed of critical nets, overall chip performance and design density up to 15,000,000 equivalent gates. TEST CAPABILITY Aeroflex supports all phases of test development from test stimulus generation through high-speed production test. This support includes ATPG, fault simulation and fault grading. Scan design options are available on all UT130nHBD storage elements. Automatic test program development capabilities handle large vector sets for use with Aeroflex's Teradyne Tiger ATEs, supporting high-speed testing (up to 1.2GHz). QUALITY AND RELIABILITY Aeroflex is dedicated to meeting the stringent performance requirements of aerospace and defense systems suppliers. Aeroflex maintains the highest level of quality and reliability through our Quality Management Program under MIL-PRF-38535 and ISO9001. In 1988 we were the first gate array manufacturer to achieve QPL certification and qualification of our technology families. Our product assurance program has kept pace with the demands of certification and qualification. Our quality management plan includes the following activities and initiatives. • Quality improvement plan • Failure analysis program • SPC plan • Corrective action plan • Change control program • Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV) assessment program • Certification and qualification program Because of numerous product variations permitted with customer specific designs much of the reliability testing is performed using a Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV). Aeroflex utilizes the wafer foundry's data from TCV test structures to evaluate hot carrier aging, electromigration and time dependent test samples for reliability testing. 6 Data from the wafer-level testing can provide rapid feedback to the fabrication process, as well as establish the reliability performance of the product before it is packaged and shipped. RADIATION TOLERANCE Aeroflex incorporates radiation-tolerance techniques in process design, design rules, array design, power distribution and library element design. All key radiation-tolerance process parameters are controlled and monitored using statistical methods and in-line testing (Table 3). Table 3: Radiation Hardness PARAMETER RADIATION TOLERANCE NOTES Total ionizing dose 100-300 krad(Si) 1,2 Single event upset (SEU) <1.0x10-10 errors per cell-day 3,4 Single event latchup (SEL) Latchup immune to LET = 115 MeV/cm2/mg 5 Notes: 1.Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019. 2.TID data measured at 1.35V core/3.6V I/ O VDDIO. All post radiation values measured at 25°C. 3.SEU limit based on standard evaluation circuit at 1.1V core/3.0V I/ O VDDIO 25°C condition. 4.SEU-hard flip-flop cell. Non-hard flip-flop typical is 5x10-8. 5.SEL data measured at 1.3V core/3.6V I/ O VDDIO and 125°C. Intel is a registered trademark of Intel Corporation Mentor, Mentor Graphics, FastScan, FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation Sun is a registered trademark of Sun Microsystems, Inc. Synopsys, Design Compiler, VHDL Compiler, HDL Compiler, Te 7 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 8