Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 270K Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG) 3 and 5 Volts Operation; Single or Dual Supply Mode High Speed Performances: – 505 ps Max NAND2 Propagation Delay at 4.5V, 825 ps at 2.7V and FO = 5 – Min 440 MHz Toggle Frequency at 4.5V, 230 MHz at 2.7V Programmable PLL Available upon Request High System Frequency Skew Control through Clock Tree Synthesis Software Low Power Consumption: – 2.7 µW/Gate/MHz at 5V – 0.86 µW/Gate/MHz at 3V Integrated Power On Reset Matrices with a Max of 360 Fully Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O High Noise and EMC Immunity: – I/O with Slew Rate Control – Internal Decoupling – Signal Filtering between Periphery and Core – Application Dependent Supply Routing and Several Independant Supply Sources Wide Selection of MQFPs and MCGA Packages up to 352 Pins Delivery in Die Form with 110 µm Pad Pitch Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence®, Mentor®, Vital® and Synopsys® Reference Platforms EDIF and VHDL Reference Formats Available in Military and Space Quality Grades (SCC, MIL-PRF-38535) No Single Event Latch-up below an LET threshold of 80MeV/mg/cm 2 Tested up to a Total Dose of 300 Krad (Si) according to MIL STD 883 Method 1019 QML Q and V with SMD 5962-00B03 and 5962-03B01 Rad Hard 190K Used Gates 0.5 µm CMOS Sea of Gates MG2RTP Description The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 270K gates cover most system integration needs. The MG2RTP is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2 RTP. The base cell architecture of the MG2RTP series provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: three or more independent supplies, internal decoupling, customization dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. The MG2RTP is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog, Modelsym and Design Compiler are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle. 4116M–AERO–06/06 The MG2RTP Library allows straight forward migration from the MG1, MG1RT, MG2 and MG2RT Sea of Gates. A netlist based on this library can be simulated as either MG2RTP or MG2RT. It can also be simulated as MG2, provided there are no SEU Free cells. Table 1. List of Available MG2RTP Matrices Type Total Gates Typical Usable Gates Maximum Programmable I/Os Total Pads MG2044P 44616 31200 146 165 MG2142P 142128 99500 262 281 MG2270P(1) 270015 189000 360 377 Note: Libraries 1. Not available for new designs. The MG2RTP cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, such as Two-Wire Interface (TWI), UART, Timer. Block Generators Block generators are used to create a customer specific simulation model and metallisation pattern for regular functions like RAM and DPRAM. The basic cell architecture allows one bit per cell for RAM and DPRAM. The main characteristics of these generators are summarized below. Function 2 Maximum Size (bits) Bits/Word Typical Characteristics (16K bits) at5V Access Time (ns) Used cells RAM 32K 1-36 12 20K DPRAM 32K 1-36 14 23K MG2RTP 4116M–AERO–06/06 MG2RTP I/O Buffer Interfacing I/O Flexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer. Inputs Input buffers with CMOS or TTL thresholds are non inverting and feature versions with and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available. Outputs Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA drive at 5V, low noise buffers with 12 mA drive at 5V. Clock Generation and PLL Clock Generation Atmel offers 5 different types of oscillators: 3 high frequency crystal oscillators and 2 RC oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms. Frequency (MHz) PLL Typical Consumption (mA) Oscillators Max 5V Max 3V 5V 3V Xtal 7M 10 6 1.2 0.4 Xtal 50M 60 35 7 2 Xtal 100M 120 70 16 5 RC 10M 10 10 2 1 RC 32M 32 32 3 1.5 Contact factory. 3 4116M–AERO–06/06 Power Supply and Noise Protection The speed and density of the SCMOS3/2RTP technology causes large switching current spikes for example when: • Either 16 high current output buffers switch simultaneously • Or 10% of the 270 000 gates are switching within a window of 1 ns. Sharp edges and high currents cause some parisitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O Buffers Switching Protection Three features are implemented to limit the noise generated by the switching current: • The power supplies of the input and output buffers are separated. • The rise and fall times of the output buffers can be controlled by an internal regulator. • A design rule concerning the number of buffers connected on the same power supply line has been imposed. Matrix Switching This noise disturbance is caused by a large number of gates switching simultaneously. To allow Current Protection this without impacting the functionality of the circuit, three new features have been added: 4 • Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. • A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. • A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. MG2RTP 4116M–AERO–06/06 MG2RTP Packaging Atmel offers a range of packaging options which are listed below: Package Type(1) Pins Lead Spacing Min/Max (mils) 100 MQFP Note: 132 196 256 25 25 25 20 1. Contact Atmel local design centers to check the availability of the matrix/package combination. 5 4116M–AERO–06/06 Design Flows and Tools Design Flows and Modes A generic design flow for an MG2RTP array is illustrated below. A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks: • Gate level logic simulation and comparison with high level simulation results. • Design and test rules check. • Power consumption analysis. • Timing analysis (only after floor plan). The main design stages are: • System specification, preferably in VHDL form. • Functional description at RTL level. • Logic synthesis. • Floor planning and bonding diagram generation. • Test/Scan insertion, ATG and/or fault simulation. • Physical cell placement, JTAG insertion and clock tree synthesis. • Routing To meet the various requirements of designers, several interface levels between the customer and Atmel are possible. For each of the possible design modes a review meeting is required for data transfer from the user to Atmel. In all cases the final routing and verifications are performed by Atmel. The design acceptance is formalized by a design review which authorizes Atmel to proceed with sample manufacturing. 6 MG2RTP 4116M–AERO–06/06 MG2RTP Figure 1. MG2RTP Design Flow System Specifications RTL Simulation Logic synthesis Floor Plan Bonding diagram Gate Level Simulation Scan insertion ATG and Fault Simulation Placement JTAG insertion Clock Tree Synthesis Routing + Extract Backannotated Simulation Sign-off Samples Manufacturing and Test 7 4116M–AERO–06/06 Design Tools and Design Kits (DK) The basic content of a design kit is described in the table below. The interface formats to and from Atmel rely on IEEE or industry standard: • VHDL for functional descriptions • VHDL or EDIF for netlists • Tabular, log or .VCD for simulation results • SDF (VITAL format) and SPF for back annotation • LEF and DEF for physical floor plan information The design kits supported for several commercial tools are listed below. Design Kit Support • Cadence/Verilog (RTL and gate), Logic Design Planner • Mentor/Modelsim (RTL and gate), Velocity, BSD Architect, Flex Test • Synopsys, Design Compiler, PrimeTime • Vital Table 2. Design Kit Description Design Tool or Library Atmel Software Name Third Party Tools Design manual and libraries - (1) Synthesis library - (1) Gate level simulation library - (1) Design rules analyser Power consumption analyser STAR COMET Floor plan library - (1) Timing analyser library - (1) Package and bonding software PIM (1) Scan path and JTAG insertion ATG and fault simulation library Note: 8 - (1) 1. Refer to “Design kits cross reference tables” ATD-TS-WF-R0181 MG2RTP 4116M–AERO–06/06 MG2RTP Electrical Characteristics Absolute Maximum Ratings Ambient temperature under bias (TA) Military ......................................................-55 to +125°C Junction temperature..............................TJ < TA + 20°C Storage temperature.................................-65 to +150°C Note: Stresses above those listed may cause permanent damage to the device. Exposure to absolute Maximum rating conditions for extended period may affect device reliability. TTL/CMOS: Supply voltage VDD ................................... -0.5V to +7V I/O voltage ......................................-0.5V to VDD + 0.5V DC Characteristics Table 3. DC Characteristics - Specified at VDD = +5V ± 10% Symbol Parameter Min Typ Max Unit Conditions 0 0 - 0.3 VDD 0.8 V - VIL Input LOW voltage (3) CMOS input TTL input VIH Input HIGH voltage(3) CMOS input TTL input 0.7 VDD VOL Output LOW voltage - - 0.4 V IOL = 24, 12, 6, 3 mA(1) VOH Output HIGH voltage TTL CMOS 2.4 3.9 - - V IOH = -24, -12, -6, -3 mA(1) IOH = -20, -10, -5, 2.5 mA (1) VT+ Schmitt trigger positive threshold CMOS input TTL input - - 3.6 1.8 V - VT- Schmitt trigger negative threshold CMOS input TTL input 1.1 0.9 - - V - - VDD VDD 2.2 V - 9 4116M–AERO–06/06 Table 3. DC Characteristics - Specified at VDD = +5V ± 10% Symbol Parameter Min CMOS Hysterisis 25°C/5V TTL Hysterisis 25°C/5V DeltaV IOZ Output Short circuit current Conditions 300 μA μA μA -5 +5 μA - - - 75 150 220 440 mA BOUT3 BOUT6 BOUT12 BOUT24 75 (2) Unit V -5 -44 3-State Output Leakage current IOS Max 1.9 0.6 Input leakage No pull up/down Pull up Pull down IL Typ +5 -100 -66 118 - ICCSB Leakage current per cell - 1.0 10.0 nA - ICCOP Operating current per cell - 0.54 0.71 μA/MHz - Note: 1. According buffer: Bout24, Bout12, Bout6, Bout3. 2. Supplied as a design limit but not guarantedd or tested. No more than one outout may be shorted at a time for a maximum duration of 10 seconds. 3. Without Schmitt trigger. Table 4. DC Characteristics - Specified at VDD = 2.7V to 3.6V Symbol VIL VIH VOL Input LOW voltage(3) LVCMOS input LVTTL input Input HIGH voltage(3) LVCMOS input LVTTL input Output LOW voltage TTL VOH Output HIGH voltage TTL VT+ Schmitt trigger positive threshold LVCMOS input LVTTL input VT- 10 Parameter Schmitt trigger negative threshold LVCMOS input LVTTL input Min Typ Max 0 0 – 0.3 VDD 0.7 VDD 0.8 – VDD 2.0 - 2.4 – VDD – – – 0.4 - 2 1 0.8 0.7 – – Unit V V Conditions – – V IOL = -6, 3, 1.5 mA(1) V IOH = -4, 2, 1 mA(1) V V – – MG2RTP 4116M–AERO–06/06 MG2RTP Table 4. DC Characteristics - Specified at VDD = 2.7V to 3.6V (Continued) Symbol DeltaV Parameter Min LVCMOS Hysterisis 25°C/3V LVTTL Hysterisis 25°C/3V Typ Max 0.8 0.2 Unit Conditions V Input leakage No pull up/down Pull up Pull down IL 31 -20 42 140 μA μA μA -1 -16 +1 -50 – IOZ 3-State Output Leakage current – – ±1 μA – IOS Output Short circuit current (2) - - 45 90 130 260 mA BOUT3 BOUT6 BOUT12 BOUT24 ICCSB Leakage current per cell – 0.6 5 nA – ICCOP Operating current per cell – 0.29 0.33 µA/MHz – Notes: 1. According buffer: Bout12, Bout6, Bout3 2. Supplied as a design limit but not guarantedd or tested. No more than one outout may be shorted at a time for a maximum duration of 10 seconds. 3. Without Schmitt trigger. 11 4116M–AERO–06/06 AC Characteristics Table 5. AC Characteristics - TJ = 25°C, Process typical (all values in ns) VDD Buffer Description Load BOUT12 Output buffer with 12 mA drive 60 pf BOUT3 BOUTQ B3STA3 B3STA12 B3STAQ 12 Output buffer with 3 mA drive Low noise output buffer with 12 mA drive 3-state output buffer with 3 mA drive 3-state output buffer with 12 mA drive Low noise 3-state output buffer with 12 mA drive Transition 5V 3V Tplh 3.332 5.277 Tphl 2.131 2.842 Tplh 5.358 8.512 Tphl 3.436 4.440 Tplh 3.742 5.696 Tphl 5.515 8.616 Tplh 5.468 8.622 Tphl 3.510 4.617 Tplh 3.475 5.426 Tphl 2.195 2.990 Tplh 3.703 5.776 60 pf 60 pf 60 pf 60 pf 60 pf MG2RTP 4116M–AERO–06/06 MG2RTP Table 6. AC Characteristics - TJ = 25°C, Process typical (all values in ns) VDD Cell Description Load BINCMOS CMOS input buffer 15 fan BINTTL INV NAND2 FDFF BUF4X NOR2 OAI22 OSFF TTL input buffer Inverter 2 - input NAND D flip-flop, Clk to Q High drive internal buffer 2-Input NOR gate 4-input OR AND INVERT gate D flip-flop with scan input, Clk to Q Transition 5V 3V Tplh 0.936 1.430 Tphl 0.776 1.085 Tplh 0.983 1.423 Tphl 0.687 1.081 Tplh 0.564 0.864 Tphl 0.382 0.487 Tplh 0.726 1.076 Tphl 0.599 0.809 Tplh 1.011 1.504 Tphl 0.889 1.360 Ts 0.400 0.615 Th -0.158 -0.290 Tplh 0.813 1.182 Tphl 0.605 0.876 Tplh 0.722 1.204 Tphl 0.347 0.433 Tplh 0.773 1.287 Tphl 0.398 0.510 Tplh 0.981 1.462 Tphl 1.143 1.656 Ts 0.501 0.976 Th -0.480 -0.791 16 fan 12 fan 12 fan 8 fan 51 fan 8 fan 8 fan 8 fan Document Revision History Changes from 4116L 06/05 to 4116M 06-06 1. Correction to Table 4 on page 10 title. 13 4116M–AERO–06/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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