Aeroflex Colorado Springs Standard Products Application Engineering Serial Programming the Aeroflex 64Mbit MRAM for Configuring the Xilinx Virtex-5 FPGA Ron Lake, Sam Stratton Page 1 1 2 3 4 5 Table of Contents Scope.................................................................................................................................................. 5 Overview ........................................................................................................................................... 5 SER2BPI Demonstration in Hardware .......................................................................................... 5 Generate Bit Files of the Aeroflex SER2BPI and User Designs .................................................. 7 Generate a .bin file from .bit file................................................................................................... 10 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 6 Loading the Aeroflex SER2BPI Logic ......................................................................................... 18 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 FPGA Clock Frequency ....................................................................................................................... 18 Open iMPACT ...................................................................................................................................... 18 Load Recent Project ............................................................................................................................. 18 ISE iMPACT ......................................................................................................................................... 19 Add Xilinx Bit File ................................................................................................................................ 19 Navigate to bit file ................................................................................................................................. 20 Ready to Program ................................................................................................................................. 21 Program V5 ........................................................................................................................................... 21 Cancel Verify......................................................................................................................................... 22 Programming In Progress .................................................................................................................... 22 Program Succeeded ............................................................................................................................... 23 Transferring the Binary Configuration File into MRAM .......................................................... 23 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 Create PROM File ................................................................................................................................ 11 Select Storage Target (PROM File Formatter Step 1) ...................................................................... 11 Add Storage Device (PROM File Formatter Step 2) ......................................................................... 12 Add Storage Device (PROM File Formatter Step 2) ......................................................................... 12 Enter Data (PROM File Formatter Step 3) ........................................................................................ 13 Choose File Name and Location (PROM File Formatter Step 3) .................................................... 13 Select OK (PROM File Formatter Step 3).......................................................................................... 14 Add BIT File.......................................................................................................................................... 14 Find BIT File ......................................................................................................................................... 15 Select No to Add Another File ............................................................................................................ 15 Generate PROM File ........................................................................................................................... 16 Data File Assignment ........................................................................................................................... 16 Generate File ........................................................................................................................................ 17 Generate Succeeded.............................................................................................................................. 17 Open Tera Term Program ................................................................................................................... 23 Setup New Connection ......................................................................................................................... 24 Port Selection ........................................................................................................................................ 24 Serial Port Setup Selection ................................................................................................................... 25 Serial Port Parameters ......................................................................................................................... 25 Select Send File ..................................................................................................................................... 26 Choose Binary Option .......................................................................................................................... 26 Choose .bin file ...................................................................................................................................... 27 Sending File ........................................................................................................................................... 27 Test for Correct MRAM File ............................................................................................................... 28 Summary ......................................................................................................................................... 28 Appendix A Configuration Register Modification................................................................... 28 Page 2 List of Figures Figure 1: Overview of Serial Programming Implementation ............................................................. 5 Figure 2: Aeroflex Board Set-up for Serially Loading Configuration into MRAM ......................... 6 Figure 3: Generating a .bit programming file using ISE tools ........................................................... 7 Figure 4: Generating a .bit programming file when using compression ........................................... 8 Figure 5: Selecting compress option for .bit file................................................................................... 9 Figure 6: UCF for Aeroflex RTL to read, format and write the configuration to MRAM ........... 10 Figure 7: iMPACT Software ................................................................................................................ 11 Figure 8: Select Type of PROM to Target .......................................................................................... 11 Figure 9: Select Memory Size .............................................................................................................. 12 Figure 10: Add 64Mbit Storage PROM .............................................................................................. 12 Figure 11: Go to Step 3 ......................................................................................................................... 13 Figure 12: Select File Type, Name and Location ............................................................................... 13 Figure 13: Select OK ............................................................................................................................. 14 Figure 14: Click ‘OK’ to add the desired .bit file .............................................................................. 14 Figure 15: Choose Desired .bit file ...................................................................................................... 15 Figure 16: Select No to Adding another File ...................................................................................... 15 Figure 17: Device File Entry Complete ............................................................................................... 16 Figure 18: Data File Assignment ......................................................................................................... 16 Figure 19: Generate File ....................................................................................................................... 17 Figure 20: Generate File Succeeded .................................................................................................... 17 Figure 21: Select ‘No’ to reject automatic creation of a project....................................................... 18 Figure 22: ‘Cancel’ load of an existing design.................................................................................... 18 Figure 23: Double click on ‘Boundary Scan’ ..................................................................................... 19 Figure 24: Right click in blue dialog box ............................................................................................ 19 Figure 25: Add Xilinx device ............................................................................................................... 20 Figure 26: Locate .bit file for ser2bpi.................................................................................................. 20 Figure 27: Ready to program............................................................................................................... 21 Figure 28: Select ‘Program’ ................................................................................................................. 21 Figure 29: Device Programming Properties. Select ‘Cancel’ ........................................................... 22 Figure 30: Programming in Progress .................................................................................................. 22 Figure 31: V-5 Programming Succeeded ............................................................................................ 23 Figure 32: New Connection .................................................................................................................. 24 Figure 33: Port Selection ...................................................................................................................... 24 Figure 34: Select Serial Port Setup...................................................................................................... 25 Figure 35: Serial Port Parameters....................................................................................................... 25 Figure 36: Select Send File ................................................................................................................... 26 Figure 37: Choose Binary Option (Critical) ....................................................................................... 26 Figure 38: Select .bin file ...................................................................................................................... 27 Figure 39: Sending File Window ......................................................................................................... 27 Figure 40: Definition of Serial Sampling Register Count for Different V-5 Clock Frequencies ... 29 Table 1 Pin Assignments for SER2BPI Application 10 Page 3 Revision History REV DESCRIPTION OF CHANGE Number 1.0 APPROVED BY R Lake S Stratton DATE APPROVED Page 4 1 Scope This document outlines the steps required to load a user’s V-5 configuration file into the Aeroflex UT8MR8M8 64Mbit MRAM device and subsequently allow the V-5 to boot by means of the UT8MR8M8 MRAM. 2 Overview Figure 1 shows a high-level view summarizing the hardware requirements and notional solution. The goal is to provide a straightforward approach to load a user configuration file into the Aeroflex 64Mbit MRAM, which will then configure the V-5 during its boot process. The Aeroflex RTL solution configures the V-5 to transfer the user’s bit stream through a serial input port and into the MRAM through the BPI. After transfer to the non-volatile MRAM, the user’s design loads into the V-5 through the BPI during power-up in the BPI-Up operating mode. In the discussion to follow, we refer to the Aeroflex RTL to program the MRAM by the name “SER2BPI”. We refer to the configuration file for the user application as “USERAPP”. Figure 1 Overview of Serial Programming Implementation 3 SER2BPI Demonstration in Hardware Aeroflex validated the SER2BPI design in hardware. The hardware-based demonstration proves the entire process of loading a user design into the non-volatile 64Mbit MRAM to configure a Xilinx V-5. The solution is practical and easy to adapt. The IP/hardware requires a serial RCV pin and the BPI on the V-5 to program the user’s binary configuration file into the MRAM. Figure 2 shows the demonstration hardware. It includes a Xilinx Virtex-5 evaluation board with a XC5VFS130T FPGA, a JTAG connector for the Xilinx USB Platform cable and two FMC (FPGA Mezzanine Card) connectors. Aeroflex designed a mezzanine card containing the 64Mbit MRAM and a mating FMC connector to insert into the V-5 board. The FMC connector maps to BPI pins on the V-5. Aeroflex added the USB to Serial UART connector to the V-5 board and mapped the serial data input to a user defined I/O on the V-5. Page 5 Figure 2 Aeroflex Board Set-up for Serially Loading Configuration into MRAM The MRAM programming and V-5 configuration process is the following: 1) Use the Xilinx ISE tools to compile the Aeroflex RTL, “SER2BPI.v” (or .vhd) into a bit file, “SER2BPI.bit”. Then compile the user application, “USERAPP.v” (or .vhd) into a second bit file “USERAPP.bit”. 2) Use the ISE iMPACT tool to create a binary format PROM file “USERAPP.bin” from the “USERAPP.bit” file 3) Use ISE iMPACT to program “SER2BPI.bit” into the V-5 through the standard JTAG connector and a Xilinx Platform Cable. 4) With the SER2BPI application running in the V-5, use a PC serial data transfer tool such as Tera Term to transmit the “USERAPP.bin” file over a USB port on the PC and into the SER2BPI UART receive input on the V-5. 5) The SER2BPI routine running in the V-5 receives the “USERAPP.bin” file, serially formats it into bytes, checks parity and loads each byte into the MRAM through the BPI on the V-5. 6) In order to load the “USERAPP.bin” configuration from the MRAM through the BPI connection, cycle power on the V-5 or toggle the PROGRAM_B b pin. The mode pins on the V5 should be set to M[2:0] = 010 to define the V-5 for BPI-Up configuration. The detailed specifics for the above flow are the topics of the remaining chapters in this application note. Page 6 4 Generate Bit Files of the Aeroflex SER2BPI and User Designs The user generates .bit files for both the SER2BPI code to transfer serial data and the USERAPP code representing the user’s design application. The ISE iMPACT tools can also compress the “USERAPP.bit” file to minimize memory usage in the MRAM. In many instances, a compressed XQR5VFX130 application can fit within an Aeroflex 16Mbit MRAM. For systems requiring in-flight reconfiguration, the user can merge these two programs into a single design to support both the final application as well as an in-flight serial update capability. For the purposes of this application note, these RTL files remain separate to demonstrate the in-direct, serial programming flow and identify the features and constraints of the SER2BPI code. Figure 3 shows the ISE options to generate a .bit file from the SER2BPI RTL. Figure 3 Generating a .bit programming file using ISE tools The “ser2bpi_top”, “serial_rec” and “mram_wr” files contain the RTL code (in this case, Verilog) to read, format, parity check and transfer the USERAPP bit stream into MRAM. The constraint file, “ser2bpi.ucf”, assigns the I/O that interface between the in-coming serial data and the BPI of the Xilinx V-5. Selecting Page 7 these files and running the “Generate Programming File” option synthesizes the “SER2BPI.bit” configuration file from the Aeroflex RTL. Use this same procedure to create a .bit file for the user’s custom design (USERAPP). The user may compress the .bit files upon generation. Figures 4 and 5 show the ISE steps necessary to generate a compressed .bit file. Figure 4 Generating a .bit programming file when using compression Page 8 Figure 5 Selecting compress option for .bit file Figure 6 shows the contents of the UCF constraint file for the SER2BPI RTL. NET "ser_da_in” IOSTANDARD=LVCMOS33 | LOC="AE10"; NET "clk" IOSTANDARD=LVCMOS33 | LOC="AM16"; NET "por_n" IOSTANDARD=LVCMOS33 | LOC="AB34"; NET "W_L" IOSTANDARD=LVCMOS33 | LOC="AM28"; NET "G_L" IOSTANDARD=LVCMOS33 | LOC="AM13"; NET "CE_L" IOSTANDARD=LVCMOS33 | LOC="AL14"; NET "par_err_flag" IOSTANDARD=LVCMOS33 | LOC="AF36"; NET "data<0>" NET "data<1>" NET "data<2>" NET "data<3>" NET "data<4>" NET "data<5>" NET "data<6>" NET "data<7>" IOSTANDARD=LVCMOS33 | LOC="AJ26"; IOSTANDARD=LVCMOS33 | LOC="AK27"; IOSTANDARD=LVCMOS33 | LOC="AM14"; IOSTANDARD=LVCMOS33 | LOC="AN14"; IOSTANDARD=LVCMOS33 | LOC="AK29"; IOSTANDARD=LVCMOS33 | LOC="AK28"; IOSTANDARD=LVCMOS33 | LOC="AP13"; IOSTANDARD=LVCMOS33 | LOC="AN13"; NET "addr<0>" NET "addr<1>" NET "addr<2>" NET "addr<3>" NET "addr<4>" NET "addr<5>" NET "addr<6>" NET "addr<7>" NET "addr<8>" NET "addr<9>" NET "addr<10>" NET "addr<11>" NET "addr<12>" NET "addr<13>" NET "addr<14>" NET "addr<15>" NET "addr<16>" NET "addr<17>" NET "addr<18>" NET "addr<19>" NET "addr<20>" NET "addr<21>" NET "addr<22>" IOSTANDARD=LVCMOS33 | LOC="P13"; IOSTANDARD=LVCMOS33 | LOC="N13"; IOSTANDARD=LVCMOS33 | LOC="M29"; IOSTANDARD=LVCMOS33 | LOC="N30"; IOSTANDARD=LVCMOS33 | LOC="M13"; IOSTANDARD=LVCMOS33 | LOC="M14"; IOSTANDARD=LVCMOS33 | LOC="N29"; IOSTANDARD=LVCMOS33 | LOC="N28"; IOSTANDARD=LVCMOS33 | LOC="N14"; IOSTANDARD=LVCMOS33 | LOC="N15"; IOSTANDARD=LVCMOS33 | LOC="P28"; IOSTANDARD=LVCMOS33 | LOC="P27"; IOSTANDARD=LVCMOS33 | LOC="N16"; IOSTANDARD=LVCMOS33 | LOC="M16"; IOSTANDARD=LVCMOS33 | LOC="N26"; IOSTANDARD=LVCMOS33 | LOC="P26"; IOSTANDARD=LVCMOS33 | LOC="P17"; IOSTANDARD=LVCMOS33 | LOC="P18"; IOSTANDARD=LVCMOS33 | LOC="P25"; IOSTANDARD=LVCMOS33 | LOC="N25"; IOSTANDARD=LVCMOS33 | LOC="AM29"; IOSTANDARD=LVCMOS33 | LOC="AL30"; IOSTANDARD=LVCMOS33 | LOC="AK14"; NET "W_L" NET "G_L" PULLUP; PULLUP; Page 9 NET "CE_L" Figure 6 PULLUP; NET "data<1>" NET "data<2>" NET "data<3>" NET "data<4>" NET "data<5>" NET "data<6>" NET "data<7>" PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; NET "addr<0>" NET "addr<1>" NET "addr<2>" NET "addr<3>" NET "addr<4>" NET "addr<5>" NET "addr<6>" NET "addr<7>" NET "addr<8>" NET "addr<9>" NET "addr<10>" NET "addr<11>" NET "addr<12>" NET "addr<13>" NET "addr<14>" NET "addr<15>" NET "addr<16>" NET "addr<17>" NET "addr<18>" NET "addr<19>" NET "addr<20>" NET "addr<21>" NET "addr<22>" PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; PULLUP; UCF for Aeroflex RTL to read, format and write the configuration to MRAM This UCF contains several pin assignments that are specific to the SER2BPI application and a larger number of pin assignments that are required to interface the control, address and data signals of the MRAM to the Xilinx V-5 BPI. The fixed V-5 BPI pins connect to the 8-bit data bus, 23-bit address bus, read/write (W_L), output enable (G_L) and chip select (CE_L) signals on the 64 Mbit MRAM. The SER2BPI application also assigns non-fixed signals to generic bidirectional I/O as shown in Table 1. The user may redefine these signals based on the needs of their application. Table 1 Pin Assignments for SER2BPI Application Signal Name Pin assignment Function ser_da_in clk por_n W_L G_L CE_L par_err_flag AE10 AM16 AB34 AM28 AM13 AL14 AF36 Receive port for serial input data Connected to 50MHz clock oscillator Resets all internal counters in SER2BPI Read / Write. Write active low (fixed) Output enable, active low (fixed) Chip enable, active low (fixed) Parity error detected 5 Generate a .bin file from .bit file The next step in the serial flow is to convert the USERAPP design from a .bit file into a .bin binary file for serial transfer to the V-5. This process uses the ISE iMPACT software as shown in the following sections. Page 10 5.1 Create PROM File Start by opening ISE and selecting the iMPACT tool. The displayed window should look like the one shown in Figure 7. Double click on the dialog ‘Create PROM File (PROM File Format..) as shown in Figure 7. Figure 7 5.2 iMPACT Software Select Storage Target (PROM File Formatter Step 1) The next window to appear should look like Figure 8. Double click in the area identified by the large black arrow to select Generic Parallel PROM format for the translated USERAPP file. Figure 8 Select Type of PROM to Target Page 11 5.3 Add Storage Device (PROM File Formatter Step 2) Select the memory size shown in Figure 9. You should select 64M [67208864] for the Aeroflex 64Mbit MRAM. For smaller, compressed designs that use the Aeroflex 16 Mbit MRAM, you may select 16M [16777216] from the menu. Figure 9 5.4 Select Memory Size Add Storage Device (PROM File Formatter Step 2) Click ‘Add Storage Device’ as shown in Figure 10. Figure 10 Add 64Mbit Storage PROM Page 12 5.5 Enter Data (PROM File Formatter Step 3) Next, click the green arrow as shown in Figure 11, which takes the user to Step 3 in the PROM File Formatter window shown in Figure 12. Figure 11 5.6 Go to Step 3 Choose File Name and Location (PROM File Formatter Step 3) Name your output file name and directory. Figure 12 has the file “userapp” highlighted in orange and the output directory “C:/Desktop” highlighted in blue. Choose the File Format drop down menu and select BIN (Swap Bits ON). Figure 12 Select File Type, Name and Location Page 13 5.7 Select OK (PROM File Formatter Step 3) The final step prior to generating the .bin file is to click ‘Ok’ as shown in Figure 13 to accept the defined PROM file format. Figure 13 5.8 Select OK Add BIT File To add the .bit file you wish to load into MRAM, first click OK in the dialogue box to start adding device files as shown in Figure 14. Figure 14 Click ‘OK’ to add the desired .bit file Page 14 5.9 Find BIT File Navigate to the directory where the .bit file is located as in Figure 15. Figure 15 Choose Desired .bit file 5.10 Select No to Add Another File iMPACT will ask if you want to add another device file. Click ‘No’ as in Figure 16. Figure 16 Select No to Adding another File Page 15 5.11 Generate PROM File Click ‘OK’ to confirm your design file definition as in Figure 17. Figure 17 Device File Entry Complete 5.12 Data File Assignment Click ‘OK’ to confirm the start address as in Figure 18. Figure 18 Data File Assignment Page 16 5.13 Generate File Double click on ‘Generate File…’ in the iMPACT Processes window as in Figure 19. Figure 19 Generate File 5.14 Generate Succeeded With all inputs defined correctly, the iMPACT tool generates a “USERAPP.bin” file from the “USERAPP.bit” file and the user sees the window shown in Figure 20. This completes the Generate Binary File part of the serial loading of the MRAM. Figure 20 Generate File Succeeded Page 17 6 Loading the Aeroflex SER2BPI Logic Note that the following steps are the standard method to program virtually all Xilinx FPGA devices. 6.1 FPGA Clock Frequency The example design use a 50MHz input clock. Users that implement a different sampling clock frequency must refer to Appendix A at the end of this document to take the steps required to change setup the design for proper operation. 6.2 Open iMPACT Open iMPACT by locating the ISE Design tools. When the program opens, the first window that appears asks whether to create and save a project automatically. Select ‘No’ as shown in Figure 21. Figure 21 6.3 Select ‘No’ to reject automatic creation of a project Load Recent Project Since this is the initial set-up for the design, the user should select ‘Cancel’ when asked to load an existing design, as shown in Figure 22. Figure 22 ‘Cancel’ load of an existing design Page 18 6.4 ISE iMPACT The ISE iMPACT tool will now open and appear as shown in Figure 23. Double click on the ‘Boundary Scan’ icon. Figure 23 6.5 Double click on ‘Boundary Scan’ Add Xilinx Bit File In the upper right hand portion of the ISE iMPACT application window shown in Figure 24, ‘Right click to Add Device or Initialize JTAG chain’ as the dialog box directs. Select ‘Add Xilinx Device…’ as shown in Figure 25, then navigate to where the desired .bit file is located. Figure 24 Right click in blue dialog box Page 19 Figure 25 6.6 Add Xilinx device Navigate to bit file Navigate to the storage location of the .bit file you intend on loading into the Xilinx FPGA. In this case, select ser2bpi and click ‘Open” as shown in Figure 26. Figure 26 Locate .bit file for ser2bpi Page 20 6.7 Ready to Program The iMPACT tool is now ready to program the V-5. The iMPACT screen should look similar to Figure 27. Figure 27 6.8 Ready to program Program V5 Right click and select ‘Program’ as shown in Figure 28. Figure 28 Select ‘Program’ Page 21 6.9 Cancel Verify Select ‘Cancel’ when the Device Programming Properties window appears, as shown in Figure 29. Figure 29 Device Programming Properties. Select ‘Cancel’ 6.10 Programming In Progress The window shown in Figure 30 will appear. It shows the progress of the V5 programming Figure 30 Programming in Progress Page 22 6.11 Program Succeeded When programming is complete and no errors occurred, you will see the window shown in Figure 31. The V-5 is now programmed and ready to operate. Figure 31 V-5 Programming Succeeded 7 Transferring the Binary Configuration File into MRAM Once the “SER2BPI.bit” routine is running within the V-5, the following steps transfer the “USERAPP.bin file” through the V5 and into the MRAM. Note that Aeroflex chose to use the PC program Tera Term to transfer the “USERAPP.bin” file out of a USB port on the PC and to the USB to Serial connector on the V5 demonstration board. Other options exist for this data transfer; however, the following discussion assumes use of Tera Term. The user should follow a similar flow if using a different PC routine for data transfer. 7.1 Open Tera Term Program Find the Tera Term program on the computer intended for loading the MRAM and open the program. Page 23 7.2 Setup New Connection The first dialogue that appears when opening the Tera Term program is the ‘New Connection’ window. Here, the user should select ‘Serial’ as shown in Figure 32. Figure 32 7.3 New Connection Port Selection Since most desktop and laptop PCs no longer have a serial port, there are options to use USB ports for serial connections. In the example shown in Figure 33, the choice of the USB Serial Port (COM5) is correct because this evaluation board uses a USB to Serial converter connector. Figure 33 Port Selection Page 24 7.4 Serial Port Setup Selection There are several setup parameters to modify prior to sending a binary file. To do this, go to the ‘Setup’ menu in the Tera Term window and choose “Serial port… “as shown in Figure 34. Figure 34 7.5 Select Serial Port Setup Serial Port Parameters Most of the default settings are correct for the serial port setup. Figure 35 highlights the two that need modification. In orange highlight is the Baud rate. It should be set to 921600 as shown. As discussed previously, the Aeroflex routine has counters defined to receive data at this frequency. Select Odd Parity for the serial interface as shown by the parameter highlighted in blue. Figure 35 Serial Port Parameters This defines the serial data transfer as follows: Start bit (active low), D0, D1, D2, D3, D4, D5, D6, D7, Parity (odd), Stop bit (active high) Page 25 7.6 Select Send File From the ‘File’ menu in the Tera Term program select ‘Send file…’ as shown in Figure 36. Figure 36 7.7 Select Send File Choose Binary Option It is critical that the user set the option for Binary in the Send File window. See Figure 37 for reference. The “USERAPP.bin” file will not load properly and the resulting V-5 configuration will be indeterminate if the Binary Option is not set. Figure 37 Choose Binary Option (Critical) Page 26 7.8 Choose .bin file Navigate to the directory where the .bin file resides (Refer to Section 4 for steps to generate .bin files) and select the desired file as shown in Figure 38. Note that when you select ‘Open’ in the Send file window shown in Figure 38, the file transfer to the V5 will begin. Figure 38 7.9 Select .bin file Sending File While the “USERAPP.bin” application transfers to the V5, the window shown in Figure 39 appears. When it completes, the Figure 39 window will disappear. Figure 39 Sending File Window Page 27 7.10 Test for Correct MRAM File The user should now cycle power on their V5 circuit board allowing the FPGA to configure itself from MRAM. 8 Summary The previous sections describe indirect programing of an MRAM through a Xilinx V-5 FPGA with a user configuration file. They propose a hardware configuration with a USB to Serial connector to receive a binary configuration file from a data transfer routine such as Tera Term. Steps identify the ISE iMPACT software to generate .bit configuration files from the Aeroflex and user RTL. These steps translate the “USERAPP.bit” file to a “USERAPP.bin” binary file for serial transmission. Then, the Aeroflex “SER2BPI.bit” configuration running in the Xilinx V-5 transfers the “USERAPP.bin” configuration from the PC through the BPI of the V-5 and into the MRAM. Some steps in this flow may vary, depending on the hardware and PC routines available to the individual user. However, the general flow remains the same and allows the user to transfer their design into the MRAM so that it will configure the V-5 when it loads into the FPGA through the BPI following power-on or the assertion of the program_b reset pin. 9 APPENDIX A Configuration Register Modification The clock frequency of the V-5 and the transfer rate of the serial data define the timing necessary to capture the incoming serial data. The “SER2BPI” routine defines a data count register using an incoming data rate of 921.6Kbs and a clock frequency of 50MHz. Section 7 shows how to assign this transfer rate for the incoming serial data. If the user clock frequency for the V-5 differs from 50MHz, then count_register in the RTL for the “SER2BPI.bit” routine must define a new value. Comments in the Aeroflex RTL file ser2bpi_top.v or .vhd define this formula, as shown in Figure 40. ((1/921600) / (1/F)) – 1 = count_register The SER2BPI RTL must assign the new count_register value prior to compiling it into the “SER2BPI.bit” file. This supports a sampling rate where 3 samples are taken for each incoming data bit and “2 out of 3” voting is used to define the incoming bit state. Page 28 *********************************************************************** // Set Sample Count Register. The register 'count_register' is very // important for this design. The register sets how many 'clk' counts to // use before sampling the incoming serial data. For these files the clk // was set to 50MHz. Also, the entire design is set to receive data at a // rate of 921600bs. So to set the correct count, the user must use the // formula below. // ((1/921600) / (1/F)) - 1 = count_register // Where F = the clk Frequency // Here is an example count_register setting if the clk is 80MHz // ((1/921600) / (1/80MHz)) - 1 = 85.8 // Round up and convert to hex = 56 Hex // Note that there may be adjustments made in the count either up or // down due to the fact that many clk frequency choices do not evenly divide // into 921600. So for a clk of 80MHz, there may be the need to set the // count_register value to 55 Hex. Some experimentation may be necessary. // ************************************************************************ assign count_register = 8'h35; // Sample count if clk = 50MHz //assign count_register = 8'h20; // Sample count if clk = 30MHz //assign count_register = 8'h56; // Sample count if clk = 80MHz // *********************************************************************** // End of Set Sample Count Register. // *********************************************************************** Figure 40 Definition of Serial Sampling Register Count for Different V-5 Clock Frequencies Page 29