Standard Products UT8MR8M8 64Megabit Non-Volatile MRAM Datasheet March 2015 www.aeroflex.com/memories FEATURES Single 3.3-V power supply Fast 50ns read/write access time Functionally compatible with traditional asynchronous SRAMs Equal address and chip-enable access times INTRODUCTION The Aeroflex 64Megabit Non-Volatile magnetoresistive random access memory (MRAM) is a high-performance memory multichip module (MCM) compatible with traditional asynchronous SRAM operations, organized as either four 2M words by 8 bits or one 8M words by 8 bits. HiRel temperature range (-40oC to +105oC) Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss CMOS and TTL compatible The MRAM is equipped with five chip enables (/En), a single write enable (/W), and a single output enable (/G) pins, allowing for significant system design flexibility without bus contention. Data is non-volatile for > 20 years at temperature and data is automatically protected against power loss by a low voltage write inhibit. Data non-volatile for > 20 years (-40oC to +105oC) Read/Write endurance: Unlimited for 20 years (-40oC to +105oC) 64-pin ceramic flatpack package Operational environment: - Total dose: 1 Mrad(Si) The 64Mb MRAM is designed specifically for operation in HiREL environments. As shown in Table 4, the magnetoresistive bit cells are immune to Single Event Effects (SEE). To guard against transient effects, an Error Correction Code (ECC) is included within the device. ECC check bits are generated and stored within the MRAM array during writes. The MBE pin identifies that ECC logic has detected two bit errors during the current read cycle. - SEL Immune: 112 MeV-cm2/mg @125oC - SEU Immune: Memory Cell 112 MeV-cm2/mg @25oC Standard Microelectronics Drawing (SMD) - 5962-13207 - QML Q, Q+, and V pending Figure 1. UT8MR8M8 MRAM Block Diagram 36-00-01-000 Ver. 1.0.0 1 Aeroflex Microelectronic Solutions - HiRel PIN NAMES Table 1. 8M x 8 Pin Functions VSS VDD VSS VSS /E0 A4 A3 A2 A1 A0 A19 ZZ/RST NUO DQ4 DQ5 VDD VSS DQ6 DQ7 /E1 /E_All A21 A22 A9 A8 A7 A6 A5 VSS VSS VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD VSS VSS VSS /E3 A20 A15 A16 A17 A18 VSS /G VSS DQ3 DQ2 VSS VDD DQ1 DQ0 /E2 VSS MBE /W A10 A11 A12 A13 A14 VSS VSS VDD VSS Signal Name A[22:0] Address Input /E[3:0]1 Chip Enable /E_All Chip Enable All /W Write Enable /G Output Enable DQ[7:0] Data I/O VDD Power Supply VSS Ground ZZ/RST Deep Power Down/Reset MBE2 Multi-Bit Error Flag NUO Not used output Do not connect Driven internally *Notes: 1.Only one /E[3:0] pin may be active at any time. 2. MBE pin is not functionally tested for prototypes. Table 2. Chip Enable Functions Table Figure 2. 40ns MRAM Pinout (64) /E_ALL /E_0 /E_1 /E_2 /E_3 A22 A21 Comment 0 1 1 1 1 0 0 MRAM Die 0 Enabled 0 1 1 1 1 0 1 MRAM Die 1 Enabled 0 1 1 1 1 1 0 MRAM Die 3 Enabled 0 1 1 1 1 1 1 MRAM Die 2 Enabled 1 0 1 1 1 X X MRAM Die 0 Enabled 1 1 0 1 1 X X MRAM Die 1 Enabled 1 1 1 0 1 X X MRAM Die 2 Enabled 1 1 1 1 0 X X MRAM Die 3 Enabled DEVICE OPERATION The UT8MR8M8 has control inputs called Chip Enable (/ E[3:0]), Chip Enable All (/E_ALL), Write Enable (/W), Output Enable (/G), and sleep/reset mode (ZZ/RST); 23 address inputs, A[22:0]; eight bidirectional data lines, DQ[7:0]; and a Multi-bit Error Flag (MBE). /E[3:0] controls device selection, active, and standby modes. Asserting /E[3:0] enables the device, causes IDD to rise to its active value, and decodes the 21 address inputs, A[20:0], to select one of 16,777,216 words in the memory. Note: Only one Chip Enable may be active at any time. Asserting / E_ALL allows the device to be addressed as a single, 64Mb memory using address bits A21 and A22 to decode and select 1 of 4 MRAM die. /W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs. ZZ/RST controls the sleep/reset mode operation and provides device reset capability. Enabling sleep/reset mode causes all other inputs to be don't cares. ZZ/RST places all die into internal low power even while system power is still applied to VDD. The MBE pin is an open drain in which when pulled down, it identifies that ECC logic has detected two bit errors during the current read cycle. It allows for wired-or of multiple MBE when using multiple MRAMs. 36-00-01-000 Ver. 1.0.0 Function *Note: Only one /E[3:0] pin may be active at any time. 2 Aeroflex Microelectronic Solutions - HiRel Write Cycle 2, the Chip Enable-controlled Access in Figure 5b, is defined by a write terminated by a single /En going VDD DQ[7:0] inactive. The write pulse width is defined by tWLEH when the write is initiated by /W, and by tELEH when the write is initiated Current by a single /En going active. For the /W initiated write, unless QIZZ HI-Z the outputs have been previously placed in the high-impedance state by /G, the user must wait tWLQZ before applying data to QIDD HI-Z the eight bidirectional pins DQ[7:0] to avoid bus contention. Table 3. Device Operation Truth Table ZZ/ RST /E[3:0]* /G /W Mode H X X X Deep Sleep/ Reset Mode L H X X Not Selected L L H H Output Disabled IDDR HI-Z L L L H Byte Read IDDR DOUT L L X L Byte Write IDDW DIN OPERATIONAL ENVIRONMENT The UT8MR8M8 MRAM incorporates special design and layout features which allows operation in harsh environments. Table 4. Operational Environment Design Specifications *Note: Only one /E[3:0] pin may be active at any time. READ CYCLE A combination of /W greater than VIH (min) and a single /En less than VIL (max) defines a read cycle. Read access time is measured from the latter of chip enable, output enable, or valid address to valid data output. MRAM Read Cycle 1, the Address Access in Figure 4a, is initiated by a change in address inputs after a single /En is asserted, /G asserted and /W deasserted. Valid data appears on data outputs DQ[7:0] after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as a single chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). LIMIT UNITS TID 1 Mrad(Si) SEL Immunity1 < 112 MeV-cm2/mg SEU Memory Cell Immunity2 < 112 MeV-cm2/mg Notes: 1. SEL test performed at VDD = 3.6V and temperature = 125oC. 2. SEU test performed at VDD = 3.0V and unpowered at room temperature. POWER UP AND POWER DOWN SEQUENCING The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The /En and /W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so the signal remains high if the driving signal is Hi-Z during power up. Any logic that drives /En and /W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). MRAM Read Cycle 2, the Chip Enable-controlled Access in Figure 4b, is initiated by a single /En going active while /G remains asserted, /W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A[20:0] is accessed and appears at the data outputs DQ[7:0]. WRITE CYCLE A combination of /W and a single /En less than VIL(max) defines a write cycle. The state of /G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either /G is greater than VIH(min), or when /W is less than VIL(max). The MRAM supports sleep/reset mode operation using the ZZ/RST control pin. To enter sleep mode/reset, ZZ/RST must be pulled high. The device will enter sleep/reset mode within 40ns. In order to exit sleep/reset mode, /En and /W must be high before ZZ/RST is pulled low. As soon as ZZ/ RST is driven low, the user must allow 100us before performing any other operation in order for the device to properly initialize. Aeroflex recommends designing a system level method to toggle the ZZ/RST pin in order to reset the MRAM device. Write Cycle 1, the Write Enable-controlled Access in Figure 5a, is defined by a write terminated by /W going high, with a single /En still active. The write pulse width is defined by tWLWH when the write is initiated by /W, and by tETWH when the write is initiated by a single /En. Unless the outputs have been previously placed in the high-impedance state by /G, the user must wait tWLQZ before applying data to the nine bidirectional pins DQ[7:0] to avoid bus contention. 36-00-01-000 Ver. 1.0.0 PARAMETER 3 Aeroflex Microelectronic Solutions - HiRel Figure 4. UT8MR2M8 Power Up and Power Down Sequencing Diagram 36-00-01-000 Ver. 1.0.0 4 Aeroflex Microelectronic Solutions - HiRel ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) The device contains protection against magnetic fields. Precautions should be taken to avoid device exposure of any magnetic field intensity greater than specified. SYMBOL PARAMETER VDD Supply VIN Voltage on any pin2 IIO DC I/O current per pin @ TJ = 125° for 20yrs PD Package power dissipation3 TJ Maximum junction temperature θJC Thermal resistance junction to case – Single Die Voltage2 VALUE UNIT -0.5 to 4.3 V -0.5 to VDD+0.5 V ± 20 mA 4 W +125 C 5 o C/W -65 to +125 oC ESD >2000 V H max_write Maximum magnetic field during write 8000 A/m H max_read Maximum magnetic field during read or standby 8000 A/m TSTG ESDHBM Storage temperature o Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment. RECOMMENDED OPERATING CONDITIONS SYMBOL TC PARAMETER Operating case temperature LIMITS -40oC to +105oC VDD Operating supply voltage 3.0V to 3.6V VWI Write inhibit voltage 2.5V to 3.0V1 VIH Input high voltage 2.2V to VDD+0.3V VIL Input low voltage VSS-0.3V to 0.8V Notes: 1. After power up or if VDD falls below VWI, a waiting period of 2 ms must be observed, and /En and /W must remain high for 2 ms. Memory is designed to prevent writing for all input pin conditions if VDD falls below minimum VWI. 36-00-01-000 Ver. 1.0.0 5 Aeroflex Microelectronic Solutions - HiRel DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* VDD = 3.0V to 3.6V; Unless otherwise noted, Tc is per the temperature ordered. SYMBOL PARAMETER CONDITION MIN MAX VIH High-level input voltage VIL Low-level input voltage VOL1 Low-level output voltage IOL = 4mA,VDD =VDD (min) VOL2 Low-level output voltage IOL = + 100μA,VDD =VDD (min) VOH1 High-level output voltage IOH = -4mA,VDD =VDD (min) VOH2 High-level output voltage IOH = -100μA,VDD =VDD (min) CIN1 Input capacitance ƒ = 1MHz @ 0V 50 pF CIO1 Bidirectional I/O capacitance ƒ = 1MHz @ 0V 60 pF Input leakage current VIN = VDD and VSS -1 +1 μA Input leakage current ZZ/RST VIN = VDD and VSS -0.25 0.25 μA IOZ Three-state output leakage current VO = VDD and VSS, VDD = VDD (max) /G = VDD (max) -1 +1 μA IOS2, 3 Short-circuit output current VDD = VDD (max), VO = VDD VDD = VDD (max), VO = VSS -100 +100 mA IDDR Active read supply current Read mode ƒ = max (IOUT = 0mA; VDD = max) 140 mA IDDW Active write supply current Write mode ƒ = 10 MHz (VDD = max) 140 mA QIDD Quiescent supply current CMOS leakage current (/E = VDD; all other inputs equal VSS or VDD; VDD = max) 30 mA 35 mA 1 mA IIN IINZZ QIZZ4 Deep power down and reset supply current 2.0 UNIT CMOS leakage current (/E = VDD; all other inputs equal VSS or VDD; VDD = max) -40oC V 0.8 V 0.4 V VSS+0.2 V 2.4 V VDD-0.2 V o +25 C +105oC Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. Allow 100μs to exit sleep/reset mode before performing any other operation. 36-00-01-000 Ver. 1.0.0 6 Aeroflex Microelectronic Solutions - HiRel AC CHARACTERISTICS READ CYCLE1 (Pre and Post-Radiation)* VDD = VDD (min); Unless otherwise noted, Tc is per the temperature ordered SYMBOL PARAMETER MIN MAX UNIT tAVAV Read cycle time tAVQV Address access time 50 ns ns tELQV2 Enable access time 50 ns tGLQV Output enable access time 25 ns tAXQX Output hold from address change 3 ns tELQX3 Enable low to output active 3 ns tGLQX3 Output enable low to output active 0 ns Enable high to output Hi-Z 0 15 ns Output enable high to output Hi-Z 0 15 ns tEHQZ3 tGHQZ3 50 Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. /W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2. Address valid before or at the same time /En goes low. 3. Transition is measured at +/-400mV from the steady-state voltage. 36-00-01-000 Ver. 1.0.0 7 Aeroflex Microelectronic Solutions - HiRel (/En < VIL, G < VIL). Figure 4a. MRAM Read Cycle 1 /En Figure 4b. MRAM Read Cycle 2 36-00-01-000 Ver. 1.0.0 8 Aeroflex Microelectronic Solutions - HiRel AC CHARACTERISTICS /W CONTROLLED WRITE CYCLE (Pre and Post-Radiation)* VDD= VDD (min); Unless otherwise noted, Tc is per the temperature ordered. SYMBOL PARAMETER MIN MAX UNIT tAVAV2 Write cycle time 50 tAVWL Address set-up time 0 ns ns tAVWH Address valid to end of write (/G high) 28 ns tAVWH Address valid to end of write (/G low) 28 Write pulse width (/G high or low) 28 ns ns tDVWH Data valid to end of write 10 ns tWHDX Data hold time 0 ns tWLQZ3 Write low to data Hi-Z 0 tWHQX3 Write high to output active 3 ns tWHAX Write recovery time 16 ns tWLWH tWLEH 15 ns Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. All write occurs during the overlap of /En low and /W low. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. If /G goes low at the same time or after /W goes low, the output will remain in a high impedance state. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. Transition is measured +/-400mV from the steady-state voltage. /En Figure 5a. MRAM Write Cycle 1 (/W Controlled Access) 36-00-01-000 Ver. 1.0.0 9 Aeroflex Microelectronic Solutions - HiRel AC CHARACTERISTICS /En CONTROLLED WRITE CYCLE1 (Pre and Post-Radiation)* VDD= VDD (min); Unless otherwise noted, Tc is per the temperature ordered. SYMBOL PARAMETER MIN MAX UNIT tAVAV2 Write cycle time 50 tAVEL Address set-up time 0 ns ns tAVEH Address valid to end of write (/G high) 28 ns tAVEH Address valid to end of write (/G low) 28 ns Enable to end of write (/G high) 28 Enable to end of write (/G low) 28 tDVEH Data valid to end of write 10 ns tEHDX4 Data hold time 0 ns tEHAX4 Write recovery time 16 ns tELEH tELWH tELEH3 tELWH3 ns ns Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. All write occurs during the overlap of /En low and /W low. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. If /G goes low at the same time or after /W goes low, the output will remain in a high impedance state. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. If /En goes low at the same time or after /W goes low, the output will remain in a high-impedance state. If /En goes high at the same time or before /W goes high, the output will remain in a high-impedance state. 4. Transition is measured +/-400mV from the steady-state voltage. /En Figure 5b. MRAM Write Cycle 2 (/En Controlled) 36-00-01-000 Ver. 1.0.0 10 Aeroflex Microelectronic Solutions - HiRel AC CHARACTERISTICS SLEEP/RESET MODE (Pre and Post-Radiation)* VDD= VDD (min); Unless otherwise noted, Tc is per the temperature ordered. SYMBOL tZZL1,3 PARAMETER MIN Sleep/reset mode exit delay MAX UNIT 100 tZZH2,3 tEZZ3 Sleep/reset mode access time 50 μs ns Sleep/reset mode exit setup time 0 ns tZZS3 Sleep/reset mode settle time 200 μs Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. /En and /W must be high when ZZ/RST is pulled low in order to exit sleep/reset mode. 2. ZZ/RST must be high for 40ns in order to enter sleep/reset mode. 3. Parameters are supplied as a design limit, but are not tested nor guaranteed. tZZS tZZH tZZL IDDW tEZZ ZZ/RST /E /W Figure 6. MRAM Sleep/Reset Mode Timing Diagram VDD VDD RTERM 100-ohms DUT Test Point Zo = 50-ohms CL = 50pF RTERM 100-ohms Notes: 1. Measurement of data output occurs at the low to high or high to low transition mid-point, typically, VDD/2. Figure 7. AC Output Test Load or Equivalent 36-00-01-000 Ver. 1.0.0 11 Aeroflex Microelectronic Solutions - HiRel Figure 8. 64-Pin Ceramic Flatpack 36-00-01-000 Ver. 1.0.0 12 Aeroflex Microelectronic Solutions - HiRel ORDERING INFORMATION 8M x 8 MRAM: UT ****** - * * * * * Lead Finish: (Note 1) (C) = Gold Screening: (Note 2,3) (E) = HiRel flow (Temperature range: -40°C to +105°C) (P) = Prototype flow (Temperature range: 25oC only) (T) = Prototype flow (Temperature range: -40°C to +105°C) Package Type: (X) = 64-lead Ceramic Flatpack (50mil lead pitch) Access Time: (50) = 50ns access time Device Type: (8MR8M8) = 8Mx8 MRAM Notes: 1. Lead finish is "C" (Gold) only. 2. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Radiation neither tested nor guaranteed. 3. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Radiation neither tested nor guaranteed. 36-00-01-000 Ver. 1.0.0 13 Aeroflex Microelectronic Solutions - HiRel 8M x 8 MRAM: SMD 5962 - ******* ** * * * Lead Finish: (Note 1) (C) = Gold Case Outline: (X) = 64-lead Ceramic Flatpack Class Designator: (Q) = QML Class Q (In development, contact factory) (V) = QML Class V (In development, contact factory) Device Type (Note 2) (01) = 50ns access time. Temperature Range (-40°C to +105°C) (02) = 50ns access time (-40°C to +105°C) manufactured to QML-Q+ flow (02TBD)=15ns access time, CMOS I/O, 40-lead flatpack package, dual chip enable (not available) Drawing Number: 13207 Total Dose: (R) = 100 krad(Si) (F) = 300 krad(Si) (G) = 500 krad(Si) (H) = 1 Mrad(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish is "C" (Gold) only. 2.Aeroflex’s Q+ flow, as defined in Section 4.2.2d of SMD, provides QML-Q product through the SMD that is manufactured with Aeroflex’s standard QML-V flow. 36-00-01-000 Ver. 1.0.0 14 Aeroflex Microelectronic Solutions - HiRel NOTES 36-00-01-000 Ver. 1.0.0 15 Aeroflex Microelectronic Solutions - HiRel Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Hi-Rel This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be required prior to the export of this product from the United States. www.aeroflex.com/HiRel [email protected] Aeroflex Colorado Springs (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 16 DATA SHEET REVISION HISTORY Revision Date March 2015 Ver 1.0.0 36-00-01-000 Ver. 1.0.0 Description of Change Initial Release of Datasheet 17 Aeroflex Microelectronic Solutions - HiRel