UT6325 RadTol Eclipse FPGA Product

Standard Products
UT6325 RadTol Eclipse FPGA
Data Sheeet
November 2013
www.aeroflex.com/FPGA
 Comprehensive design tools include high quality Verilog/
VHDL synthesis and simulation
 QuickLogic IP available for microcontrollers, DRAM
controllers, USART and PCI
 Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, 484
CLGA, 208 PQFP, 280 PBGA, and 484 PBGA
 Standard Microcircuit Drawing 5962-04229
- QML Q & V
FEATURES
TM
 0.25m, five-layer metal, ViaLink epitaxial CMOS
process for smallest die sizes
 One-time programmable, ViaLink technology for
personalization
 Typical performance characteristics -- 120 MHz 16-bit
counters, 120 MHz datapaths, 60+ MHz FIFOs
 2.5V core supply voltage, 3.3V I/O supply voltage
 Up to 320,000 system gates (non-volatile)
 I/Os
- Interfaces with 3.3 volt
- PCI compliant with 3.3 volt
- Full JTAG 1149.1 compliant
- Registered I/O cells with individually controlled enables
 Operational environment; total dose irradiation testing to
MIL-STD-883 Test Method 1019
- Total-dose: 300 krad(Si)
- SEL Immune: <120MeV-cm2/mg
INTRODUCTION
The UT6325 RadTol Eclipse Field Programmable Gate Array
Family (FPGA) offers up to 320,000 system gates including
Dual-Port RadTol SRAM modules. It is fabricated on 0.25m
five-layer metal ViaLink CMOS process and contains 1,536
logic cells and 24 dual-port SRAM modules (see Figure 1 Block
Diagram). Each SRAM module has 2,304 RAM bits, for a
maximum total of 55,300 bits. Please reference product family
features chart on page 2.
SRAM modules are Dual Port (one asynchronous/synchronous
read port, one write port) and can be configured into one of four
modes (see Figure 2). Designers can cascade multiple RAM
modules to increase the depth or width allowed in single
modules by connecting corresponding address lines together and
dividing the words between modules (see Figure 3). This
approach allows a variety of address depths and word widths to
be tailored to a specific application.
- LETTH (0.25) MeV-cm2/mg:
>42 logic cell flip flops
>64 for embedded SRAM
- Saturated Cross Section (cm2) per bit
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
 Up to 24 dual-port RadTol SRAM modules, organized in
user-configurable 2,304 bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and initialized RAM
functions
 100% routable with full logic cell utilization and 100% user
fixed I/O
 Variable-grain logic cells provide high performance and
100% utilization
 Typical logic utilization = 65-80% (design dependent)
The UT6325 RadTol Eclipse FPGA is available in a 208-pin
Cerquad Flatpack, allowing access to 99 bidirectional signal I/
O, 1 dedicated clock, 8 programmable clocks and 16 high drive
inputs. Other package options include a 288 CQFP, 484 CCGA
and a 484 CLGA.
Aeroflex uses QuickLogic Corporation’s licensed ESP
(Embedded Standard Products) technology. QuickLogic is a
pioneer in the FPGA semiconductor and software tools field.
1
UT6325 Product Features
Features
Device
System
Gates
Logic
Cells
UT6325
320,640
1,536
Maximum
Logic
Flip Flops Cell Flip
Flops
4,002
RAM
Modules
RAM
Bits
I/O Standards
Clocks
High
Drive
Inputs
24
55,300
LVTTL,
LVCMOS3, PCI
9
16
3072
Operational Environment
Device
Total Dose
LETTH (0.25) MeV-cm2/mg
Saturated Cross Section
UT6325
3E5
>42 logic cell flip flops
>64 embedded SRAM
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
Latch-up
Immune
>120
Bidirectional I/O per Package
Device
208 PQFP
208 CQFP
280PBGA
288 CQFP
484 PBGA
484 CLGA
484 CCGA
UT6325
99
99
163
163
310
316
316
2
Embedded RAM Blocks
Maximum
of
24
RadTol
SRAM
Blocks
Fabric
Embedded RAM Blocks
Bidirectional I//O and
High-Drive Inputs
Figure 1. UT6325 Eclipse FPGA Block Diagram
3
IP
Maximum
of
1,536
High
Speed
Variable
Grain
Logic
Cells
PRODUCT DESCRIPTION
I/O Pins
(9:0)
(17:0)
WA
WD
RCLK
RA
WE
RD
WCLK
(1:0)
MODE
• Up to 316 bi-directional input/output pins, PCI-compliant for
3.3V buses (see Table 4)
RE
• Each bidirectional I/O contains RadTol flip-flops for input,
output, and output enable lines
(9:0)
Distributed Networks
(17:0)
• One, dedicated clock network, hardwired to each logic cell
flip-flop clock pin to minimize skew
ASYNCRD
• Three programmable, global clock networks accessible from
clock input only pins
Figure 2. UT6325 Eclipse FPGA RAM Module
• Five programmable quadrant clock networks, accessible from
clock pins or internal logic
Software support for the product is available from both
Aeroflex and QuickLogic. The Windows PC-based QuickWorksTM package provides the most complete software solution from design entry to logic synthesis, place and route,
simulation, static timing, and power analysis. Device libraries
are available to provide support for designers who use Mentor,
Synplicity, Synopsys or other third party tools for design entry,
synthesis and simulation. Please visit QuickLogic’s website at
www.quicklogic.com for more information.
• 20 pre-defined Quad-clock networds, five per quadrant. Accessed by the five programmable quadrant clock networks
• Sixteen high drive inputs. Two inputs located in each of the
eight I/O banks. Used as clock or enable signals for the I/O
RadTol flip-flops, or as high drive inputs for internal logic
Typical Performance
The variable grain logic cell features up to 17 simultaneous inputs and 6 outputs within a cell that can be fragmented into 6
independent sections. Each cell has a fan-in of 30 including
register and control lines (see Figure 5).
• Input + logic cell + output total delays under 12ns
• Data path speeds over 120 MHz
• Counter speeds over 120 MHz
WDATA
RAM
Module
(2,304 bits)
WADDR
• FIFO speeds over 60+ MHz
RDATA
RADDR
RAM
Module
(2,304 bits)
WDATA
RDATA
Figure 3. UT6325 Eclipse FPGA Module Bits
4
+
-
INPUT
REGISTER
Q
E
D
R
PAD
Q
OUTPUT
REGISTER
D
R
E
OUTPUT
ENABLE
REGISTER
Q
D
R
Figure 4. RadTol Eclipse FPGA I/O Cell
5
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
MS
AZ
OZ
S
D Q
QZ
R
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
S
D Q
R
PS
PP
QC
DCLK
CLKSEL
QR
GRST
Figure 5. RadTol Eclipse FPGA Logic Cell
6
NZ
Q2Z
FZ
Table 1: 208-pin Ceramic Quad Flatpack Pinout Table
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
1
PLLRST(3)
36
IO(B)
71
IO(C)
106
VCCPLL(1)
141
IO(F)
176
IO(G)
2
VCCPLL(3)
37
IO(B)
72
VCCIO(C)
107
IO(E)
142
IO(F)
177
VCCIO(G)
3
GND
38
IO(B)
73
IO(C)
108
GND
143
IO(F)
178
GND
4
GND
39
IOCTRL(B)
74
IO(C)
109
IO(E)
144
IOCTRL(F)
179
IO(G)
5
IO(A)
40
INREF(B)
75
GND
110
IO(E)
145
INREF(F)
180
IO(G)
6
IO(A)
41
IOCTRL(B)
76
VCC
111
VCCIO(E)
146
VCC
181
IO(G)
7
IO(A)
42
IO(B)
77
IO(C)
112
IO(E)
147
IOCTRL(F)
182
VCC
8
VCCIO(A)
43
IO(B)
78
TRSTB
113
VCC
148
IO(F)
183
TCK
9
IO(A)
44
VCCIO(B)
79
VCC
114
IO(E)
149
IO(F)
184
VCC
10
IO(A)
45
IO(B)
80
IO(D)
115
IO(E)
150
VCCIO(F)
185
IO(H)
11
IOCTRL(A)
46
VCC
81
IO(D)
116
IO(E)
151
IO(F)
186
IO(H)
12
VCC
47
IO(B)
82
IO(D)
117
IOCTRL(E)
152
IO(F)
187
IO(H)
13
INREF(A)
48
IO(B)
83
GND
118
INREF(E)
153
GND
188
GND
14
IOCTRL(A)
49
GND
84
VCCIO(D)
119
IOCTRL(E)
154
IO(F)
189
VCCIO(H)
15
IO(A)
50
TDO
85
IO(D)
120
IO(E)
155
PLLOUT(3)
190
IO(H)
16
IO(A)
51
PLLOUT(1)
86
VCC
121
IO(E)
156
GNDPLL(0)
191
IO(H)
17
IO(A)
52
GNDPLL(2)
87
IO(D)
122
VCCIO(E)
157
GND
192
IOCTRL(H)
18
IO(A)
53
GND
88
IO(D)
123
GND
158
VCCPLL(0)
193
IO(H)
19
VCCIO(A)
54
VCCPLL(2)
89
VCC
124
IO(E)
159
PLLRST(0)
194
INREF(H)
20
IO(A)
55
PLLRST(2)
90
IO(D)
125
IO(E)
160
GND
195
VCC
21
GND
56
VCC
91
IO(D)
126
IO(E)
161
IO(G)
196
IOCTRL(H)
22
IO(A)
57
IO(C)
92
IOCTRL(D)
127
162
VCCIO(G)
197
IO(H)
23
TDI
58
GND
93
INREF(D)
128
CLK(5)
PLLIN(3)
CLK(6)
163
IO(G)
198
IO(H)
24
CLK(0)
59
IO(C)
94
IOCTRL(D)
129
VCC
164
IO(G)
199
IO(H)
25
CLK(1)
60
VCCIO(C)
95
IO(D)
130
CLK(7)
165
VCC
200
IO(H)
26
VCC
61
IO(C)
96
IO(D)
131
VCC
166
IO(G)
201
IO(H)
27
CLK(2)
PLLIN(2)
62
IO(C)
97
IO(D)
132
CLK(8)
167
IO(G)
202
IO(H)
28
CLK(3)
PLLIN(1)
63
IO(C)
98
VCCIO(D)
133
TMS
168
IO(G)
203
VCCIO(H)
29
VCC
64
IO(C)
99
IO(D)
134
IO(F)
169
IOCTRL(G)
204
GND
30
CLK(4),
DEDCLK
PLLIN(0)
65
IO(C)
100
IO(D)
135
IO(F)
170
INREF(G)
205
IO(H)
31
IO(B)
66
IO(C)
101
GND
136
IO(F)
171
IOCTRL(G)
206
PLLOUT(2)
32
IO(B)
67
IOCTRL(C)
102
PLLOUT(0)
137
GND
172
IO(G)
207
GND
33
GND
68
INREF(C)
103
GND
138
VCCIO(F)
173
IO(G)
208
GNDPLL(3)
34
VCCIO(B)
69
IOCTRL(C)
104
GNDPLL(1)
139
IO(F)
174
IO(G)
35
IO(B)
70
IO(C)
105
PLLRST(1)
140
IO(F)
175
VCC
7
Table 2: 288-pin Ceramic Quad Flatpack Pinout Table
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
1
GND
36
CLK(7)
71
VCC
106
IO(G)
141
PLLRST(3)
176
IO(A)
2
VCC
37
CLK(8)
72
GND
107
TCK
142
VCCPLL(3)
177
TDI
3
PLLRST(1)
38
TMS
73
GND
108
VCC
143
VCC
178
CLK(0)
4
VCCPLL(1)
39
IO(F)
74
VCC
109
IO(H)
144
GND
179
CLK(1)
5
IO(E)
40
IO(F)
75
GND
110
IO(H)
145
GND
180
6
IO(E)
41
IO(F)
76
PLLRST(0)
111
IO(H)
146
VCC
181
7
IO(E)
42
IO(F)
77
IO(F)
112
IO(H)
147
GND
182
8
IO(E)
43
VCC
78
IO(F)
113
IO(H)
148
IO(A)
183
CLK(2)
PLLIN(2)
CLK(3)
PLLIN(1)
CLK(4),
DEDCIK,
PLLIN(0)
IO(B)
9
IO(E)
44
GND
79
IO(F)
114
IO(H)
149
IO(A)
184
IO(B)
10
IO(E)
45
VCCIO(F)
80
IO(G)
115
VCC
150
IO(A)
185
IO(B)
11
IO(E)
46
IO(F)
81
IO(G)
116
GND
151
IO(A)
186
IO(B)
12
IO(E)
47
IO(F)
82
IO(G)
117
VCCIO(H)
152
IO(A)
187
VCC
13
IO(E)
48
IO(F)
83
IO(G)
118
IO(H)
153
IO(A)
188
GND
14
VCC
49
IO(F)
84
IO(G)
119
IO(H)
154
IO(A)
189
VCCIO(B)
15
GND
50
IO(F)
85
IO(G)
120
IO(H)
155
IO(A)
190
IO(B)
16
VCCIO(E)
51
IO(F)
86
VCC
121
IOCTRL(H)
156
IOCTRL(A)
191
IO(B)
17
IOCTRL(E)
52
INREF(F)
87
GND
122
IO(H)
157
INREF(A)
192
IO(B)
18
INREF(E)
53
IOCTRL(F)
88
VCCIO(G)
123
INREF(H)
158
VCC
193
IO(B)
19
IOCTRL(E)
54
IOCTRL(F)
89
IO(G)
124
IOCTRL(H)
159
GND
194
IO(B)
20
IO(E)
55
IO(F)
90
IOCTRL(G)
125
IO(H)
160
VCCIO(A)
195
IOCTRL(B)
21
IO(E)
56
IO(F)
91
INREF(G)
126
IO(H)
161
IOCTRL(A)
196
INREF(B)
22
IO(E)
57
VCCIO(F)
92
IOCTRL(G)
127
IO(H)
162
IO(A)
197
IOCTRL(B)
23
IO(E)
58
GND
93
IO(G)
128
IO(H)
163
IO(A)
198
IO(B)
24
IO(E)
59
VCC
94
IO(G)
129
VCCIO(H)
164
IO(A)
199
IO(B)
25
IO(E)
60
IO(F)
95
IO(G)
130
GND
165
IO(A)
200
IO(B)
26
IO(E)
61
IO(F)
96
IO(G)
131
VCC
166
IO(A)
201
VCCIO(B)
27
IO(E)
62
IO(F)
97
IO(G)
132
IO(H)
167
IO(A)
202
GND
28
VCCIO(E)
63
IO(F)
98
IO(G)
133
IO(H)
168
IO(A)
203
VCC
29
GND
64
IO(F)
99
IO(G)
134
IO(H)
169
IO(A)
204
IO(B)
30
VCC
65
IO(F)
100
VCCIO(G)
135
IO(A)
170
IO(A)
205
IO(B)
31
IO(E)
66
IO(F)
101
GND
136
IO(A)
171
IO(A)
206
IO(B)
32
IO(E)
67
IO(F)
102
VCC
137
IO(A)
172
VCCIO(A)
207
IO(B)
33
IO(E)
68
PLLOUT(3)
103
IO(G)
138
PLLOUT(2)
173
GND
208
IO(B)
34
CLK(5)
PLLIN(3)
69
GNDPLL(0)
104
IO(G)
139
GND
174
VCC
209
IO(B)
35
CLK(6)
70
VCCPLL(0)
105
IO(G)
140
GNDPLL(3)
175
IO(A)
210
IO(B)
8
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
211
TDO
224
IO(B)
237
IOCTRL(C)
250
IO(C)
263
IO(D)
276
IO(D)
212
PLLOUT(1)
225
IO(C)
238
INREF(C)
251
IO(C)
264
IO(D)
277
IO(D)
213
GNDPLL(2)
226
IO(C)
239
IOCTRL(C)
252
TRSTB
265
IO(D)
278
IO(D)
214
IO(B)
227
IO(C)
240
IO(C)
253
VCC
266
IO(D)
279
IO(D)
215
VCC
228
IO(C)
241
IO(C)
254
IO(D)
267
IO(D)
280
IO(D)
216
GND
229
IO(C)
242
IO(C)
255
IO(D)
268
IO(D)
281
IO(E)
217
GND
230
VCC
243
IO(C)
256
IO(D)
269
IO(D)
282
IO(E)
218
VCC
231
GND
244
VCCIO(C)
257
IO(D)
270
IOCTRL(D)
283
IO(E)
219
GND
232
VCCIO(C)
245
GND
258
IO(D)
271
INREF(D)
284
PLLOUT(0)
220
VCCPLL(2)
233
IO(C)
246
VCC
259
VCC
272
IOCTRL(D)
285
GND
221
PLLRST(2)
234
IO(C)
247
IO(C)
260
GND
273
VCCIO(D)
286
GNDPLL(1)
222
IO(B)
235
IO(C)
248
IO(C)
261
VCCIO(D)
274
GND
287
VCC
223
IO(B)
236
IO(C)
249
IO(C)
262
IO(D)
275
VCC
288
GND
9
Table 3: 484-pin Ceramic Land Grid Array and Plastic Ball Grid Array Pinout Table
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
A1
IO(A)
AA14
IO(D)
B5
IO(A)
C18
IO(G)
E9
IO(H)
F22
IOCTRL(F)
A2
PLLRST(3)
AA15
IO(D)
B6
IO(H)
C19
IO(F)
E10
IO(H)
G1
IO(A)
A3
IO(A)
AA16
IO(D)
B7
IO(H)
C20
GNDPLL(0)
E11
VCC
G2
IO(A)
A4
IO(A)
AA17
IO(D)
B8
INREF(H)
C21
IO(F)
E12
IO(G)
G3
IO(A)
A5
IO(A)
AA18
IO(D)
B9
IO(H)
C22
IO(F)
E13
IO(G)
G4
IO(A)
A6
IO(H)
AA19
IO(E)
B10
IO(H)
D1
IO(A)
E14
IO(G)
G5
IO(A)
A7
IO(H)
AA20
GNDPLL(1)
B11
IO(H)
D2
IO(A)
E15
IOCTRL(G)
G6
IO(A)
A8
IOCTRL(H)
AA21
IO(E)
B12
NC
D3
IO(A)
E16
IO(G)
G7
GND
A9
IO(H)
AA22
IO(E)
B13
NC
D4
IO(A)
E17
INREF(G)
G8
IO(H)
A10
NC
AB1
IO(B)
B14
NC
D5
IO(A)
E18
IO(G)
G9
IO(H)
A11
IO(H)
AB2
GNDPLL(2)
B15
IO(G)
D6
IO(H)
E19
IO(F)
G10
IO(H)
A12
TCK
AB3
PLLRST(2)
B16
IO(G)
D7
IO(H)
E20
IO(F)
G11
IO(G)
A13
IO(G)
AB4
IO(B)
B17
IO(G)
D8
IO(H)
E21
IO(F)
G12
GND
A14
IO(G)
AB5
IO(B)
B18
IO(G)
D9
IO(H)
E22
IO(F)
G13
IO(G)
A15
IO(G)
AB6
IO(C)
B19
PLLRST(0)
D10
IO(H)
F1
IO(A)
G14
IO(G)
A16
IO(G)
AB7
IO(C)
B20
IO(F)
D11
IO(H)
F2
INREF(A)
G15
IO(G)
A17
IO(G)
AB8
IOCTRL(C)
B21
IO(F)
D12
IO(G)
F3
IO(A)
G16
GND
A18
IO(G)
AB9
IO(C)
B22
IO(F)
D13
IO(G)
F4
IO(A)
G17
VCCIO(F)
A19
IO(F)
AB10
IO(C)
C1
IO(A)
D14
IO(G)
F5
IO(A)
G18
IO(F)
A20
GND
AB11
IO(C)
C2
IO(A)
D15
IOCTRL(G)
F6
VCCIO(A)
G19
IO(F)
A21
PLLOUT(3)
AB12
IO(D)
C3
VCCPLL(3)
D16
IO(G)
F7
VCCIO(H)
G20
IO(F)
A22
IO(F)
AB13
IO(D)
C4
PLLOUT(2)
D17
IO(G)
F8
IO(H)
G21
INREF(F)
AA1
TDO
AB14
IO(D)
C5
IO(A)
D18
IO(F)
F9
VCCIO(H)
G22
IO(F)
AA2
PLLOUT(1)
AB15
IO(D)
C6
IO(H)
D19
VCCPLL(0)
F10
IO(H)
H1
IO(A)
AA3
GND
AB16
IOCTRL(D)
C7
IO(H)
D20
IO(F)
F11
VCCIO(H)
H2
IO(A)
AA4
IO(B)
AB17
IO(D)
C8
IO(H)
D21
IO(F)
F12
VCCIO(G)
H3
IO(A)
AA5
IO(C)
AB18
IO(D)
C9
IOCTRL(H)
D22
IO(F)
F13
IO(G)
H4
IO(A)
AA6
IO(C)
AB19
IO(E)
C10
IO(H)
E1
IOCTRL(A)
F14
VCCIO(G)
H5
IOCTRL(A)
AA7
IO(C)
AB20
GND
C11
IO(H)
E2
IO(A)
F15
NC
H6
VCCIO(A)
AA8
INREF(C)
AB21
VCCPLL(1)
C12
IO(H)
E3
IO(A)
F16
VCCIO(G)
H7
IO(H)
AA9
IO(C)
AB22
IO(E)
C13
IO(G)
E4
IO(A)
F17
IO(F)
H8
GND
AA10
IO(C)
B1
IO(A)
C14
IO(G)
E5
IO(A)
F18
IO(F)
H9
VCC
AA11
IO(C)
B2
GND
C15
IO(G)
E6
IO(H)
F19
IO(F)
H10
VCC
AA12
IO(D)
B3
GNDPLL(3)
C16
IO(G)
E7
IO(A)
F20
IOCTRL(F)
H11
VCC
AA13
IO(D)
B4
GND
C17
IO(G)
E8
IO(H)
F21
IO(F)
H12
GND
10
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
H13
VCC
K4
IO(A)
L17
VCCIO(F)
N8
VCC
P21
IO(E)
T12
IO(C)
H14
VCC
K5
IO(A)
L18
IO(F)
N9
VCC
P22
IO(E)
T13
IO(D)
H15
GND
K6
VCCIO(A)
L19
CLK(8)
N10
GND
R1
IO(B)
T14
IO(E)
H16
IO(F)
K7
IO(A)
L20
IO(F)
N11
GND
R2
INREF(B)
T15
IO(D)
H17
IO(F)
K8
VCC
L21
IO(F)
N12
GND
R3
IO(B)
T16
GND
H18
IO(F)
K9
VCC
L22
IO(F)
N13
GND
R4
IO(B)
T17
IO(E)
H19
IO(F)
K10
GND
M1
IO(B)
N14
VCC
R5
IO(B)
T18
IO(E)
H20
IO(F)
K11
GND
M2
IO(B)
N15
VCC
R6
IO(B)
T19
IO(E)
H21
IO(F)
K12
GND
M3
IO(B)
N16
IO(E)
R7
IO(B)
T20
IO(E)
H22
IO(F)
K13
GND
M4
N17
VCCIO(E)
R8
GND
T21
IOCTRL(E)
J1
IO(A)
K14
VCC
M5
CLK(3)
PLLIN(1)
IO(B)
N18
IO(E)
R9
VCC
T22
IO(E)
J2
IO(A)
K15
VCC
M6
VCCIO(B)
N19
IO(E)
R10
VCC
U1
IOCTRL(B)
J3
IO(A)
K16
IO(F)
M7
CLK(1)
N20
IO(E)
R11
GND
U2
IO(B)
J4
IO(A)
K17
IO(F)
M8
VCC
N21
IO(E)
R12
VCC
U3
IOCTRL(B)
J5
IO(A)
K18
IO(F)
M9
VCC
N22
IO(E)
R13
VCC
U4
IO(B)
J6
IO(A)
K19
IO(F)
M10
GND
P1
IO(B)
R14
VCC
U5
IO(B)
J7
IO(A)
K20
IO(F)
M11
GND
P2
IO(B)
R15
GND
U6
IO(C)
J8
VCC
K21
IO(F)
M12
GND
P3
IO(B)
R16
IO(D)
U7
VCCIO(C)
J9
GND
K22
IO(F)
M13
GND
P4
IO(B)
R17
VCCIO(E)
U8
NC
J10
VCC
L1
CLK4,
DEDCLK
PLLIN(0)
M14
GND
P5
IO(B)
R18
IO(E)
U9
VCCIO(C)
J11
VCC
L2
CLK(0)
M15
GND
P6
VCCIO(B)
R19
IO(E)
U10
IO(C)
J12
GND
L3
CLK(2)
PLLIN(2)
M16
GND
P7
IO(B)
R20
IO(E)
U11
VCCIO(C)
J13
VCC
L4
IO(A)
M17
IO(E)
P8
VCC
R21
IO(E)
U12
VCCIO(D)
J14
GND
L5
IO(A)
M18
IO(E)
P9
GND
R22
IO(E)
U13
IO(D)
J15
VCC
L6
IO(A)
M19
IO(E)
P10
VCC
T1
IO(B)
U14
VCCIO(D)
J16
IO(F)
L7
GND
M20
CLK(7)
P11
GND
T2
IO(B)
U15
NC
J17
VCCIO(F)
L8
GND
M21
P12
VCC
T3
IO(B)
U16
VCCIO(D)
J18
IO(F)
L9
GND
M22
CLK(5)
PLLIN(3)
TMS
P13
VCC
T4
IO(B)
U17
VCCIO(E)
J19
IO(F)
L10
GND
N1
IO(B)
P14
GND
T5
IO(B)
U18
IO(E)
J20
IO(F)
L11
GND
N2
IO(B)
P15
VCC
T6
VCCIO(B)
U19
IO(E)
J21
IO(F)
L12
GND
N3
IO(B)
P16
IO(E)
T7
GND
U20
IOCTRL(E)
J22
IO(F)
L13
GND
N4
IO(B)
P17
IO(E)
T8
IO(C)
U21
IO(E)
K1
TDI
L14
VCC
N5
IO(B)
P18
IO(E)
T9
IO(B)
U22
INREF(E)
K2
IO(A)
L15
VCC
N6
IO(B)
P19
IO(E)
T10
TRSTB
V1
IO(B)
K3
IO(A)
L16
CLK(6)
N7
IO(B)
P20
IO(E)
T11
GND
V2
IO(B)
11
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
V3
IO(B)
V14
IO(D)
W3
IO(B)
W14
IO(D)
Y3
VCCPLL(2)
Y14
IO(D)
V4
IO(B)
V15
IO(D)
W4
IO(B)
W15
IO(D)
Y4
IO(C)
Y15
IOCTRL(D)
V5
IO(B)
V16
INREF(D)
W5
IO(B)
W16
NC
Y5
IO(C)
Y16
IO(D)
V6
IO(C)
V17
IO(D)
W6
IO(C)
W17
IO(D)
Y6
IO(C)
Y17
IO(D)
V7
IO(C)
V18
IO(E)
W7
NC
W18
IO(E)
Y7
IO(C)
Y18
IO(E)
V8
IO(C)
V19
IO(E)
W8
IO(C)
W19
IO(E)
Y8
IOCTRL(C)
Y19
PLLOUT(0)
V9
NC
V20
IO(E)
W9
IO(C)
W20
IO(E)
Y9
IO(C)
Y20
PLLRST(1)
V10
IO(C)
V21
IO(E)
W10
IO(C)
W21
IO(E)
Y10
IO(C)
Y21
ID(E)
V11
IO(C)
V22
IO(E)
W11
IO(C)
W22
IO(E)
Y11
IO(D)
Y22
IO(E)
V12
VCC
W1
IO(B)
W12
IO(D)
Y1
IO(B)
Y12
IO(D)
V13
NC
W2
IO(B)
W13
IO(D)
Y2
IO(B)
Y13
IO(D)
12
Table 4: UT6325 Eclipse FPGA Pin Description
PIN
FUNCTION
DESCRIPTION
TDI/RSI
Test data in for JTAG/RAM
initialization Serial Data In
Hold HIGH during normal operation. Connects to serial PROM
data in for RAM initialization. Connect to VCC if unused.
TRSTB/RRO
Active low reset for JTAG/
RAM initialization reset out
Hold LOW during normal operation. Connects to serial PROM
reset for RAM initialization. Connect to GND if unused.
TMS
Test mode select for JTAG
Hold HIGH during normal operation. Connect to VCC if not
used for JTAG.
TCK
Test clock for JTAG
Hold HIGH or LOW during normal operation. Connect to VCC
or ground if not used for JTAG.
TDO/RCO
Test data out for JTAG/RAM
initialization clock out
Connect to serial PROM clock for RAM initialization. Must be
left unconnected if not used for JTAG or RAM initialization.
CLK1
Global clock network driver
Low skew global clock. This pin provides access to a
programmable clock network.
IO(A)
Input/Output Pin
The I/O pin is a bi-directional pin, configurable to input and/or
output. The A inside the parenthesis means that the I/O is
located in Bank A.
DEDCLK1
Dedicated clock pin
Low skew global clock. This pin provides access to a dedicated,
distributed clock network capable of driving the CLOCK inputs
of sequential elements of the device (e.g., RAM and flip-flops).
PLLIN1
PLL clock input
Clock input for PLL.
VCCPLL1
Phase locked loop power
supply pin
Voltage supply for PLLIN. VCCPLL should be connected to
2.5V supply if the PLLs are used. If the PLLs are not used,
VCCPLL can be connected GND.
GNDPLL
Ground pin for PLL
Connect to GND.
PLLRST1
Reset input pin for PLL
Reset input for PLL. If PLLs are not used, PLLRST should be
connect to the same voltage as VCCPLL (e.g., GND).
PLLOUT2
PLL output pin
Dedicated PLL output pin. If PLLs are not used, PLLOUT
should be connected to GND.
INREF(A)
Differential reference voltage The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. The A inside the parenthesis means that
INREF is located in Bank A. This pin should be tied to GND
for LVTTL, LVCMOS3 and PCI inputs.
IOCTRL(A)1
Highdrive input
This pin provides fast RESET, SET, CLOCK and ENABLE
access to the I/O cell flip flops, providing fast clock-to-out and
fast I/O response times. This pin can also double as a high-drive
pin to the internal logic cells. The A inside the parenthesis
means that IOCTRL is located in Bank A.
VCC
Power supply pin
Connect to 2.5V supply.
13
Table 4: UT6325 Eclipse FPGA Pin Description
PIN
FUNCTION
DESCRIPTION
VCCIO(A)
Input voltage tolerance pin
Connect to 3.3V supply. The A inside the parenthesis means
that VCCIN is located in Bank A. Every I/O pin in Bank A will
be tolerance of VCCIO input signals and will output VCCIO level
signals.
GND
Ground pin
Connect to ground.
Note: Four PLL inputs are available on the RadTol Eclipse FPGA. These PLL pins are noted and available in the QuickWorks/SpDE place and route tools. Aeroflex
has tested and characterized the PLL circuits for jitter performance vs frequency and SEE. Aeroflex cautions against the use of the PLL circuits without a full review
of the test results. Please contact Aeroflex Colorado Springs directly for support.
1. All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are LVCMOS2 compliant (2.5V). Modifications to the ESD protection
networks allow these pins to be driven up to VCCIO +0.3V. Slightly lower noise margins exist for these LVCMOS2 compliant inputs, as compared to the LVCMOS3
compliant bidirectional I/O.
2. All PLLOUT output pins are driven by the VCC rail, not the VCCIO rail. These output pins are LVCMOS2 compliant only (2.5V).
14
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VCC
Core supply voltage
-0.5 to 3.6V
VCCIO
I/O supply voltage
-0.5 to 4.6V
VIO
Voltage on any pin
-0.5V to VCCIO +0.5V
ILU
Electrical Latchup Immunity
+/-100mA
PD
Power Dissipation
.5 - 2.5W
JC
Thermal resistance, junction-to-case2 for
208 CQFP, 288 CQFP, 484 CLGA/CCGA
6oC/W
Thermal resistance, junction-to-case2 for
208 PQFP, 280 PBGA, 484 PBGA
8oC/W
Maximum junction temperature2
TJ
+150C
ESDS
ESD pad protection
+/-2000V
II
DC input current
±10 mA
TLS
Lead Temperature
300C
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Test per MIL-STD-883; Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VCC
Core supply voltage
2.3 to 2.7V
VCCIO
I/O Input Tolerance Voltage
3.0 to 3.6V
TA
Ambient Temperature
-55C to +125C
K1
Delay factor for FPGA
0.42 to 1.92
(speed grade -4)
tINRISE
tINFALL
Maximum input rise or fall time
(VIN transitioning between VIL (max) and VIH (min))
20ns
Notes:
1. To conclude best and worst case delays, multiply the K factor from the operating conditions with the delay values defined in the following AC delay tables.
15
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-55C to +125C) (2.3V < VCC < 2.7V)
SYMBOL
PARAMETER
IIN1
Input or I/O leakage current, all I/O
except TRSTB, TDI, TMS
IIN2
MIN
MAX
UNIT
VIN = VCCIO or Gnd
-2
2
A
Input leakage current TRSTB, TDI,
TMS
VIN = VCCIO or Gnd
-20
5
A
IIN2
Input leakage current TRSTB, TDI,
TMS post 300 krads(Si)
VIN = VCCIO or Gnd
-50
50
A
IOZ
Three-state output leakage current
VIN= VCCIO or Gnd
-10
10
A
CI1
Input capacitance
--
-
8
pF
CI/O1
Bi-directional capacitance
--
-
12
pF
IOS2
Short-circuit output current
VO = GND
VO = VCCIO
-15
40
-180
210
mA
mA
ICC3
Core quiescent current
VCC = 2.7V
15
mA
ICC3
Core quiescent current
VCC = 2.7V, post 100 krads(Si)
5
mA
ICC3
Core quiescent current
VCC = 2.7V, post 300 krads(Si)
400
mA
ICCIO3
I/O quiescent current
VCCIO = 3.6V
50
A
ICCIO3
I/O quiescent current
VCCIO = 3.6V, post 100 krads(Si)
0.5
mA
ICCIO3
I/O quiescent current
VCCIO = 3.6V, post 300 krads(Si)
5
mA
-10
10
A
-
150
A
IREF
DC supply current on INREF
IPD
Pad Pull-down (programmable)
CONDITION
VCCIO = 3.6V
Notes:
* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Capacitance is sample tested for initial qualification or design changes only. Clock pins are 12pF maximum.
2. Input only or I/O. Duration should not exceed 1 second. Measured at initial qualification, or after any design or process change that may affect this parameter.
3. All quiescent current measurements utilize a worst case Standard Evaluation Circuit (SEC) which represents full utilization of synchronous, combinatorial and
SRAM logic.
16
Table 5: DC Input and Output Levels1
VIL
INREF
VIH
VOL
VOH
IOL
IOH
VMIN
VMAX
VMIN
VMAX
VMIN
VMAX
VMAX
VMIN
mA
mA
LVTTL
n/a
n/a
-0.3
0.8
2.0
VCCIO + 0.3
0.4
2.4
2.0
-2.0
LVCMOS2
n/a
n/a
-0.3
0.7
1.7
VCCIO + 0.3
0.7
1.7
2.0
-2.0
LVCMOS3
n/a
n/a
-0.3
0.8
2.0
VCCIO + 0.3
.55
2.0
24.0
-24.0
LVCMOS32
n/a
n/a
-0.3
0.8
2.0
VCCIO + 0.3
0.20
VCCIO -0.2
0.10
-0.10
PCI
n/a
n/a
-0.3
0.3 x VCCIO
0.5 x VCCIO
VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO
1.5
-0.5
Notes:
1. The data provided in Table 5 are JEDEC and PCI specifications. See preceding AC Delay Data for information specific to Eclipse FPGA I/Os.
2. Low current mode for LVCMOS3 outputs.
Table 6: Max Bidirectional I/O per Device/Package Combination
Device
208 CQFP
288 CQFP
484 CLGA/484 CCGA
UT6325 Eclipse FPGA
99
163
316
Notes:
1. Excludes input only signals such as DEDCLK. PROGCLK and IOCTRL.
17
AC CHARACTERISTICS LOGIC CELLS (Pre/Post-Radiation)*
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
Min
Max
TPD
Combinatorial Delay of the longest path: time taken by the
combinatorial circuit to output
0.205
1.01
TSU
Setup Time: time the synchronous input of the flip flop must be
stable before the active clock edge
0.231
--
THL
Hold Time: time the synchronous input of the flip flop must be stable
after the active clock edge
0
--
TCO
Clock to Out Delay: the amount of time taken by the flip flop to
output after the active clock edge
-
0.43
TCWHI
Clock High Time: required minimum time the clock stays high
0.46
--
TCWLO
Clock Low Time: required minimum that the clock stays low
0.46
--
TSET
Set Delay: time between when the flip flop is "set" (high) and when
the output is consequently "set" (high)
--
0.59
TRESET
Reset Delay: time between when the flip flop is "reset" (low) and
when the output is consequently "reset" (low)
--
0.66
TSW
Set Width: time that the SET signal remains high/low
0.3
--
TRW
Reset Width: time that the RESET signal remains high/low
0.3
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Stated timing for typical case propagation delay over process variation at VCC=2.5V and TA=25oC. Multiply by the appropriate delay factor, K, for voltage and
temperature settings as specified in operating range.
2. These limits are derived from a representative selection of the slowest paths through the logic cell including typical net delays. Worst case delay values for specific
paths should be determined from timing analysis of your particular design.
18
SET
D
Q
CLK
RESET
Figure 6: Logic Cell Flip Flop
CLK
tCWHI (MIN)
tCWLO (MIN)
SET
RESET
Q
tRESET
tSET
tRW
tSW
Figure 7: Logic Cell Flip Flop Timings - First Waveform
CLK
D
tSU
tHL
D
tCO
Figure 8: Logic Cell Flip Flop Timings - Second Waveform
19
Quad Net
Figure 9: Global Clock Structure
GLOBAL CLOCK TREE DELAY
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
Min
Max
tPGCK
Global clock pin delay to quad net
0.990
1.386
tBGCK
Global clock buffer delay (quad net to flip flop)
0.534
1.865
Programmable Clock
Global Clock Buffer
External Clock
Global Clock
Clock
Select
tPGCK
tBGCK
Figure 10: Global Clock Structure Schematic
20
RAM CELL SYNCHRONOUS and ASYNCHRONOUS READ TIMING
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
RAM Cell Synchronous Read Timing
Min
Max
tSRA
RA setup time to RCLK: time the READ ADDRESS must be stable
before the active edge of the READ CLOCK
0.686
--
tHRA
RA hold time to RCLK: time the READ ADDRESS must be stable
after the active edge of the READ CLOCK
0
--
tSRE
RE setup time to RCLK: time the READ ENABLE must be stable
before the active edge of the READ CLOCK
0.243
--
tHRE
RE hold time to RCLK: time the READ ENABLE must be stable
after the active edge of the READ CLOCK
0
--
tRCRD
RCLK to RD: time between the active READ CLOCK edge and
the time when the data is delivered to RD
--
2.3
--
2.4
RAM Cell Asynchronous Read Timing
tPDRD
RA to RD: time between when the READ ADDRESS is input and
when the DATA is output
RCLK
RA
tSRA
tHRA
tSRE
tHRE
RE
RD
old data
new data
tRCRD
tPDRD
Figure 11: RAM Cell Synchronous and Asynchronous Read Timing
21
RAM CELL SYNCHRONOUS WRITE TIMING
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
Min
Max
tSWA
WA setup time to WCLK: time the WRITE ADDRESS must be
stable before the active edge of the WRITE CLOCK
0.675
--
tHWA
WA hold time to WCLK: time the WRITE ADDRESS must be
stable after the active edge of the WRITE CLOCK
0
--
tSWD
WD setup time to WCLK: time the WRITE DATA must be stable
before the active edge of the WRITE CLOCK
0.654
--
tHWD
WD hold time to WCLK: time the WRITE DATA must be stable
after the active edge of the WRITE CLOCK
0
--
tSWE
WE setup time to WCLK: time the WRITE ENABLE must be stable
before the active edge of the WRITE CLOCK
0.276
tHWE
WE hold time to WCLK: time the WRITE ENABLE must be stable
after the active edge of the WRITE CLOCK
0
tWCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK
edge and the time when the data is available at RD
--
2.8
WCLK
WA
tSWA
tHWA
tSWD
tHWD
tSWE
tHWE
WD
WE
RD
old data
new data
tWCRD
Figure 12: RAM Cell Synchronous Write Timing
22
tICLK
tIN - tINI
tISU
+
-
tSID
Q
E
D
R
PAD
Figure 13. Input Register Cell
23
INPUT REGISTER CELL
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
Min
Max
tISU
Input register setup time: time the synchronous input of the pin must
be stable before the active clock edge
3.308
3.526
tIHL
Input register hold time: time the synchronous input of the flip-flop
must be stable after the active clock edge
0
--
tICO
Input register clock to out: time taken by the flip-flop to output after
the active clock edge
--
0.494
tIRST
Input register reset delay: time between when the flip-flop is "reset"
(low) and when the output is consequently "reset" (low)
--
0.464
tIESU
Input register clock enable setup time: time "enable" must be stable
before the active clock edge
0.830
-
tIEH
Input register clock enable hold time: time "enable" must be stable
after the active clock edge
0
--
STANDARD INPUT DELAYS
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
Min
tSID (LVTTL)
tSID (LVCMOS3)
LVTTL input delay: Low voltage TTL for 3.3V applications
Max
-
0.34
LVCMOS3 input delay: Low voltage CMOS for 3.3V applications -
0.42
R
CLK
D
tISU
tIHL
tICO
Q
tIRST
E
tIESU
tIEH
Figure 14. Input Register Timing
24
PAD
Q
D
Figure 15. Output Register Cell
25
OUTPUT REGISTER CELL
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL
PARAMETER
Value (ns)
Min
tOUTLH
Output Delay low to high (90% of H)
-
2.59
tOUTHL
Output Delay high to low (10% of L)
-
2.16
tPZH
Output Delay tri-state to high (90% of H)
-
3.06
tPZL
Output Delay tri-state to low (10% of L)
--
2.71
tPHZ
Output Delay high to tri-state
--
3.44
tPLZ
Output Delay low to tri-state
--
3.32
tCOP
Clock to out delay (does not include clock tree delays)
--
2.67 (fast skew)
9.0 (slow skew)
OUTPUT SLEW RATES
(VCC = 2.5V, TA = 25oC, K=1.00, VCCIO = 3.3V)
Fast Slew
Slow Slew
Rising Edge
2.8V/ns
1.0V/ns
Falling Edge
2.86V/ns
1.0V/ns
tOUTHL
L
H
H
Z
Z
L
tPZH
Z
Z
tPZL
L
H
H
L
tOUTHL
H
H
L
Max
L
tPLZ
Figure 16. Output Register Cell Timing
26
tPHZ
Power vs Operating Frequency
The basic power equation which best models power consumption is shown below.
PTOTAL = 0.350 + f(0.0031 NLC + 0.0948 NCKBF +0.01 NCLBF + 0.0263 NCKLD + 0.543 NRAM + 0.0035 NINP + 0.0257
NOUTP) (mW)
Where
• NLC is the total number of logic cells in the design
• NCKBF = # of clock buffers
• NCLBF = # of column clock buffers
• NCKLD = # of loads connected to the column clock buffers
• NRAM = # of RAM blocks
• NINP is the number of input pins
• NOUTP is the number of output pins
Figure 17 exhibits the power consumption in the device. The chip was filled with (300) 8-bit counters, approximately 76%
logic cell utilization.
Power vs Frequency (Counter_300)
2.5
Power (W)
2
1.5
1
.5
0
0
20
40
60
80
100
Frequency (Mhz)
Figure 17: Power Consumption
27
120
140
Power-Up Sequencing
VCCIO
Voltage
VCC
tPOR
VCCOFFSET
tRVCC
Time
Figure 18. Power-Up Requirements/Recommendations
Notes:
1. VCC and VCCIO should either be ramped simultaneously to their final values (as shown) or with the core voltage VCC leading the
I/O voltage VCCIO.
2. Rise time for the voltage supplies (tRVCC) must be within the range of 1s < tRVCC <200ms.
3. Voltage power up/power down ramps for the supplies must be monotonically increasing/decreasing.
4. The starting point for power up (VCCOFFSET) must be less than or equal to 300mV.
5. Users must allow time for the asynchronous power on reset to complete initialization of the device (tPOR). For fast rise times,
(tRVCC <10msec) a minimum tPOR =10 msec must be allowed. For slower rise times, 10ms <tRVCC <200ms, a minimum
tPOR=tRVCC must be allowed.
28
Joint Test Access Group (JTAG)
TCK
TAp Controller
State Machine
(16 States)
TMS
Instruction Decode
&
Control Logic
TRSTB
Instruction Register
RDI
Mux
Mux
TDO
Boundary-Scan
Register (Data Register)
Bypass
Register
Internal
Register
I/O Registers
User Defined Data Register
Figure 19. JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not in the least of
which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge,
resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register
(IR), which allow users to run three required tests along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller
verification of higher level system elements.
The 1149.1 standard requires the following three tests:
• Extest Instruction: The Extest instruction performs a PCB interconnect test. This test places a device into an external
boundary test mode, selecting the boundary scan register to be connected between the TAP’s Test Data In (TDI) and Test
Data Out (TDO) pins. Boundary scan cells are preloaded with test patters (via the Sample/Preload Instruction), and input
boundary cells capture the input data for analysis.
• Sample/Preload Instruction: This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed
29
via a data scan operation, allowing users to sample the functional data entering and leaving the device.
• Bypass Instruction: The Bypass instruction allows data to skip a device’s boundary scan entirely, so the data passes through the
bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is
connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation
of the device.
Table 7: JTAG Pin Descriptions
Pin
Function
Description
TDI/RSI
Test Data In for JTAG/RAM init. Serial Data In Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VCC if
unused.
TRSTB/RRO
Active low Reset for JTAG/RAM init. reset out Hold LOW during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to GND
if unused.
TMS
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to VCC if
not used for JTAG.
TCK
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect
to VCC or GND if not used for JTAG.
Test data out for JTAG/RAM init. clock out
Connect to serial PROM clock for RAM initialization.
Must be left unconnected if not used for JTAG or RAM
initialization.
TDO/RCO
Recommended Unused Pin Terminations for the UT6325 Eclipse FPGA Devices
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration editor.
This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint ->Fix
Placement in the Option pull-down menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 8.
30
Table 8: Recommended Unused Pin Terminations
Signal Name
Recommended Termination
IOCTRL <y>
Any unused pins of this type should be connected to either VCC or GND (recommended: GND).
CLK/PLLIN <x>
Any unused clock pins should be connected to either VCC or GND (recommended: GND).
INREF <y>
If an I/O bank does not require the use of an INREF signal, that INREF pin should be connected
to GND.
VCCPLL <x>
If a PLL is not used, the associated VCCPLL must be connected to the same voltage as PLLRST
(2.5V or GND; recommend GND).
PLLRST <x>
If a PLL is not used, the associated PLLRST must be connected to the same voltage as VCCPLL
(2.5V or GND; recommend GND).
PLLOUT <x>
Unused PLLOUT pins must be connected to either VCC or GND so that the input buffer portion
never floats (recommend GND). Utilized PLLs which route the PLL clock outside of the chip
require use of the associated PLLOUT pin.
Note: X---> number, Y ---> alphabetical character
31
PACKAGING
Figure 20. 208-pin Ceramic FLATPACK
32
Figure 21. 288-pin Ceramic Quad FLATPACK
33
Figure 22. 484-pin Ceramic Column Grid Array
34
Figure 23. 484-pin Ceramic Land Grid Array
35
Figure 24. 208-pin Plastic Quad Flat Pack
36
Figure 25. 280-pin Plastic Ball Grid Array
37
Figure 26. 484-pin Plastic Ball Grid Array
38
ORDERING INFORMATION
UT6325 RadTol Eclipse FPGA:
UT ***** *
*
*
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold, solder, or tinned)
Screening: (NOTES 3 & 4)
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Packaging: (NOTE 5)
(W) = 208-pin PQFP Plastic Quad Flatpack
(X) = 208-pin CQFP Ceramic Quad Flatpack
(P) = 280-pin PBGA Plastic Ball Grid Array
(Y) = 288-pin CQFP Ceramic Quad Flatpack
(R) = 484-pin PBGA Plastic Ball Grid Array
(Z) = 484-pin CLGA Ceramic Land Grid Array
(S) = 484-pin CCGA Ceramic Column Grid Array
Device Type:
(6325) = FPGA
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is FACTORY OPTION "X" only. Radiation
neither tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C.
Radiation neither tested nor guaranteed.
5. Use the following table to determine which lead finishes to select for the corresponding package options.
Package Option
Associated Lead Finish Option
(W) 208-PQFP
(A) Hot Solder Dipped
(X) 208-CQFP
(C) Gold
(P) 280-PBGA
(A) Hot Solder Dipped
(Y) 288-CQFP
(C) Gold
(R) 484-PBGA
(A) Hot Solder Dipped
(Z) 484-CLGA
(C) Gold
(S) 484-CCGA
(A) Hot Solder Dipped
39
UT6325 FPGA: SMD
5962 - 04229
** * * *
Lead Finish:
(C) = Gold
(A) = Solder
Case Outline: (NOTE 1)
(X) = 208-pin CQFP Ceramic Quad Flatpack
(Y) = 288-pin CQFP Ceramic Quad Flatpack
(Z) = 484-pin CLGA Ceramic Land Grid Array
(V) = 484-pin CCGA Ceramic Land Grid Array
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type (NOTE 2)
01 = UT6325 (Temperature Range: -55oC to +125oC)
02 = No Longer Available. Contact Factory
03 = UT6325 assembled to Aeroflex’s Q+ flow
Drawing Number: 04229
Total Dose: (NOTE 3)
(R) = 1E5 (100 krad)(Si))
(F) = 3E5 (300 krad)(Si))
Federal Stock Class Designator: No options
Notes:
1. Case outlines "X", "Y" and "Z" can only be ordered with Gold lead finish "C". Case outline "V" can only be ordered with Solder lead finish "A".
2. Aeroflex’s Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QML-Q product through that SMD that is manufactured with Aeroflex’s
standard QML-V flow.
3.Aeroflex’s Total dose radiation must be specified when ordering. QML Q not available without radiation hardening.
40
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
COLORADO
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Aeroflex Colorado Springs, Inc. reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
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Aeroflex or of third parties.
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