Standard Products UT8RHEEB-208C RadTol Eclipse FPGA UT6325 Evaluation Board Preliminary Data Sheet September 2008 www.aeroflex.com/FPGA INTRODUCTION FEATURES User configurable evaluation board for the UT6325 RadTol Eclipse FPGAs Supports the 208 ceramic quad flatpack Ideal for rapid evaluation of the RadTol Eclipse FPGA functionality, DC and AC performance Includes full access to every I/O on the RadTol Eclipse FPGA - Selectable 4.7K-ohm pull-up, 4.7K-ohm pull-down, tristate - Logic analyzer and wire-wrap access through dual-row header strips JTAG access support SMB connectors for all clock inputs to the board BNC connctors for all power supply and voltage reference inputs Extensive prototyping area to support convenient inclusion of customer circuitry The UT8RHEEB-208C Evaluation Board supplies users of the UT6325 RadTol Eclipse FPGA with a quick, convenient environment for evaluating the 208-ceramic quad flatpack version of the RadTol Eclipse FPGA. To maximize the user’s ability to control and access every FPGA I/O, the UT8RHEEB-208C provides 4.7K-ohm, switchselectable, I/O bias to either VCCIO or VSS. If the user does not wish to bias an FPGA I/O signal, the net may be isolated from either power supply rail. All FPGA I/O’s are connected to dualrow headers which are optimized to interface with Tektronix logic analyzer pods. Furthermore, the header pins protrude ~ 1/2" below the board in order to provide wire-wrap access to the respective FPGA I/O. Coupling the wire-wrap access with local prototyping area, the UT8RHEEB-208C provides a convenient interface between custom circuitry and the RadTol Eclipse FPGA. The board’s flexible design demonstrates some of the capabilities of the 208-CQFP UT6325 RadTol Eclipse FPGA devices, and enables fast development with full pin access and code verification. Because the UT8RHEEB-208C includes a socket for the UT6325 in a un-lead formed 208-CQFP, the board can be used to verify proper programming of the device prior to installing it onto your target PCB. 4 HARDWARE DESCRIPTION Table 1: The UT8RHEEB-208C Evaluation Board contains the following functional components Name U2 J1 J2 J3 J4 JP1-JP4, JP39-JP46 JP5-JP12 SW2-SW25 JP31 – JP38 JP25 – JP28 SW1 JP30 JP29 JP47 – JP54 J5 – J21 Description FPQ-352 socket for Aeroflex’s UT6325 RadHard Eclipse FPGA devices BNC Connector for VCC CORE 2.5V BNC Connector for VCCIO 3.3V BNC Connector for VCCIO 2.5V BNC Connector for VCCPLL 2.5V Header-2 for testing current measurements • These headers must present a “short” across the pins to ensure proper operation of the board. Header-3 The VCCIOA – VCCIOH must be connected to either 2.5V or 3.3V: • Place a jumper between VCCIO* and 2.5V to connect the signal to VCCIO-2.5V • Place a jumper between VCCIO* and 3.3V to connect the signal to VCCIO-3.3V 12-position DIP 24 Switches • Setting the Even switch to the “ON” position ties the corresponding I/O to VCCIO via a 4.7K-ohm pull up • Setting the Odd switch to the “ON” position ties the corresponding I/O to GND via a 4.7K-ohm pull down • Setting the respective switches to the “OFF” position isolates the corresponding I/O from either power supply rail by floating the net • Setting both switches (Even and Odd) to the “ON” position ties the corresponding I/O to 4.7K-ohm voltage divider 17x2_100 mil, Dual-Row Headers • FPGA I/Os are available at these connectors • Tektronix TLA Logic Analyzer Pods can plug directly onto the connectors • Wire-wrap access is available at these headers from the bottom-side of the board Header-3 • The VCCPLL0 – VCCPLL3 must be connected to either VCCPLL or GNDPLL Place a jumper between VCCPLL* and VCCPLL to connect the signal to VCCPLL 2.5V Place a jumper between VCCPLL* and GNDPLL to connect the signal to GNDPLL Push button reset switch for PLLRST 4-Pin PLLRST Header 8-Pin JTAG Connector Header-2 for INREFA-INREFH • Placing a jumper on the header ties the corresponding INREF* to GND via a 10Kohm pull down SMB Connectors • The CLK0 – CLK8 and the INREF(A) – INREF(H) signals are accessible through to SMB Connectors 2 Table 2: UT8RHEEB-208C FPGA Evaluation Board Netlist 208CQFP Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Net Name Switch Access Point PLLRST3 VCCPLL3 GND GND IOA1 IOA2 IOA3 VCCIOA IOA4 IOA5 IOCTRLA1 VCC INREF(A) IOCTRLA2 IOA6 IOA7 IOA8 IOA9 VCCIOA IOA10 GND IOA11 TDI CLK0 CLK1 VCC CLK2 CLK3 VCC CLK4 IOB1 IOB2 GND VCCIOB IOB3 IOB4 IOB5 IOB6 IOCTRLB1 INREF(B) IOCTRLB2 IOB7 IOB8 VCCIOB IOB9 VCC IOB10 IOB11 GND TDO PLLOUT1 GNDPLL GND VCCPLL2 PLLRST2 VCC IOC1 GND IOC2 VCCIOC IOC3 NA NA NA NA SW2 SW2 SW2 NA SW2 SW2 SW2 NA NA SW3 SW3 SW3 SW3 SW3 NA SW3 NA SW4 NA SW4 SW4 NA SW4 SW4 NA SW7 SW5 SW5 NA NA SW5 SW5 SW5 SW5 SW6 NA SW6 SW6 SW6 NA SW6 NA SW6 SW7 NA NA SW10 NA NA NA NA NA SW8 NA SW8 NA SW8 JP30.4 VCCPLL3 GND GND JP31.3 JP31.4 JP31.5 JP5 JP31.6 JP31.7 JP31.1 VCC JP39 JP31.2 JP31.8 JP31.9 JP31.10 JP31.11 JP5 JP31.12 GND JP31.13 JP29.3 JP31.14,CLK0 JP31.15,CLK1 VCC JP31.16,CLK2 JP31.17,CLK3 VCC JP32.17,CLK4 JP32.3 JP32.4 GND JP6 JP32.5 JP32.6 JP32.7 JP32.8 JP32.1 JP40 JP32.2 JP32.9 JP32.10 JP6 JP32.11 VCC JP32.12 JP32.13 GND JP29.2 JP33.17 GNDPLL GND VCCPLL2 JP30.3 VCC JP33.3 GND JP33.4 JP7 JP33.5 208CQFP Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 3 Net Name Switch Access Point IOC4 IOC5 IOC6 IOC7 IOC8 IOCTRLC1 INREF(C) IOCTRLC2 IOC9 IOC10 VCCIOC IOC11 IOC12 GND VCC IOC13 TRSTB VCC IOD1 IOD2 IOD3 GND VCCIOD IOD4 VCC IOD5 IOD6 VCC IOD7 IOD8 IOCTRLD1 INREF(D) IOCTRLD2 IOD9 IOD10 IOD11 VCCIOD IOD12 IOD13 GND PLLOUT0 GND GNDPLL PLLRST1 VCCPLL1 IOE1 GND IOE2 IOE3 VCCIOE IOE4 VCC IOE5 IOE6 IOE7 IOCTRLE1 INREF(E) IOCTRLE2 IOE8 IOE9 VCCIOE SW8 SW8 SW8 SW9 SW9 SW9 NA SW9 SW9 SW9 NA SW10 SW10 NA NA SW10 NA NA SW11 SW11 SW11 NA NA SW11 NA SW11 SW11 NA SW12 SW12 SW12 NA SW12 SW12 SW12 SW13 NA SW13 SW13 NA SW13 NA NA NA NA SW14 NA SW14 SW14 NA SW14 NA SW14 SW14 SW15 SW15 NA SW15 SW15 SW15 NA JP33.6 JP33.7 JP33.8 JP33.9 JP33.10 JP33.1 JP41 JP33.2 JP33.11 JP33.12 JP7 JP33.13 JP33.14 GND VCC JP33.15 JP29.5 VCC JP34.3 JP34.4 JP34.5 GND JP8 JP34.6 VCC JP34.7 JP34.8 VCC JP34.9 JP34.10 JP34.1 JP42 JP34.2 JP34.11 JP34.12 JP34.13 JP8 JP34.14 JP34.15 GND JP34.17 GND GNDPLL JP30.2 VCCPLL1 JP35.3 GND JP35.4 JP35.5 JP9 JP35.6 VCC JP35.7 JP35.8 JP35.9 JP35.1 JP43 JP35.2 JP35.10 JP35.11 JP9 Table 2: UT8RHEEB-208C FPGA Evaluation Board Netlist (Continued) 208 CQFP Pin 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Net Name Switch Access Point GND IOE10 IOE11 IOE12 CLK5 CLK6 VCC CLK7 VCC CLK8 TMS IOF1 IOF2 IOF3 GND VCCIOF IOF4 IOF5 IOF6 IOF7 IOF8 IOCTRLF1 INREF(F) VCC IOCTRLF2 IOF9 IOF10 VCCIOF IOF11 IOF12 GND IOF13 PLLOUT3 GNDPLL GND VCCPLL0 PLLRST0 GND IOG1 VCCIOG IOG2 IOG3 VCC NA SW15 SW16 SW16 SW16 SW16 NA SW16 NA SW19 NA SW17 SW17 SW17 NA NA SW17 SW17 SW17 SW18 SW18 SW18 NA NA SW18 SW18 SW18 NA SW19 SW19 NA SW19 SW22 NA NA NA NA NA SW20 NA SW20 SW20 NA GND JP35.12 JP35.13 JP35.14 JP35.15,CLK5 JP35.16,CLK6 VCC JP35.17,CLK7 VCC JP36.17,CLK8 JP29.6 JP36.3 JP36.4 JP36.5 GND JP10 JP36.6 JP36.7 JP36.8 JP36.9 JP36.10 JP36.1 JP44 VCC JP36.2 JP36.11 JP36.12 JP10 JP36.13 JP36.14 GND JP36.15 JP37.17 GNDPLL GND VCCPLL0 JP30.1 GND JP37.3 JP11 JP37.4 JP37.5 VCC 208 CQFP Pin 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 4 Net Name Switch Access Point IOG4 IOG5 IOG6 IOCTRLG1 INREF(G) IOCTRLG2 IOG7 IOG8 IOG9 VCC IOG10 VCCIOG GND IOG11 IOG12 IOG13 VCC TCK VCC IOH1 IOH2 IOH3 GND VCCIOH IOH4 IOH5 IOCTRLH1 IOH6 INREF(H) VCC IOCTRLH2 IOH7 IOH8 IOH9 IOH10 IOH11 IOH12 VCCIOH GND IOH13 PLLOUT2 GND GNDPLL SW20 SW20 SW20 SW21 NA SW21 SW21 SW21 SW21 NA SW21 NA NA SW22 SW22 SW22 NA NA NA SW23 SW23 SW23 NA NA SW23 SW23 SW23 SW24 NA NA SW24 SW24 SW24 SW24 SW24 SW25 SW25 NA NA SW25 SW25 NA NA JP37.6 JP37.7 JP37.8 JP37.1 JP45 JP37.2 JP37.9 JP37.10 JP37.11 VCC JP37.12 JP11 GND JP37.13 JP37.14 JP37.15 VCC JP29.8 VCC JP38.3 JP38.4 JP38.5 GND JP12 JP38.6 JP38.7 JP38.1 JP38.8 JP46 VCC JP38.2 JP38.9 JP38.10 JP38.11 JP38.12 JP38.13 JP38.14 JP12 GND JP38.15 JP38.17 GND GNDPLL ORDERING INFORMATION UT8RHEEB208 RadTol FPGA Evaluation Board: UT8RHEEB-208 Base Part Number: Note 1 UT8RHEEB-208C = UT6325 Evaluation Board with 208package support NOTE 1: The UT8RHEEB-208C does not include a UT6325 FPGA. This device should be purchased as a separate line item on the purchase order. 5 5 4 3 2 1 Revision History 09/07/04: First Release SILK: 2.5V CORE POWER J xx/xx/xx: J VCC_CORE On the board place a de-coupling capacitor very close to each VCC input UT6325 (The UT6325 has 18 VCC pins) J1 BNC JP1 1 1 2 + 2 JUMPER C1 47uF + C2 47uF C3 47uF + + C5 .01uF C4 47uF C6 .1uF C7 .01uF C8 .1uF C9 .01uF C10 .1uF C11 .01uF C12 .1uF C13 .01uF C14 .1uF C15 .01uF C16 .1uF C17 .01uF C18 .1uF C19 .01uF C20 .1uF C21 .01uF C22 .1uF C23 .01uF C24 .1uF I I SILK: 3.3V I/O POWER SILK: 2.5V PLL POWER SILK: 2.5V I/O POWER VCCPLL VCCIO_33V J2 BNC JP4 1 2 JUMPER C37 47uF + C38 47uF C39 47uF + + C40 47uF JP3 1 C26 .01uF 2 + 2 1 + JUMPER 2 1 H VCCIO_25V J3 BNC JP2 1 C25 47uF C27 .1uF + C29 .01uF C28 47uF C30 .1uF 1 2 + JUMPER 2 J4 BNC C32 .01uF C31 47uF C33 .1uF + C34 47uF C35 .01uF C36 .1uF H G G VCCIO_25V JP5 C41 .01uF C42 .1uF JP6 1 2 3 vccioa + C43 47uF vcciob C45 .1uF C44 .01uF HEADER 3 + C46 47uF JP7 1 2 3 vccioc C47 .01uF HEADER 3 C48 .1uF + C49 47uF 1 2 3 JP8 C50 .01uF C51 .1uF HEADER 3 JP9 1 2 3 vcciod + C52 47uF C53 .01uF C54 .1uF HEADER 3 JP10 1 2 3 vccioe + C55 47uF C56 .01uF C57 .1uF HEADER 3 JP11 1 2 3 vcciof + C58 47uF C59 .01uF C60 .1uF HEADER 3 JP12 1 2 3 vcciog + C61 47uF 1 2 3 vccioh C62 .01uF C63 .1uF + C64 47uF HEADER 3 HEADER 3 F F VCCIO_33V E E (Note: Distribute evenly around the board) VCCPLL JP13 JP14 JP15 JP16 JP17 JP18 JP19 JP20 JP21 JP22 JP23 JP24 TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND TP_GND C65 .01uF + C66 47uF C67 .01uF C68 .1uF HEADER 3 C69 .01uF + C70 47uF C71 .01uF C72 .1uF C73 .01uF HEADER 3 + C75 .01uF C74 47uF C76 .1uF C77 .01uF + HEADER 3 C79 .01uF C78 47uF C80 .1uF 1 1 1 1 1 1 1 1 2 3 1 JP28 vccpll3 1 1 2 3 vccpll2 1 JP27 1 2 3 1 JP26 vccpll1 1 JP25 1 2 3 vccpll0 HEADER 3 D D VCC_CORE vccpll3 vccpll2 vccpll1 vccpll0 VCC_CORE VCC_CORE D1 C DIODE (Notes appear in silkscreen) 10k 10k R6 R7 VCC_CORE R1 R2 R3 R4 R5 10k 4.7k 4.7k 4.7k 4.7k C 1 2 3 4 5 6 7 8 tdo tdi U1B 2 SN74HC14D 3 D2 JP30 4 SN74HC14D trstb tms 1 2 3 4 DIODE D3 PLLRST(0) PLLRST(1) PLLRST(2) PLLRST(3) PLLRST U1A 1 HEADER 4 tck C81 HEADER 8 1 B JTAG INTERFACE (Notes appear in silkscreen) JP29 VCC TDO TDI N/C TRSTB TMS GND TCK 10k 47uF B DIODE D4 R8 2 10k SW1 C82 .01uF R9 SW SPST DIODE D5 pllrst0 DIODE A pllrst1 pllrst3 UT6325 RadHard FPGA Evaluation Board Size C Date: 5 4 3 2 A Title pllrst2 Document Number 4350098-000 Rev 01 Tuesday, September 14, 2004 1 Sheet 1 of 5 5 4 JP31 JP33 1 JP34 JP35 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(a1) ioctrl(a2) io(a1) io(a2) io(a3) io(a4) io(a5) io(a6) 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(b1) ioctrl(b2) io(b1) io(b2) io(b3) io(b4) io(b5) io(b6) 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(c1) ioctrl(c2) io(c1) io(c2) io(c3) io(c4) io(c5) io(c6) 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(d1) ioctrl(d2) io(d1) io(d2) io(d3) io(d4) io(d5) io(d6) 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(e1) ioctrl(e2) io(e1) io(e2) io(e3) io(e4) io(e5) io(e6) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(a7) io(a8) io(a9) io(a10) io(a11) clk(0) clk(1) clk(2) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(b7) io(b8) io(b9) io(b10) io(b11) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(c7) io(c8) io(c9) io(c10) io(c11) io(c12) io(c13) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(d7) io(d8) io(d9) io(d10) io(d11) io(d12) io(d13) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(e7) io(e8) io(e9) io(e10) io(e11) io(e12) clk(5) clk(6) 18 18 17 17 clk(3) 18 18 17 17 clk(4) 18 18 17 17 pllout(1) 18 18 17 17 pllout(0) 18 18 17 17 clk(7) 5 tek_la_hdr_17x2 CLK0 tek_la_hdr_17x2 4 I J6 SMB 1 H Note: Signal names appear in silkscreen 3 2 J8 SMB 1 5 5 4 4 J7 SMB 1 5 CLK4 J tek_la_hdr_17x2 CLK5 H CLK1 tek_la_hdr_17x2 J5 SMB 1 3 2 4 tek_la_hdr_17x2 5 I JP32 2 3 2 J 3 CLK6 J9 SMB 1 3 2 3 2 4 CLK2 J10 SMB 1 3 2 4 5 F CLK3 J12 SMB 1 G JP38 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(f1) ioctrl(f2) io(f1) io(f2) io(f3) io(f4) io(f5) io(f6) 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(g1) ioctrl(g2) io(g1) io(g2) io(g3) io(g4) io(g5) io(g6) 34 33 32 31 30 29 28 27 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ioctrl(h1) ioctrl(h2) io(h1) io(h2) io(h3) io(h4) io(h5) io(h6) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(f7) io(f8) io(f9) io(f10) io(f11) io(f12) io(f13) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(g7) io(g8) io(g9) io(g10) io(g11) io(g12) io(g13) 26 25 24 23 22 21 20 19 26 25 24 23 22 21 20 19 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 io(h7) io(h8) io(h9) io(h10) io(h11) io(h12) io(h13) 18 17 17 18 17 17 18 17 17 18 3 2 4 JP37 34 33 32 31 30 29 28 27 18 clk(8) tek_la_hdr_17x2 5 E CLK8 CLK7 4 J11 SMB 1 F Revision History 09/07/04: First Release xx/xx/xx: pllout(2) tek_la_hdr_17x2 E J13 SMB 1 3 2 4 18 pllout(3) tek_la_hdr_17x2 5 5 JP36 34 33 32 31 30 29 28 27 3 2 G D D B JUMPER inrefb 4 JP41 1 2 JUMPER inrefc 4 JP42 1 2 4 inrefd JUMPER JP43 1 2 JUMPER inrefe 4 JP44 1 2 inreff JUMPER 4 JP45 1 2 inrefg 4 JUMPER 10k 10k 10k 10k 10k 10k 10k R10 R11 R12 R13 R14 R15 R16 J21 SMB 1 JP46 1 2 10k R17 JP47 JP48 JP49 JP50 JP51 JP52 JP53 JP54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 HEADER 2 HEADER 2 HEADER 2 HEADER 2 HEADER 2 HEADER 2 HEADER 2 HEADER 2 A C inrefh JUMPER 3 2 2 3 2 JP40 1 3 2 JUMPER 4 3 2 inrefa 3 2 2 3 2 JP39 1 3 2 4 3 2 C INREF(H) 5 J20 SMB 1 5 INREF(G) J19 SMB 1 5 INREF(F) J18 SMB 1 5 INREF(E) J17 SMB 1 5 INREF(D) J16 SMB 1 5 INREF(C) J15 SMB 1 5 INREF(B) J14 SMB 1 5 INREF(A) B A Title UT6325 RadHard FPGA Evaluation Board Size C Date: 5 4 3 2 Document Number 4350098-000 Rev 01 Tuesday, September 14, 2004 1 Sheet 2 of 5 5 4 3 2 1 Revision History 09/07/04: First Release xx/xx/xx: Note: Signal names appear in silkscreen J J RP1 io(a1) io(a2) io(a3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP7 I io(a4) io(a5) ioctrl(a1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vccioa SW2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP2 ioctrl(a2) io(a6) io(a7) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP8 io(a8) SW DIP-12 io(a9) io(a10) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vccioa SW3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP3 io(a11) clk(0) clk(1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP9 clk(2) SW DIP-12 clk(3) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vccioa SW4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP4 io(b1) io(b2) io(b3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP10 io(b4) SW DIP-12 io(b5) io(b6) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciob SW5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP5 ioctrl(b1) ioctrl(b2) io(b7) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP11 io(b8) SW DIP-12 io(b9) io(b10) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vcciob SW6 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP6 io(b11) clk(4) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciob SW7 1 2 3 4 5 6 7 8 9 10 11 12 SW DIP-12 24 23 22 21 20 19 18 17 16 15 14 13 I SW DIP-12 4.7k H H RP12 io(c1) io(c2) io(c3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k G RP18 io(c4) io(c5) io(c6) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vccioc SW8 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP13 io(c7) io(c8) ioctrl(c1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP19 ioctrl(c2) SW DIP-12 io(c9) io(c10) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vccioc SW9 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP14 io(c11) io(c12) io(c13) pllout(1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vccioc SW10 1 2 3 4 5 6 7 8 9 10 11 12 SW DIP-12 24 23 22 21 20 19 18 17 16 15 14 13 RP15 io(d1) io(d2) io(d3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP20 io(d4) SW DIP-12 io(d5) io(d6) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciod SW11 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP16 io(d7) io(d8) ioctrl(d1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP21 ioctrl(d2) SW DIP-12 io(d9) io(d10) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vcciod SW12 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP17 io(d11) io(d12) io(d13) pllout(0) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciod SW13 1 2 3 4 5 6 7 8 9 10 11 12 SW DIP-12 24 23 22 21 20 19 18 17 16 15 14 13 G SW DIP-12 4.7k F F RP22 io(e1) io(e2) E io(e3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP28 io(e4) io(e5) io(e6) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vccioe SW14 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP23 io(e7) ioctrl(e1) ioctrl(e2) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP29 io(e8) SW DIP-12 io(e9) io(e10) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vccioe SW15 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP24 io(e11) io(e12) clk(5) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP30 clk(6) SW DIP-12 clk(7) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vccioe SW16 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP25 io(f1) io(f2) io(f3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP31 io(f4) SW DIP-12 io(f5) io(f6) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciof SW17 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP26 io(f7) io(f8) ioctrl(f1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP32 ioctrl(f2) SW DIP-12 io(f9) io(f10) 1 2 3 4 5 6 7 8 4.7k 16 15 14 13 12 11 10 9 vcciof SW18 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP27 io(f11) io(f12) io(f13) clk(8) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciof SW19 1 2 3 4 5 6 7 8 9 10 11 12 SW DIP-12 24 23 22 21 20 19 18 17 16 15 14 13 E SW DIP-12 4.7k D D RP33 io(g1) C io(g2) io(g3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP39 io(g4) io(g5) io(g6) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vcciog SW20 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SW DIP-12 RP34 ioctrl(g1) ioctrl(g2) io(g7) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP40 io(g8) io(g9) io(g10) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vcciog SW21 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RP35 io(g11) io(g12) io(g13) pllout(3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k SW DIP-12 vcciog SW22 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SW DIP-12 RP36 io(h1) io(h2) io(h3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP41 io(h4) io(h5) ioctrl(h1) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k 4.7k vccioh SW23 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SW DIP-12 RP37 io(h6) ioctrl(h2) io(h7) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RP42 io(h8) io(h9) io(h10) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vccioh SW24 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SW DIP-12 RP38 io(h11) io(h12) io(h13) pllout(2) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k vccioh SW25 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 C SW DIP-12 4.7k B B A A Title UT6325 RadHard FPGA Evaluation Board Size D Document Number 4350098-000 Tuesday, September 14, 2004 Date: 5 4 3 2 1 Rev 01 Sheet 3 of 5 5 4 3 2 1 J J Revision History 09/07/04: First Release xx/xx/xx: I I Note: ROUTES AS SHORT AS POSSIBLE tck io(g13) io(g12) io(g11) io(h1) io(h2) io(h3) io(g10) io(h4) io(h5) ioctrl(h1) io(h6) H H io(g9) io(g8) io(g7) ioctrl(g2) inrefh inrefg ioctrl(h2) io(h7) io(h8) io(h9) io(h10) io(h11) io(h12) ioctrl(g1) io(g6) io(g5) io(g4) io(g3) io(g2) io(g1) io(h13) pllout(2) pllrst0 VCC_CORE vccioh vcciog vccioa 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vccpll0 pllrst3 vccpll3 io(a1) io(a2) io(a3) io(a4) io(a5) ioctrl(a1) inrefa ioctrl(a2) io(a6) io(a7) io(a8) io(a9) io(a10) io(a11) tdi clk(0) clk(1) clk(2) clk(3) clk(4) io(b1) io(b2) F vcciob io(b3) io(b4) io(b5) io(b6) ioctrl(b1) inrefb ioctrl(b2) io(b7) io(b8) io(b9) io(b10) io(b11) tdo pllout(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PLLRST(3) VCCPLL(3) GND GND IO(A1) IO(A2) IO(A3) VCCIO(A) IO(A4) IO(A5) IOCTRL(A1) VCC INREF(A) IOCTRL(A2) IO(A6) IO(A7) IO(A8) IO(A9) VCCIO(A) IO(A10) GND IO(A11) TDI CLK(0) CLK(1) VCC CLK(2) CLK(3) VCC CLK(4) IO(B1) IO(B2) GND VCCIO(B) IO(B3) IO(B4) IO(B5) IO(B6) IOCTRL(B1) INREF(B) IOCTRL(B2) IO(B7) IO(B8) VCCIO(B) IO(B9) VCC IO(B10) IO(B11) GND TDO PLLOUT(1) GNDPLL(2) GNDPLL(3) GND PLLOUT(2) IO(H13) GND VCCIO(H) IO(H12) IO(H11) IO(H10) IO(H9) IO(H8) IO(H7) IOCTRL(H2) VCC INREF(H) IO(H6) IOCTRL(H1) IO(H5) IO(H4) VCCIO(H) GND IO(H3) IO(H2) IO(H1) VCC TCK VCC IO(G13) IO(G12) IO(G11) GND VCCIO(G) IO(G10) VCC IO(G9) IO(G8) IO(G7) IOCTRL(G2) INREF(G) IOCTRL(G1) IO(G6) IO(G5) IO(G4) VCC IO(G3) IO(G2) VCCIO(G) IO(G1) GND PLLRST(0) VCCPLL(0) GND vcciof G GNDPLL(0) PLLOUT(3) IO(F13) GND IO(F12) IO(F11) VCCIO(F) IO(F10) IO(F9) IOCTRL(F2) VCC INREF(F) IOCTRL(F1) IO(F8) IO(F7) IO(F6) IO(F5) IO(F4) VCCIO(F) GND IO(F3) IO(F2) IO(F1) TMS CLK(8) VCC CLK(7) VCC CLK(6) CLK(5) IO(E12) IO(E11) IO(E10) GND VCCIO(E) IO(E9) IO(E8) IOCTRL(E2) INREF(E) IOCTRL(E1) IO(E7) IO(E6) IO(E5) VCC IO(E4) VCCIO(E) IO(E3) IO(E2) GND IO(E1) VCCPLL(1) PLLRST(1) UT6325 G 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 pllout(3) io(f13) io(f12) io(f11) io(f10) io(f9) ioctrl(f2) inreff ioctrl(f1) io(f8) io(f7) io(f6) io(f5) io(f4) io(f3) io(f2) io(f1) tms clk(8) clk(7) clk(6) clk(5) io(e12) io(e11) io(e10) F io(e9) io(e8) ioctrl(e2) inrefe ioctrl(e1) io(e7) io(e6) io(e5) io(e4) io(e3) io(e2) io(e1) vccpll1 pllrst1 GND VCCPLL(2) PLLRST(2) VCC IO(C1) GND IO(C2) VCCIO(C) IO(C3) IO(C4) IO(C5) IO(C6) IO(C7) IO(C8) IOCTRL(C1) INREF(C) IOCTRL(C2) IO(C9) IO(C10) VCCIO(C) IO(C11) IO(C12) GND VCC IO(C13) TRSTB VCC IO(D1) IO(D2) IO(D3) GND VCCIO(D) IO(D4) VCC IO(D5) IO(D6) VCC IO(D7) IO(D8) IOCTRL(D1) INREF(D) IOCTRL(D2) IO(D9) IO(D10) IO(D11) VCCIO(D) IO(D12) IO(D13) GND PLLOUT(0) GND GNDPLL(1) vccioe E 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 E vccpll2 vccioc vcciod GNDPLL pllrst2 pllout(0) io(c1) io(d13) io(d12) io(c2) io(d11) io(d10) io(d9) ioctrl(d2) io(c3) io(c4) io(c5) io(c6) io(c7) io(c8) ioctrl(c1) inrefd ioctrl(d1) io(d8) io(d7) inrefc ioctrl(c2) io(c9) io(c10) io(d6) io(d5) io(d4) D D io(c11) io(c12) io(d3) io(d2) io(d1) io(c13) trstb C C B B A A Title UT6325 RadHard FPGA Evaluation Board Size E Date: 5 4 3 2 1 Document Number 4350098-000 Tuesday, September 14, 2004 Rev 01 Sheet 4 of 5 5 4 3 J 2 1 io(a1) io(a2) io(a3) io(a4) io(a5) ioctrl(a1) ioctrl(a2) io(a6) io(b1) io(b2) io(b3) io(b4) io(b5) io(b6) ioctrl(b1) ioctrl(b2) io(a7) io(a8) io(a9) io(a10) io(a11) clk(0) clk(1) clk(2) io(b7) io(b8) io(b9) io(b10) io(b11) clk(4) J clk(3) I I C83 No Pop C84 No Pop C85 No Pop C86 No Pop C87 No Pop C88 No Pop C89 No Pop C90 No Pop C91 No Pop C92 No Pop C93 No Pop C94 No Pop C95 No Pop C96 No Pop C97 No Pop C98 No Pop C99 No Pop H C100 No Pop C101 No Pop C102 No Pop C103 No Pop C104 No Pop C105 No Pop C106 No Pop C107 No Pop C108 No Pop C109 No Pop C110 No Pop C111 No Pop C112 No Pop C113 No Pop io(c1) io(c2) io(c3) io(c4) io(c5) io(c6) io(c7) io(c8) io(d1) io(d2) io(d3) io(d4) io(d5) io(d6) io(d7) io(d8) ioctrl(c1) ioctrl(c2) io(c9) io(c10) io(c11) io(c12) io(c13) pllout(1) ioctrl(d1) ioctrl(d2) io(d9) io(d10) io(d11) io(d12) io(d13) pllout(0) H G G C114 No Pop C115 No Pop C116 No Pop C117 No Pop C118 No Pop C119 No Pop C120 No Pop C121 No Pop C122 No Pop C123 No Pop C124 No Pop C125 No Pop C126 No Pop C127 No Pop C128 No Pop C129 No Pop C130 No Pop F E C131 No Pop C132 No Pop C133 No Pop C134 No Pop C135 No Pop C136 No Pop C137 No Pop C138 No Pop C139 No Pop C140 No Pop C141 No Pop C142 No Pop C143 No Pop C144 No Pop C145 No Pop io(e1) io(e2) io(e3) io(e4) io(e5) io(e6) io(e7) ioctrl(e1) io(f1) io(f2) io(f3) io(f4) io(f5) io(f6) io(f7) io(f8) ioctrl(e2) io(e8) io(e9) io(e10) io(e11) io(e12) clk(5) clk(6) ioctrl(f1) ioctrl(f2) io(f9) io(f10) io(f11) io(f12) io(f13) clk(8) F E clk(7) C146 No Pop C147 No Pop C148 No Pop C149 No Pop C150 No Pop C151 No Pop C152 No Pop C153 No Pop C154 No Pop C155 No Pop C156 No Pop C157 No Pop C158 No Pop C159 No Pop C160 No Pop C161 No Pop D C C179 No Pop C180 No Pop C181 No Pop C182 No Pop C183 No Pop C184 No Pop C185 No Pop C186 No Pop C187 No Pop C188 No Pop C189 No Pop C190 No Pop C191 No Pop C192 No Pop C193 No Pop C194 No Pop C162 No Pop C163 No Pop C164 No Pop C165 No Pop C166 No Pop C167 No Pop C168 No Pop C169 No Pop C170 No Pop C171 No Pop C172 No Pop C173 No Pop C174 No Pop C175 No Pop C176 No Pop C177 No Pop C178 No Pop io(g1) io(g2) io(g3) io(g4) io(g5) io(g6) ioctrl(g1) ioctrl(g2) io(h1) io(h2) io(h3) io(h4) io(h5) ioctrl(h1) io(h6) ioctrl(h2) io(g7) io(g8) io(g9) io(g10) io(g11) io(g12) io(g13) pllout(3) io(h7) io(h8) io(h9) io(h10) io(h11) io(h12) io(h13) pllout(2) C195 No Pop C196 No Pop C197 No Pop C198 No Pop C199 No Pop C200 No Pop C201 No Pop C202 No Pop C203 No Pop C204 No Pop C205 No Pop C206 No Pop C207 No Pop C208 No Pop C209 No Pop D C C210 No Pop Revision History 09/07/04: First Release B xx/xx/xx: B A A Title UT6325 RadHard FPGA Evaluation Board Size C Date: 5 4 3 2 Document Number 4350098-000 Rev 01 Tuesday, September 14, 2004 1 Sheet 5 of 5 C:\CentraWork\4350098_rev03_top.ps 1 of 1 C:\CentraWork\4350098_rev03_bot.ps 1 of 1 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc. reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 6