Aeroflex Colorado Springs Product Advisory UT699-PA-01 UT699 PCI Reset and Clock Requirements Table 1: Cross Reference of Applicable Products Product Name: UT699 32-bit Fault-Tolerant SPARC V8/LEON 3FT Processor Manufacturer Part Number SMD # Device Type Internal PIC* Number: UT699 5962-08228 01, 02 WG07 * PIC = Product Identification Code 1 Overview The UT699 Leon 3FT microprocessor system-on-chip includes a PCI core that can be configured for 32-bit, 33MHz operations. The PCI core requires proper initialization even when PCI is not utilized. If proper initialization requirements are not met, the PCI core can lock up the internal AMBA bus in some instances causing the entire processor to lock up. This lockup condition is identified by the processor performing a single access to PROM at address 0x0 following the de-assertion of RESET with no subsequent PROM accesses occurring. This advisory explains the requirements for PCI initialization. The initialization sequence is required during the power-up sequence after which time the PCI core may be utilized normally as described in Chapter 9.0 PCI Target / Master Unit of the UT699 Functional Manual. Thereafter, each time power is cycled, the system must perform the initialization sequence. Timing requirements for PCI clock gating are also discussed. 2 PCI Initialization Requirements 2.1 PCI Core Utilized in System Figure 1 shows the required timing relationship between the PCI clock input and the RESET and PCIRST inputs when the PCI core is utilized. It is assumed that the VDD and VDDC power rails are stable and the SYSCLK input has a valid clock as described in Section 4.1 Power Sequencing and Reset of the UT699 Leon 3FT Data Sheet. Parameters tCVPH and tCVRH are specified in PCI clock cycles and must be met in order to ensure that the PCI state machine is initialized to idle state prior to the execution of code. RESET may be deasserted after 10 valid PCI clock cycles. There is no timing requirement for RESET relative to PCIRST. The PCI core may be held in reset by asserting PCIRST until core utilization is required. If clock gating is used to reduce power, the PCI clock can be disabled after delaying tPLCI following the assertion of the PCIRST. Refer to Table 2 for a summary of the timing parameters. SYSCLK PCICLK tCVPH tPLCI PCIRST tCVRH RESET Figure 1. Timing Relationships of Clock and Reset Inputs for PCI Core Utilization Creation Date: 6/21/11 Page 1 of 2 Modification Date: 6/21/11 Aeroflex Colorado Springs Product Advisory 2.2 UT699-PA-01 Initialization of Unused PCI Core Figure 2 shows the required timing relationship between the PCI clock input and RESET when the PCI core is not utilized. It is assumed that the VDD and VDDC power rails are stable, and that the SYSCLK input has a valid system clock per Section 4.1 Power Sequencing and Reset of the UT699 Leon 3FT Data Sheet. The critical timing parameter is tCVRH which must be met in order to ensure that the PCI state machine is initialized to idle state. RESET may be deasserted after 10 valid PCI clock cycles. The PCI clock input may be permanently tied low or high immediately following the rising edge of RESET. Since PCI is not being used, PCIRST is permanently tied to VSS. Refer to Table 2 for a summary of critical and recommended timing parameters. SYSCLK PCICLK tCVRH RESET PCIRST Figure 2. Timing Relationships of Clock and Reset Inputs for Unused PCI Core 2.3 Timing Summary The following table summarizes the required and recommended timing parameters to ensure proper PCI core and system operation. Table 2: Summary of Timing Parameters Symbol Description Min Max Units tCVRH PCICLK to RESET deassertion 10 -- PCI clocks tCVPH PCICLK to PCIRST deassertion 10 -- PCI clocks tPLCI PCIRST assertion to PCICLK invalid 10 -- PCI clocks Creation Date: 6/21/11 Page 2 of 2 Modification Date: 6/21/11