GEN 6 Single Board Computer - Aeroflex Microelectronic Solutions

Standard Products
GEN 6 Single Board Computer
Product Brief
August 2015
Aeroflex.com/SBC
The most important thing we build is trust
Features
General
3U cPCI Form Factor
Flexible Architecture
LEON 3FT Based
Radiation Performance
TID > 100 krad(Si)
SEL Immunity: up to 86MeV cm2/mg
Memory
64MB of EDAC SRAM Memory
32MB of EDAC Non-Volatile MRAM
Overview
The GEN 6 LEON 3FT Single Board Computer (SBC) is Cobham Semiconductor Solutions’ (formerly Aeroflex) Flight Ready TRL-6 based, off the shelf system designed for
LEO, GEO, and Planetary command and control applications. The board is designed with
a flexible core architecture to balance power and performance needs. The system is
capable of up to 95 Dhrystone MIPS with a132MHz System Clock.
The GEN 6 SBC is equipped with 64MB of EDAC protected SRAM and 32MB of EDAC
protected Non-Volatile Memory. There are 3 physical interface types on the SBC: cPCI,
SpaceWire and a test and development interface. The cPCI interface connectors support 32 bit 33MHz PCI bus as well as 1553B, SPI, and CAN. The 1553B, SPI and CAN
interfaces are implemented via unused signals of the J2 cPCI connector. The test and
development interface is a 37 pin MDM connector that supports access to the LEON
3FT Debug Support Unit (DSU), Ethernet, and processor reset via the Cobham supplied
Interface Pod.The SBC comes with an additional Interface Pod to expand the capabilities and debug/software loading of the GEN 6 SBC.
Interfaces
Two SpaceWire Ports operating
at 132Mbs max
32 bit 33MHz cPCI bus
Test port for Ethernet, Serial DSU, and
UART interfaces
1553B (UT700 version only)
SPI (UT700 version only)
CAN (All Versions)
Environmental
Acceptance Test Levels: -30°C to +70°C
Qualification Level: -35°C to +80°C
Figure 1. View of the Cobham GEN 6 SBC
Power Requirements:
Requires only the 3.3V supply from the
cPCI backplane. 5V is not required.
Power Consumption:
UT700 Processor
up to 132MHz and 7.3W Max
UT699 Processor
up to 49.5MHz and 8.5W Max
UT699E Processor
up to 66MHz and 6.6W Max
958025-000
Version 1.2.0
-1 -
Cobham Semiconductor Solutions
Aeroflex.com/SBC
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Figure 2. GEN 6 SBC Block Diagram
System Synchronized Multi-Frequency Clock Network Management System
The GEN 6 SBC is capable of managing power and performance by configuring board components to run clock frequencies that are ideal
for a particular user application. There are five available configurations offering different performance in regard to speed, throughput,
and power. Thus, users can choose a configuration tailored to their particular power and performance needs when using the GEN 6 SBC.
The following table demonstrates the possible configurations:
Table 1 Possible Clock Configurations
CPU Version
CPU Clock
SpaceWire Clock
UT700
33MHz
33MHz
UT700
66MHz
132MHz
UT700
132MHz
132MHz
UT699E
33MHz
33MHz
UT699E
66MHz
132MHz
UT699
49.5MHz
99MHz
Expandable Digital IO Capabilities
The GEN 6 SBC is capable of supporting additional signal types by connecting to 8 spare signal pins on the cPCI J2 connector on the SBC
backplane. Users who need to process signal types outside the integrated feature set can construct a simple expander card that attaches
to these 8 pins to drive those signal types across the SBC, allowing for extensibility to applications outside its base feature set.
958025-000
Version 1.2.0
-2 -
Cobham Semiconductor Solutions
Aeroflex.com/SBC
J3 Interface Pod
The GEN 6 includes an Interface Pod designed to enable Ethernet, Serial DSU, and UART functionality on the SBC. The Pod interfaces to
the GEN 6 SBC via the test and development interface connector as shown in Figure 3. A PC can be used to interface through mini USB
and RJ45 ethernet connectors to J3 on the SBC, giving users the ability to run GRMON which allows the capability of loading and running
software, testing the Ethernet interface or even setting up an OS interface such as VxWorks.
Features
10/100 Fast Ethernet
Two Mini USB Ports
User Controlled GPIO
SBC Reset Button
Status LEDs
Figure 3. J3 Interface Pod Configuration and Board Layout.
This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be required prior to
the export of this product from the United States.
Email:
Phone:
Web:
[email protected]
800.645.8862
Cobham.com/HiRel
Aeroflex Colorado Springs Inc., DBA Cobham Semiconductor Solutions, reserves the right to make changes to any products and
services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the
information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising
out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor
does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
958025-000
Version 1.2.0
-3 -
Cobham Semiconductor Solutions
Aeroflex.com/SBC