AX10420
48 Bits DIO Module
User’s Manual
Disclaimers
The information in this manual has been carefully checked and is believed to be accurate.
AXIOMTEK Co., Ltd. assumes no responsibility for any infringements of patents or other
rights of third parties which may result from its use.
AXIOMTEK assumes no responsibility for any inaccuracies that may be contained in this
document. AXIOMTEK makes no commitment to update or to keep current the information
contained in this manual.
AXIOMTEK reserves the right to make improvements to this document and/or product at any
time and without notice.
No part of this document may be reproduced, stored in a retrieval system, or transmitted, in
any form or by any means, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written permission of AXIOMTEK Co., Ltd.
Copyright
1994 by AXIOMTEK Co., Ltd.
All rights reserved.
November 1994, 2nd Edition
Printed in Taiwan
Trademarks Acknowledgments
AXIOMTEK is a trademark of AXIOMTEK Co., Ltd.
IBM is a registered trademark of International Business Machines Corporation.
MS-DOS, Microsoft C and QuickBasic are trademarks of Microsoft Corporation.
TURBO C is a trademark of Borland Inc.
BASIC is a trademark of Dartmouth College.
Intel is a trademark of Intel Corporation.
Other brand names and trademarks are the properties and registered brands of their
respective owners.
ESD Precautions
Integrated circuits on computer boards are sensitive to static electricity. To avoid damaging
chips from electrostatic discharge, observe the following precautions:
! Do not remove boards or integrated circuits from their anti-static packaging until you
are ready to install them.
! Before handling a board or integrated circuit, touch an unpainted portion of the
system unit chassis for a few seconds. This helps to discharge any static electricity
on your body.
! Wear a wrist grounding strap, available from most electronic component stores,
when handling boards and components.
i
Unpacking
The AX10420 is packed in an anti-static bag. The board has components that are easily
damaged by static electricity. Do not remove the anti-static wrapping until proper precautions
have been taken. Safety instructions in front of this User’s Manual describe anti-static
precautions and procedures.
Inventory and Inspection
After unpacking the board, place it on a raised surface and carefully inspect the board for any
damage that might have occurred during shipment. Ground the board and exercise extreme
care to prevent damage to the board from static electricity.
Integrated circuits will sometimes come out of their sockets during shipment. Examine all
integrated circuits, particularly the BIOS, processor and keyboard controller chip to ensure
that they are firmly seated.
The AX10420 48 Bits DIO Module package includes the following:
!
AX10420 Board
!
Screw 3mm (x4)
!
Bronze stick 6mm (x4)
AS59099 DAC Driver CD
Make sure that all of the items listed above are present.
!
What To Do If There Is A Problem
If there are damaged or missing parts, contact your supplier and/or dealer immediately. Do
not attempt to apply power to the board if there is damage to any of its components.
ii
Table of Contents
Chapter 1 Introduction ........................................................................... 1
1.1 General Description.................................................................................................1
1.2 Applications .............................................................................................................1
1.3 Specifications ..........................................................................................................2
1.4 Accessories Guide ..................................................................................................3
Chapter 2 Module Configuration and Installation ............................ 4
2.1 Component Locator Diagram .................................................................................4
2.2 Base Address Switch ..............................................................................................5
2.3 +12V or Ground Selection Jumper.........................................................................6
2.4 IRQ Level Jumper ....................................................................................................7
2.5 Interface Setting Jumper.........................................................................................7
2.6 Connector Pin Assignments...................................................................................9
2.7 Resistor Pack.........................................................................................................10
2.8 Hardware Description............................................................................................11
2.9 Module Installation ................................................................................................11
Chapter 3 Register Structure and Format ........................................ 13
3.1 AX10420 I/O Address Map ....................................................................................13
3.2 AX10420 Register Description..............................................................................14
Chapter 4 Programming........................................................................ 16
4.1 Digital Input and Output........................................................................................16
4.2 Interrupt..................................................................................................................17
Chapter 5 Application............................................................................ 22
5.1 Event Trigger .........................................................................................................22
5.2 Polling 4*4 Keypad ................................................................................................25
Appendix A PC I/O Port Mapping ....................................................... 28
Appendix B Block Diagram .................................................................. 29
Appendix C Technical Reference ........................................................ 30
Appendix D PC/104 Mechanical Specification.................................. 33
AX10420 48 Bits DIO Module User’s Manual
Chapter 1
Introduction
1.1 General Description
The AX10420 is a PC/104 module which is primary intended to PC embedded application in
industrial environment, containing 48-bit digital input and output. It can be used with TTL
low-level input/output circuitry or with solid state relay module such as AX1416 or AX1424
and provides 2500V isolation for interfacing with high level AC and DC signals.
The 48 TTL/DTL/CMOS compatible digital I/O lines are arranged into two separated groups.
Each group supports 8255 PPI (Programmable Peripheral Interface) chip mode 0 but with
stronger driving capability and consists of three 8-bit ports; Port A, Port B, and Port C. These
ports can be functionally programmed as either digital inputs or digital outputs. Of the three
ports, only Port C is further divided into Port C-upper (4-bit) and Port C-lower (4-bit) which can
be independently configured for input or output port.
There is a unique feature associated with AX10420: an interrupt on change of state. Interrupt
occurs when Port C bit 3 or bit 7 of each group changes state. This feature frees up the PC to
do other activities since there is no need to poll the digital input port for an event to occur.
1.2 Applications
!
Sense and control high level signals through I/O module.
!
Sense low-Level (TTL) switches or signals.
!
Drive indicator light or control recorders.
!
Parallel data transfer to PC.
Introduction
1
AX10420 48 Bits DIO Module User’s Manual
1.3 Specifications
Input and Output
!
Input/Output Lines :
48
!
Operation Mode : 8255 MODE 0
!
Input/Output Mode :
!
Interruput Options : Jumper-selectable to level 9(2), 5, 10, 11, 12, or
15
!
Improved Noise Margins :
Pair
Hysteresis
VT+ - VT- = 0.4 typ.
!
Input/Output Level: TTL/DTL compatible
!
Added Pull-up Resistor :
!
Electrical Characteristics
CMOS/dry contact compatible
#
VIH : 2V min.
#
VIL : 0.8V max.
#
IIH : 20uA max. at VI = 2.7V
#
IIL : -0.2mA max. at VIL = 0.4V
#
VOH : 2.4V min at IOH = -3mA
#
VOL : 0.4V max at IOL = 12mA
#
IOH : -15mA max.
#
IOL : 24mA max.
Interface Characteristic
!
I/O Connector : 50-pin male mating connector
!
I/O Cable Type :
#
Ribbon Twisted Pair Cable : ZO = 50Ω to 100Ω typ.
#
Ribbon Stripline Cable : ZO = 30Ω to 80Ω typ.
!
Compatible Bus : PC/104 bus
!
Interface Type : I/O mapped with 10-bit addressing (A9 – A0)
!
Number of Locations Occupied :
!
Data Path : 8 bits
8 consecutive addresses
Power Requirements
!
2
+5V : 0.4A typ.
Introduction
AX10420 48 Bits DIO Module User’s Manual
Physical/Environmental
!
Dimensions : 95mm X 90mm
!
Weight :
!
Operating Temperature Range:
!
Storage Temperature Range: -25oC to 85oC
!
Relative Humidity : To 90%, non-condensing
200g
0oC to 60oC
1.4 Accessories Guide
!
AX751
Screw terminal board for all digital I/O connections. Shipped with 3.3 feet (1
meter) cable and 50-pin connector.
!
AX754
24-channel opto-isolated D/I panel for signal connection and conditioning
with the AX10420. Shipped with 3.3 feet (1 meter) cable and 50-pin
connector.
!
AX755
8-channel
electromechanical
single-pole,
double-throw(SPDT)
and
16-channel opto-isolated digital I/P panel which is compatible with the
AX10420. Shipped with 3.3 feet (1 meter) cable and 50-pin connector.
!
AX756
24-channel electromechanical single-pole, double-throw(SPDT) which can
be driven by the AX10420. Shipped with 3.3 feet (1 meter) cable and 50-pin
connector.
Introduction
3
AX10420 48 Bits DIO Module User’s Manual
Chapter 2
Module Configuration and Installation
2.1 Component Locator Diagram
The following figure shows the location of AX10420’s components. All switch and jumper
settings in this figure are the factory default setting.
J1
50 49
RP1
1
1
2
1
JP2
4
1
JP4
2
1
RP2
RP5
RP3
RP6
9(2)
5
10
11
12
15
X
J5
SW1
ON
1
2
3
4
5
6
7
8
49 50
PC/104 INTERFACE
J2
J4
JP3
1
2
RP4
1
JP1
2
1
J3
40
39
64
63
Module Configuration and Installation
AX10420 48 Bits DIO Module User’s Manual
2.2 Base Address Switch
The AX10420 module occupies 8 consecutive locations in I/O address space. The first
address or base address is selected via a 8-position DIP switch labeled SW1. If more than
one module are to be installed to the embedded system, each module must be given its own
distinct I/O address or base address. No more than one module may use the same base
address. It would be better if you check with Appendix A for I/O port distribution to avoid
conflicting with other installed devices. In factory, the AX10420 base address is set for 220
Hex or 544 Dec.
To set to appropriate base address, switch the individual switches into the ON or OFF
position. The following figure shows DIP switch default setting, 220 Hex, where switches 1
and 5 are moved to the OFF position while leaving all other switches in the ON position. A
table for DIP switch setting is given in the following page.
SW1
O
N
A9 A8 A7 A6 A5 A4 A3
1
2
3
4
5
6
7
X
8
Weighting
8 Dec ( 008 Hex )
16 Dec ( 010 Hex )
32 Dec ( 020 Hex )
64 Dec ( 040 Hex )
128 Dec ( 080 Hex )
256 Dec ( 100 Hex )
512 Dec ( 200 Hex )
NOTE
X : Not used.
Each switch represents one address weight. The desired base address is determined by
adding the weight of the switches flipped at OFF position. The base address calculation is as
follows:
Base Address = 512 + 32 = 544 Dec
= 220 Hex
Module Configuration and Installation
5
AX10420 48 Bits DIO Module User’s Manual
I/O Port Range
DIP Switch Position
1
2
3
4
5
6
7
8
A9
A8
A7
A6
A5
A4
A3
X
200 – 207
1
0
0
0
0
0
0
X
208 – 20F
1
0
0
0
0
0
1
X
210 – 217
1
0
0
0
0
1
0
X
218 – 21F
1
0
0
0
0
1
1
X
220 – 227 (*)
1
0
0
0
1
0
0
X
Hexadecimal
.
.
.
.
.
.
.
.
3F0 – 3F7
1
1
1
1
1
1
0
X
3F8 – 3FF
1
1
1
1
1
1
1
X
NOTE
0 = ON, 1 = OFF,
(*) : Factory default setting
2.3 +12V or Ground Selection Jumper
Group #2
1
JP1
G +12V
Group #1
1
JP3
G +12V
Jumper cap should be placed at pins 1 and 2 of JP1 (JP3) to connect pins 2 and 4 of J1(J4)
connector to Ground. With this configuration, the AX10420 is compatible with AX1416 and
AX1424 Opto-22 interface panels. When jumper cap is placed at pins 2 and 3 of JP1, pins 2
and 4 of J1(J4) connector are connected to +12V. With this configuration, the AX10420 is
compatible with AX754, AX755 and AX756 accessory board. The above figure shows the
factory default setting for JP1 and JP3.
6
Module Configuration and Installation
AX10420 48 Bits DIO Module User’s Manual
2.4 IRQ Level Jumper
Jumper labeled J5 is used for selecting IRQ level (9(2), 5, 10, 11, 12 15). Below figure gives
the jumper configuration and default setting of J5. Place jumper cap at “X” position, if no
interrupt is required.
1
J5
IRQ9
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
X (No connect)
13
2.5 Interface Setting Jumper
AX10420 provides hardware interrupt function for applications. Port C bit 3 (PC3) and bit 7
(PC7) are in charge of the task. INTERRUPT ENABLE (IENx) and PROGRAMMABLE
INTERRUPT(INPx) are selectable via two jumpers. The interrupt signal can be lead to any of
the six interrupt request lines (IRQ level 9(2), 5, 10, 11, 12, 15) by J5 jumper. Below figure
gives the default setting for JP4 and JP2 jumpers.
Group #1
Group #2
EDP
EDP
JP4
NOTE
JP2
D : Disable Interrupt,
E : Enable Interrupt,
P:
!
Programmable Interrupt
Disable Interrupt Jumper (“D” position)
When this jumper is set, any interrupt input on this group will be disabled.
Module Configuration and Installation
7
AX10420 48 Bits DIO Module User’s Manual
!
Enable Interrupt Jumper (“E” position)
When this jumper is set, any change from 0 to 1 on this group’s PC3 will generate an
interrupt. The status is illustrated as follows:
PC3
Interrupt
YES
(*)
NO
NOTE
!
(*) After interrupt immediately pull down PC3,
thus enable other interrupt to happen.
Programmable Interrupt Jumper (“P” position)
When this jumper is set, a programmable interrupt function can be raised via PC3 and
PC7. The status is illustrated as follows:
PC3
NOTE
PC7
Interrupt
0
YES
0
NO
X
1
NO
0
X
NO
1
YES
1
NO
(*)
(**)
(*) After interrupt immediately pull down PC3,
thus enable other interrupt to happen.
(**) After interrupt immediately pull high PC7,
thus enable other interrupt to happen.
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Module Configuration and Installation
AX10420 48 Bits DIO Module User’s Manual
2.6 Connector Pin Assignments
The AX10420’s 48 DI/O lines are divided into two groups; Group #1 and Group #2. The 24
DI/O lines of Group #1 are built in J4 50-pin connector while the 24 DI/O lines of Group #2 are
built in J1 50-pin connector. Both connector pin assignments are the same and shown in
below figure. Through these connectors, the AX10420 module can be directly connected to
AXIOMTEK’s AX751, AX754, AX755 and AX756 accessory boards or standard Opto-22
interface panel.
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OPT
OPT
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
+5V
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3/INT
PC4
PC5
PC6
PC7/INT
Pin Name
Description
+5V
PA0 – PA7
PB0 – PB7
PC0 – PC3
+5V PC power supply
Port A – eight digital I/O lines
Port B – eight digital I/O lines
Port C-lower – four digital I/O lines. The PC3 has interrupt
handling capability. Refer to Interrupt Setting Jumper
section.
Port C-upper – four digital I/O lines. The PC7 has interrupt
handling capability. Refer to Interrupt Setting Jumper
section.
These pins can be connected to +12V PC power or
Ground by jumpering JP1 and JP3. Refer to +12V or
Ground Selection Jumper section.
PC4 – PC7
OPT
Module Configuration and Installation
9
AX10420 48 Bits DIO Module User’s Manual
WARNING
As pin 2 and pin 4 can be connected to +12V or
Ground (refer to +12V or Ground Selection Jumper
section), thus when the AX10420 is connected to
other board through this 50-pin connector, user must
pay attention to the connector pin assignment
(especially pin 2 and pin 4) of the corresponding
board.
2.7 Resistor Pack
As mentioned before the 8-bit port of each group can be configured for input or output port
(refer to Chapter 3). Initially the digital I/O lines are left floating. When any of these ports is
set to input port, user is suggested to pull high it’s input lines by installing RP(s). Onboard
there are six reserved spaces, marked as RP1 – RP6 (refer to below table, the RP is
approximately 4.7K). If a port is configured as output as output lines, just leave the
corresponding RP unoccupied.
NOTE
10
DI/O Lines
RP
Group #1 Port A
RP6
Group #1 Port B
RP5
Group #1 Port C
RP4
Group #2 Port A
RP1
Group #2 Port B
RP2
Group #2 Port C
RP3
In some situations, i.e. environment ground is not
stable, the digital output resets frequently. User is
suggested to isolated system circuitry from external
signal. Let the external signal to go through AX754
(24 Channel Opto-isolated D/I Panel) or AX755 (8
Channel
Relay
Output
and
16
Channel
Opto-isolated D/I panel) before reaching the system
circuitry.
Module Configuration and Installation
AX10420 48 Bits DIO Module User’s Manual
2.8 Hardware Description
PC/104 module can be of two bus types, 8 bit and 16 bit. These correspond to the PC and
PC/AT buses, respectively. The detailed mechanical dimensions of these two PC/104 bus
types are provided in Appendix D.
Basically the AX10420 belongs to 16 bit bus option which design only to by pass PC/AT bus
signal in order to compatible to PC/AT type PC/104 module. The AX10420 uses only IRQ
lines on J3 40-pin connector. If this module is going to plug onto PC type PC/104 bus, do not
use IRQ line above 10.
Besides bus option, there are stackthrough and non-stackthrough difference. The
stackthrough version provides a self-stacking PC bus. It can be placed any where in a
multi-module stack. The non-stackthrough version offers minimum thickness, by omitting bus
stackthrough pins. It must be positioned at one end of a stack.
For convenience, the AX10420 is equipped with stackthrough version only.
NOTE
For safety, you are suggested to cut bus
stackthrough pins of the last module on
condition; that you are sure you won’t add/plug
any module to the module stack in the future.
2.9 Module Installation
The AX10420 board is shipped with protective electrostatic cover. When unpacking, touching
the board electrostatically shielded packaging with the metal frame of your computer to
discharge the accumulated static electricity prior to touching the board.
Following description summarizes the procedures for installing the AX10420:
WARNING
Turn off the PC and all accessories connected to the
PC whenever installing or removing any peripheral
board including the AX10420 module.
Module Configuration and Installation
11
AX10420 48 Bits DIO Module User’s Manual
Installation Procedures:
1. Turn off the system power.
2. Unplug all power cords.
3. Remove the case cover if necessary.
4. Remove the top module if it is a non-stackthrough module.
5. Put the AX10420 module in line with the present module as described in
Appendix D.
6. Install four spacers and fasten them if necessary.
7. Crush between the modules until inside distance is SPACER’s height
(0.6”). Restore all the screws.
8. Repeat step 6 until all modules are set into position.
9. Connect cable to AX10420 (J1 or J4) if necessary.
10.Restore the case cover and connect all the necessary cables.
11.Turn on the system power.
12
Module Configuration and Installation
AX10420 48 Bits DIO Module User’s Manual
Chapter 3
Register Structure and Format
The AX10420 occupies 8 consecutive I/O addresses of PC I/O address space. During
installation, the first address or base address is determined by setting onboard DIP switch
(SW1).
This chapter describes each AX10420 register in terms of function, address, bit structure and
bit function. Each register is easy to read and write to by using direct I/O instructions of
whatever application languages.
3.1 AX10420 I/O Address Map
The 48 digital I/O lines of AX10420 are arranged into separated groups. Each group supports
8255 PPI chip mode 0.
The AX10420 is programmable through configuration registers. By writing to control registers,
the type of each group may be specified. If a group is configured as a write port, the data
driver will drive the data value to the corresponding port. If a group is configured as a read
port, the data value on corresponding port will be sent to the digital I/O lines. Only Port C of
each group is divided into two 4-bit nibbles; Port C-upper and Port C-lower, of which the I/O
direction can be determined by programming to the control register.
The following table lists and describes the registers and their locations (R = Read, W = Write,
Base = Base address).
Location
Function
Type
Base Address +0
Group #1 Port A
R/W
Base Address +1
Group #1 Port B
R/W
Base Address +2
Group #1 Port C
R/W
Base Address +3
Group #1 Control Register
W
Base Address +4
Group #2 Port A
R/W
Base Address +5
Group #2 Port B
R/W
Base Address +6
Group #2 Port C
R/W
Base Address +7
Group #2 Control Register
W
Register Structure and Format
13
AX10420 48 Bits DIO Module User’s Manual
3.2 AX10420 Register Description
Group #1 Data and Control Registers (Base +0 to +3)
!
Port A Data Register (Base +0, R/W)
base
+0
!
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port B Data Register (Base +1, R/W)
base
+1
!
7
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port C Data Register (Base +2, R/W)
base
+2
7
6
5
4
3
2
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC0 – PC3: Port C-lower, PC4 – PC7: Port C-upper
!
Control Register (Base +3, W)
base
7
6
5
4
3
2
1
0
+3
1
0
0
D4
D3
0
D1
D0
Port A
Port C-upper
Port B
Port C-lower
NOTE
1) PA0 – PA7, PB0 – PB7 and PC0 – PC7 bits are
associated to pins at J4 connector.
2) For D0, D1, D3, D4 : 1 → Input, 0 → Output
14
Register Structure and Format
AX10420 48 Bits DIO Module User’s Manual
Group #2 Data and Control Register (Base +4 to +7)
!
Port A Data Register (Base +4, R/W)
base
+4
!
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port B Data Register (Base +5, R/W)
base
+5
!
7
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port C Data Register (Base +6, R/W)
base
+6
7
6
5
4
3
2
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC0 – PC3: Port C-lower, PC4 – PC7: Port C-upper
!
Control Register (Base +7, W)
base
7
6
5
4
3
2
1
0
+7
1
0
0
D4
D3
0
D1
D0
Port A
Port C-upper
Port B
Port C-lower
NOTE
1) PA0 – PA7, PB0 – PB7 and PC0 – PC7 bits are
associated to pins at J1 connector.
2) For D0, D1, D3, D4 : 1 → Input, 0 → Output
Register Structure and Format
15
AX10420 48 Bits DIO Module User’s Manual
Chapter 4
Programming
4.1 Digital Input and Output
AX10420 provides 48-bit digital I/O lines arranged into two groups. Each group contains three
8-bit ports; Port A, B and C. Port C is divided into two 4-bit nibbles; Port C-upper, Port
C-lower. The I/O direction of the ports (Port A, B, C-upper and C-lower) can be determined by
programming to the control register.
Programming Examples
The following BASIC program configures Group #1 Port A and B input port (install
corresponding RP’s), Port C as output port. An increasing pattern is sent to Port C. It is
expected that user will connect both Port A and Port B to Port C before running this program.
10
CLS
20
PORT% = &H220
‘ REM Base address
30
OUT PORT%+3, &H92
‘ REM Port A, B: input, C: output
40
FOR J =0 to 255
‘ REM Decimal value from 00 to FF
50
OUT PORT %+2, J
‘ REM Output data to Port C
60
B = INP (PORT%)
‘ REM Read data on Port A
70
C = INP (PORT%+1)
‘ REM Read data on Port B
80
PRINT B, C, J
‘ REM Check data versus Port A and B
90
NEXT J
100
END
The following program configures Group #1 Port A, B and C as output ports. Data value of 00
to FF Hex are sent to all ports and read back from output latch to ensure that the transfer is
successful.
16
Programming
AX10420 48 Bits DIO Module User’s Manual
10
PORT% = &H220
20
OUT PORT% +3, &H80
30
FOR J = PORT% To PORT% +2 ‘ REM Port A, B, C are all output
40
FOR X=0 to 255
‘ REM Decimal value for Port A to C
50
OUT J, X
‘ REM Decimal value for 00 to FF
Hex
60
B = INP (J)
‘ REM Output value X to port J
70
PRINT X, B, J
‘ REM Read back from latch
80
NEXT X
‘ REM Print input, output value, port
90
NEXT J
100
END
‘ REM Base address
4.2 Interrupt
The AX10420’s built-in interrupt control circuitry allows either Port C PC3 bit or PC7 bit of
each group to cause an interrupt request. The group where interrupt comes from can be
discovered by polling data from each group’s Port C bit 3 and bit 7.
Interrupt can be caused by external input to Port C or by direct output to Port C. This feature
can be used to detect external critical signal or to generate an interrupt from program.
The priority of interrupt is not defined in the interrupt control circuitry, user must define the
priority via software control. Note that the inputs are not latched until the input(read) is
executed.
Programming Examples
Here we provide a demo program written in Turbo C. Before executing this program, Group
#2 PA3 pin must be wired to PC3 pin. This program give a brief description of the interrupt
handling capability of the AX10420. It sets Group #2 Port A for output port and Port C for
input port (install corresponding RP(s) if necessary) and sends 0 followed by 1 to PA3. The
IRQ level selected is IRQ5. If interrupt occurs then shows ‘Interrupt’ on screen. The jumper
configurations are as follows:
EDP
EDP
JP4
JP2
J5
Programming
IRQ9
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
X
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AX10420 48 Bits DIO Module User’s Manual
/* DEMO PROGRAM IN TURBO C */
#include
#include
#include
#define
#define
#define
#define
<dos.h>
<stdio.h>
<conio.h>
intp 0x0d
mimr oxdf
base 0x220
ctr_r 0x89
/* IRQ5 interrupt number */
/* Enable Peripheral Interrupt Controller for IRQ5 */
/* Default base address */
void interrupt (*oldisr)();
void interrupt far newisr();
void restore_isr(void);
int Intolsr;
main()
{
clrscr();
oldisr = getvect(intp);
setvect(intp, newisr);
outp(0x21, inp(0x21)& mimr); /* Enable IRQ5 */
outp(base+7, ctr_r);
/* Set Port A as output, Port C as input */
do {
Introsr=0;
outp(base+4,0x0);
/* Generate a pulse from Port A */
outp(bae+4,0x08);
delay(50);
outp(base+4,0x0);
if (Intolsr==1) {printf(“interrupt\n”);Intolsr=0;}
} while (kbhit()==0);
restore_isr();
/* Free ISR */
outp(0x21,0xb8);
/* Disable IRQ5 */
}
void interrupt far newisr()
{
Intolsr=1;
outp(0x20,0x20);
}
/* ISR routine */
void restore_isr(void)
{
setvect(intp,oldsr);
}
18
Programming
AX10420 48 Bits DIO Module User’s Manual
The following is another demo program written in Turbo Pascal. It is similar to the proceeding
program in Turbo C except here we select Group #1 and IRQ9. The jumpers settings are thus
differ as follows:
EDP
JP2
J5
EDP
JP4
IRQ9
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
X
{ DEMO PROGRAM IN PASCAL }
{$M 1024,0,0}
PROGRAM AX10420_IRQ9_INT;
USES DOS,CRT;
CONST
INTP=$0A;
MIMR=$FB;
BASE=$220;
CTR_R=$89;
VAR
INTOISR:INTEGER;
OLDISR:POINTER;
RKB:CHAR;
{IRQ9}
{Enable peripheral interrupt controller for IRQ9}
{Default base setting}
PROCEDURE NEW_ISR;INTERRUPT;
BEGIN
INTOISR:=1;
PORT[$20]:=$20;
END
BEGIN
GETINTVEC(INTP,OLDISR);
{Get old interrupt vector and save it}
SETINTVEC(INTP,@NEW_ISR);
{Install the new handler}
PORT[$21]:=MIMR AND PORT[$21]; {Enable IRQ9}
PORT[BASE+3]:=CTR_R;
{Set Port A as output, Port C as input}
WRITELN(‘ENTER key to continue, ENTER ESC to end’);
INTOISR:=0;
Programming
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AX10420 48 Bits DIO Module User’s Manual
READ(RKB);
REPEAT
BEGIN
PORT[BASE+0]:=$00;
PORT[BASE+0]:=$08;
PORT[BASE+0]:=$00;
IF INTOISR=1 THEN
BEGIN
WRITELN(‘Interrupt’);
INTOISR:=0;
END;
READ(RKB);
END;
UNTIL(readkey = #27);
SETINTVEC(INTP,OLDISR);
PORT[$21]:=PORT[$21]+8;
END.
{Generate a pulse to trigger interrupt}
{Free interrupt $0b}
{Disable IRQ9}
Here is another demo program in Microsoft C which is similar to the preceeding program in
Turbo C. This program configures Group #2 as output port and write 0 followed by 1 to its
PC3 bit to generate interrupt. The IRQ level selected is IRQ5. Configure the jumpers as
follows:
EDP
EDP
JP4
J5
JP2
IRQ9
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
X
/* DEMO PROGRAM IN MICROSOFT C */
#include <dos.h>
#include <conio.h>
#include <stdio.h>
#define BASE 0x220
20
/* Default base address setting */
Programming
AX10420 48 Bits DIO Module User’s Manual
int pc3_high=0;
static short int_num;
static void *old_int;
void interrupt far isr();
void initiate(void)
/* Initiate interrupt */
{
_disable();
int_num = 0x0d;
/* IRQ5 interrupt number */
old_int = _dos_getvect(int_num); /* Get old interrupt vector and save it */
_dos_setvect(int_num,isr);
/* Install the new handler */
outp(0x21,inp(0x21)&0xdf);
/* Unmask IRQ5 */
_enable();
}
void interrupt far isr(void)
/* Interrupt service routine */
{
_enable();
pc3_high=1;
/* If interrupt occur set pc3_high to 1 */
outp(0x20,0x20);
/* Interrupt completed */
}
void close_int(void)
{
_disable();
_dos_setvect(0xod,old_int);
/* Restore original interrupt vector */
outp(0x21,inp(0x21)|0x20);
/* Mask IRQ5 */
_enable();
}
main()
{
initiate();
outp(BASE+7,0x80);
/* Assign Group #2 as output */
outp(BASE+6,0);
/* Set Group #2:PC3 low */
outp(BASE+6,0x08);
/* Set Group #2:PC3 high */
outp(BASE+6,0);
while (!kbhit())
{
if (pc3_high==1)
{
printf(“Interrupt”);
pc3_high=0;
}
}
close_int();
}
Programming
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Chapter 5
Application
In this chapter, two simple application examples are provided.
5.1 Event Trigger
GROUP #1
PA7
PA6
PA5
1
2
3
4
PA4
5
6
11
12
PA3
PA2
8
PC3
74LS30
PA1
PA0
Configured Group #1 as input port and set jumpers as described in figure below. Install the
corresponding RP(s). If any of the push button is pressed, an interrupt is acknowledged via
PC3. Reading back the data value on Port A will tell us which one of the PA0 through PA7 is
low (pressed down). A demo program in Turbo C is provided in the following page.
EDP
JP2
J5
22
EDP
JP4
IRQ9
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
X
Application
AX10420 48 Bits DIO Module User’s Manual
/* DEMO PROGRAM IN TURBO C FOR EVENT TRIGGER */
#include
#include
#include
<dos.h>
<conio.h>
<stdio.h>
#define BASE 0x220
/* Default base address setting */
static int pc3_high=0;
static short int_num;
static inp PA;
void interrupt far isr();
static void interrupt (*old_int)();
void initiate(void)
{
disable();
int_num = 0x0d;
old_int = getvect(int_num);
setvect(int_num,isr);
outp(0x21;inportb(0x21)&0xdf);
enable();
}
void interrupt far isr(void)
{
enable();
if (pc3_high==0)
{
PA=inp(BASE);
pc3_high=1;
}
outp(0x20,0x20);
}
void close_int(void)
{
disable();
setvect(0x0d,old_int);
outp(0x21,inp(0x21)|0x20;
Application
/* IRQ5 interrupt number */
/* Get old interrupt vector and save it */
/* Install the new handle */
/* Unmask IRQ5 */
/* Read status */
/* If interrupt occur set pc3_high to 1 */
/* Interrupt completed */
/* Restore original interrupt vector */
/* Mask IRQ5 */
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AX10420 48 Bits DIO Module User’s Manual
enable();
}
main()
{
clrscr();
initiate();
outp(BASE+3,0x9B);
while (!kbhit())
{
if (pc3_high==1)
{
if ((PA&0x01)==0)
if ((PA&0x02)==0)
if ((PA&0x04)==0)
if ((PA&0x08)==0)
if ((PA&0x10)==0)
if ((PA&0x20)==0)
if ((PA&0x40)==0)
if ((PA&0x80)==0)
delay(250);
pc3_high=0;
}
}
close_int();
}
24
/* Assign Group#1 as input */
printf(“PA0
printf(“PA1
printf(“PA2
printf(“PA3
printf(“PA4
printf(“PA5
printf(“PA6
printf(“PA7
pressed!
pressed!
pressed!
pressed!
pressed!
pressed!
pressed!
pressed!
“);
“);
“);
“);
“);
“);
“);
“);
Application
AX10420 48 Bits DIO Module User’s Manual
5.2 Polling 4*4 Keypad
4 * 4 KEYPAD
PC0
W
R
PC1
I
T
PC2
E
PC3
PC4
PC5
R
E
PC6
A
PC7
D
Install the corresponding RP(s) to pull high the digital input lines. Configure Group #1 Port
C-upper as read port and Port C-lower as write port. In a loop, send below patterns to Group
#1 Port C:
XXXX 1110
XXXX 1101
XXXX 1011
XXXX 0111
Each time after sending a pattern, check whether keypad is pressed by reading back the data
in Port C-upper. Any 0 value in this 4-bit nibble means keypad is pressed. Then find out the
pressed position. A demo program in Turbo C is provided in the following page.
EDP
JP2, JP4
Application
J5
IRQ9
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
X
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AX10420 48 Bits DIO Module User’s Manual
#include
#include
#include
/* DEMO PROGRAM IN TURBO C FOR POLLING KEYPAD */
<conio.h>
<dos.h>
<stdio.h>
#define BASE 0x220
/* Default base setting */
void re_key(void)
{
int g1_pc;
/* Find which key pressed */
g1_pc=inp(BASE+2);
if (g1_pc & 0x10)== 0)
else if ( (g1_pc & 0x20)== 0)
else if ( (g1_pc & 0x40)== 0)
else if ( (g1_pc & 0x80)== 0)
}
printf(“PC4)
printf(“PC5)
printf(“PC6)
printf(“PC7)
vod main()
{
clrsc();
outp(BASE+3,0x88);
whiel (!kbhit())
{
oupt(BASE+2,0xfe);
if ((inp(BASE+2)>> 4) != 0x0f)
{
printf(“(PC0,”);
re_key();
delay(250);
}
while ((inp(BASE+2)>> 4) != 0x0f;
outp(BASE+2,0xfd);
if ((inp(BASE+2)>> 4) != 0x0f)
{
printf(“(PC1,”);
re_key();
delay(250);
}
26
“);
“);
“);
“);
/* Send pattern 1111 1110 */
/* Check if key pressed */
/* Wait until key released */
/* Send pattern 1111 1101 */
/* Check if key pressed */
Application
AX10420 48 Bits DIO Module User’s Manual
while ((inp(BASE+2)>>4) != 0x0f);
/* Wait until key released */
oupt(BASE+2,0xfb);
if ((inp(BASE+2)>>4) != 0x0f)
{
printf(“(PC2,”);
re_key();
delay(250);
}
while ((inp(BASE+2)>>4) != 0x0f);
/* Send pattern 1111 1011 */
/* Check if key pressed */
outp(BASE+2,0xf7);
if ((inp(BASE+2)>>4) != 0x0f)
{
print(“(pc3,”);
re_key();
delay(250);
}
while ((inp(BASE+2)>>4) != 0x0f);
}
/* Wait until key released */
/* Send pattern 1111 0111 */
/* Check if key pressed */
/* Wait until key released */
}
Application
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AX10420 48 Bits DIO Module User’s Manual
Appendix A
PC I/O Port Mapping
I/O Port Address Range
Function
000 – 1FF
PC reserved
200 – 20F
Game controller (Joystick)
278 – 27F
Second parallel printer port
(LPT2)
2E1
2F8 – 2FF
320 – 32F
378 – 37F
GPIB controller
Second serial port (COM2)
Fixed disk (XT)
380 – 38F
Primary
(LPT1)
parallel
printer
port
3B0 – 3BF
SDLC communication port
3C0 – 3CF
Monochrome adapter/printer
3D0 – 3DF
EGA, reserved
3F0 – 3F7
Color/graphics adapter
3F8 – 3FF
Floppy disk controller
Primary serial port (COM1)
28
PC I/O Port Mapping
AX10420 48 Bits DIO Module User’s Manual
Appendix B
Block Diagram
P
C
/
1
0
4
B
U
S
Block Diagram
Address
Decode Logic
Interrupt
Control Logic
8255
BUF
PA7 - PA0
PB7 - PB0
PC7 - PC4
PC3 - PC0
8255
BUF
PA7 - PA0
PB7 - PB0
PC7 - PC4
PC3 - PC0
INTE
INTP
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Appendix C
Technical Reference
General Usage of Digital Input and Output
Digital signals are usually used for detecting logical status or controlling devices, a brief
description is given below. TTL level signals are developed by most DAS systems.
!
TTL or LSTTL Level I/O Connections
TTL LEVEL I/O CONNECTION
TTL Devices
DO
DI
DGND
Connection with CMOS Device – Use a pull-up resistor if you wish to interface to
CMOS devices. This will raise the logic high output level from its minimum TTL level of
2.4V to +5V suitable for CMOS interface.
VCC
PULL-UP RESISTOR
TTL
30
CMOS
Technical Reference
AX10420 48 Bits DIO Module User’s Manual
Digital Input for Open/Short Switch Detection – A pull-up resistor must be
connected, especially at long distance wiring, to ensure logic high input level.
+5V
4.7K
SS
DI
Switch
SS
!
Digital Input for Large Signal
DI
R
Digital Output for Relay Driving - The D1 diode is added to protect the IC driver
against the inductive “kickback” from the relay coil.
VCC
D1
D0
Technical Reference
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AX10424 Port A, B and C Basic Definition
1. Equivalent ckt of Port A, B and C.
VCC
Line Driver
Internal
Data Bus
D
Data
Write Pulse
Q
Pull High Resistor
74LS244
CLK
74LS273
Control Port
Data
Control Port
Write Pulse
D
50 Pin Connector
PA0 - PA7
PB0 - PB7
PC0 - PC7
Q
CLK
74LS273
Line Receiver
74LS244
READ PULSE
NOTE:
Optional Resistor Pack
< Not Installed in Factory >
2. Any port is programmable to input or output.
3. Outputs are drived by 74LS244 and latched by 74LS273.
4. Inputs are received by 74LS244 but not latched.
5. Interrupt handling capability at PC3 and PC7.
6. All inputs and outputs are buffered by standard line drivers and line
receivers.
7. The initial state and default setting of port A, B and C are tri-state.
32
Technical Reference
AX10420 48 Bits DIO Module User’s Manual
Appendix D
PC/104 Mechanical Specification
PC/104 General Description
While the PC and PC/AT architectures have become extremely popular in both general
purpose (desktop) and dedicated (non-desktop) applications, its use in embedded
microcomputer applications has been limited due to the large size of standard PC and
PC/AT motherboards and expansion cards.
This document supplies the mechanical and electrical specifications for a compact
version of the PC/AT bus, optimized for the unique requirements of embedded systems
applications. The specification is herein referred to as “PC/104”, based on the 104
signal contacts on the two bus connectors (64 pins on J2 plus 40 pins on J3).
Module Dimensions
PC/104 modules can be of two bus types, 8-bit and 16-bit. These correspond to the PC
and PC/AT buses, respectively.
PC/104 Mechanical Specification
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AX10420 48 Bits DIO Module User’s Manual
PC/104 8-Bit Module Dimensions
!
-0.500*
0.350
3.775
0.250 DIA. PAD
0.125 DIA. HOLE 3.250
(4 PLCS.)
0.062
4.050*
3.575
0.100
3.450*
Primary Side
Primary
Side
I/O Connectors May
Overhang Within
These Regions*
(Includes Mating Connectors)
0.500
0.400
*0.325
1
0.100 TYP.
Secondary
Side
0.025 SO.
(TYP.)
0.195
(TYP.)
32
B J1
A
J1
B
B P1
A
A
J1
B
A
0.200
0
0.200
-0.500*
0 0.325* 0.250
3.550
3.350
*0.435
0.420
*3.225
Option 1
Stackthrough Bus
NOTE
Option 2
Non-Stackthrough Bus
Dimensions are in inches ± 0.05.
I/O mating connectors may not extend outside
these boundaries.
34
PC/104 Mechanical Specifcation
AX10420 48 Bits DIO Module User’s Manual
!
PC/104 16-Bit Module Dimensions
-0.500*
0.250 DIA. PAD
0.125 DIA. HOLE
(4 PLCS.)
0.350
3.775
3.250
0.062
4.050*
3.575
0.100
3.450*
Primary Side
Primary
Side
I/O Connectors May
Overhang Within
These Regions*
(Includes Mating Connectors)
0.500
0.400
0.300
*0.325 0
1
0.100 TYP.
Secondary
Side
0.025 SO.
(TYP.)
0.195
(TYP.)
0.100 TYP.
32
1
J2
0.200
B J1
A
C
D
3.550
3.350
0.200
-0.500*
B
J1 A
C
J2 D
*0.435
B P1
A
C P2
D
B
J1 A
C
J2 D
0.420
0 0.325* 0.950*
0.250
NOTE
Option 1
Stackthrough Bus
Option 2
Non-Stackthrough Bus
Dimensions are in inches ± 0.05.
I/O mating connectors may not extend outside
these boundaries.
PC/104 Mechanical Specification
35
AX10420 48 Bits DIO Module User’s Manual
!
Typical Module Stack
Figure 1 illustrates a typical module stack of 8-bit modules, and shows the use of the
“stack-through” and “non-stackthrough” J2 bus connector options.
Stackthrough
8-bit module
0.6" Spacers(4 plcs.)
Stackthrough
16-bit module
0.6" Spacers(4 plcs.)
Non-Stackthrough
16-bit module
0.435"
(Approx.)
2.0"
0.6"
0.6"
Figure 1 Typical Module Stack
36
PC/104 Mechanical Specifcation